CN113851530A - Fin-type semiconductor device and method of making the same - Google Patents
Fin-type semiconductor device and method of making the same Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000002360 preparation method Methods 0.000 claims abstract description 3
- 230000004888 barrier function Effects 0.000 claims description 84
- 239000000463 material Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 18
- 238000001039 wet etching Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 230000003247 decreasing effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明提供了一种鳍式半导体器件及其制备方法，包括：衬底；介质层，位于所述衬底上；以及，若干鳍片，间隔排布在所述衬底上，每个所述鳍片从所述衬底向上贯穿所述介质层后继续向上延伸，且所述鳍片包括从下至上的第一部分、第二部分及第三部分，其中，所述第一部分位于所述介质层中，所述第二部分及所述第三部分均位于所述介质层上，所述第三部分的侧壁的一部分向内凹陷以使所述第三部分对应凹陷部位的横向宽度减小；本发明减小了鳍式半导体器件短沟道效应，改善漏电现象，提高了鳍式半导体器件的电性能。
The present invention provides a fin-type semiconductor device and a preparation method thereof, comprising: a substrate; a dielectric layer, located on the substrate; and a plurality of fins, arranged on the substrate at intervals, each of the The fins extend upward from the substrate upward through the dielectric layer, and the fins include a first part, a second part and a third part from bottom to top, wherein the first part is located in the dielectric layer wherein, the second portion and the third portion are both located on the dielectric layer, and a portion of the sidewall of the third portion is recessed inward to reduce the lateral width of the corresponding recessed portion of the third portion; The invention reduces the short channel effect of the fin-type semiconductor device, improves the leakage phenomenon, and improves the electrical performance of the fin-type semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a fin type semiconductor device and a manufacturing method thereof.
Background
A Fin Field effect transistor (FinFET) is a complementary metal oxide semiconductor Field effect transistor, and includes a vertical channel structure, also called a Fin, where two sides and a top of the Fin are surrounded by a gate structure, and the FinFET structure makes the device smaller and has higher performance, and the Fin semiconductor device is widely used in the Field of memory and logic devices. In the case of the reduced size of the FinFET structure, the height of the fin is required to be increased and the sidewall of the fin is required to be straighter, and the fin is expected to form a "tall and thin" shape, and particularly, the size of the bottom of the fin surrounded by the gate structure is required to be smaller, so as to improve the control capability of the gate structure on the channel current, reduce the leakage current of the device, and thus improve the electrical performance of the device. In the prior art, when a fin is formed, the side wall of the fin is inclined, the bottom of the fin is wide, and the top of the fin is narrow due to the influence of an etching process.
Disclosure of Invention
The invention aims to provide a fin type semiconductor device and a manufacturing method thereof, and aims to improve the electrical property of the fin type semiconductor device.
In order to achieve the above object, the present invention provides a fin-type semiconductor device, including:
a substrate;
the dielectric layer is positioned on the substrate; and the number of the first and second groups,
the fin structure comprises a plurality of fins which are arranged on a substrate at intervals, wherein each fin penetrates through a dielectric layer from the substrate upwards and then continues to extend upwards, the fins comprise a first part, a second part and a third part from bottom to top, the first part is located in the dielectric layer, the second part and the third part are both located on the dielectric layer, and one part of the side wall of the third part is inwards recessed so that the transverse width of the corresponding recessed part of the third part is reduced.
Optionally, the bottom of the recessed portion of the third portion coincides with the top of the second portion.
Optionally, the vertical height of the fin is 110nm to 140 nm.
Optionally, the sum of the vertical heights of the second portion and the third portion is 50nm to 60nm, the vertical height of the second portion is 2nm to 5nm, and the vertical height of the recessed portion of the third portion is 10nm to 20 nm.
A method for manufacturing a fin type semiconductor device comprises the following steps:
providing a substrate; and the number of the first and second groups,
forming a plurality of fins and a dielectric layer on the substrate, wherein the fins are arranged on the substrate at intervals, each fin penetrates through the dielectric layer from the substrate upwards and then continues to extend upwards, the fins comprise a first part, a second part and a third part from bottom to top, the first part is located in the dielectric layer, the second part and the third part are located on the dielectric layer, and one part of the side wall of the third part is inwards recessed so that the transverse width of the third part corresponding to the recessed part is reduced.
Optionally, the step of forming the plurality of fins and the dielectric layer includes:
etching the substrate to form a plurality of grooves, wherein the part of the substrate, which is positioned between two adjacent grooves, forms the fin;
filling the dielectric layer in partial depth of the groove to enable the top of the dielectric layer to be flush with the top of the first part;
forming a first barrier layer on the dielectric layer, wherein the top of the first barrier layer is flush with the top of the second part, and forming a second barrier layer on partial side walls of the third part; and the number of the first and second groups,
and transversely etching the third part by taking the first barrier layer and the second barrier layer as etching barrier layers so as to enable a part of the side wall of the third part to be inwards recessed.
Optionally, when the first barrier layer is formed, a sacrificial layer is simultaneously formed on the first barrier layer, the sacrificial layer covers a part of the sidewall of the third portion, and the second barrier layer is formed on the remaining sidewall of the third portion.
Optionally, after forming the second barrier layer on the remaining sidewall of the third portion, removing the sacrificial layer is further included.
Optionally, the step of forming the first barrier layer and the sacrificial layer includes:
forming the first barrier material layer on the dielectric layer, wherein the first barrier material layer covers the dielectric layer, the second part and the outer wall of the third part;
forming a first sub-sacrificial layer on the first barrier layer;
removing the first barrier material layer on the outer wall of the third part by adopting a wet etching process, wherein the remaining first barrier material layer forms the first barrier layer; and the number of the first and second groups,
forming a second sub-sacrificial layer on the first sub-sacrificial layer, the second sub-sacrificial layer covering the first sub-sacrificial layer and filling a gap between the first sub-sacrificial layer and the third portion, the first sub-sacrificial layer and the second sub-sacrificial layer forming the sacrificial layer.
Optionally, the first barrier layer and the second barrier layer are made of silicon nitride, and the sacrificial layer is made of silicon oxide.
In the fin type semiconductor device and the preparation method thereof provided by the invention, the dielectric layer is positioned on the substrate; the fins are arranged on the substrate at intervals, each fin penetrates through the dielectric layer from the substrate upwards and then continues to extend upwards, and each fin comprises a first part, a second part and a third part from bottom to top, wherein the first part is located in the dielectric layer, the second part and the third part are both located on the dielectric layer, and one part of the side wall of the third part is inwards recessed so that the transverse width of the corresponding recessed part of the third part is reduced; in the invention, the second part and the third part are used as channel structures of devices, a gate structure formed in a subsequent process can surround the second part and the third part, the side wall of the fin is inclined due to the influence of an etching process, the bottom of the fin is wide, the top of the fin is narrow, the lateral width of one part of the side wall of the third part is reduced, one part of the side wall of the third part is recessed inwards, the lateral width of one part of the side wall of the channel structure is reduced, the control capability of the gate structure on channel current can be improved, the leakage current of the devices is reduced, and the electrical property of the fin type semiconductor devices is improved.
Drawings
Fig. 1 is a flowchart illustrating a method for fabricating a fin-type semiconductor device according to an embodiment of the present invention;
fig. 2A to 2J are schematic cross-sectional views illustrating corresponding steps in a method for fabricating a fin-type semiconductor device according to an embodiment of the invention, wherein fig. 2J is a schematic cross-sectional view illustrating the fin-type semiconductor device according to the embodiment of the invention;
wherein the reference numerals are:
10-a substrate; 11-fins; 111-a first part; 112-a second portion; 113-a third portion; 20-a dielectric layer; 311-a first barrier material layer; 31-a first barrier layer; 321-a second barrier material layer; 32-a second barrier layer; 40-a sacrificial layer; 41-a first sub-sacrificial layer; 42-second sub-sacrificial layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2J is a schematic cross-sectional view of the fin-type semiconductor device according to the present embodiment. Referring to fig. 2J, the fin-type semiconductor device of the present embodiment includes a substrate 10, a dielectric layer 20 and a plurality of fins 11, wherein the dielectric layer 20 is disposed on the substrate 10, in the present embodiment, the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon, and the material of the dielectric layer 20 may be silicon oxide, but is not limited thereto.
A plurality of fins 11 are arranged on the substrate 10 at intervals, each fin 11 penetrates the dielectric layer 20 from the substrate 10 upwards and then extends upwards, the fin 11 includes a first portion 111, a second portion 112 and a third portion 113 from bottom to top, and the first portion 111, the second portion 112 and the third portion 113 are of an integral structure. The first portion 111 is located in the dielectric layer 20, the second portion 112 and the third portion 113 are both located on the dielectric layer 20, and a portion of a sidewall of the third portion 113 is recessed inward so that a lateral width of a recessed portion corresponding to the third portion 113 is reduced.
In this embodiment, since the second portion 112 and the third portion 113 serve as channel structures of devices, gate structures formed in a subsequent process surround the second portion 112 and the third portion 113, and in order to make sidewalls of the fin 11 straighter and expect the fin 11 to have a "slim" profile, it is required that a bottom of the fin 11 surrounded by the gate structures is smaller in size, and therefore, it is preferable that a bottom of a recessed portion of the third portion 113 coincides with a top of the second portion 112, so that a lateral width of a portion of the third portion 113 closer to the second portion 112 is smaller, but not limited to this structure position.
In this embodiment, the vertical height of the fin 11 is 110nm to 140nm, the sum of the vertical heights of the second portion 112 and the third portion 113 is 50nm to 60nm, the vertical height of the second portion 112 is 2nm to 5nm, and the vertical height of the recessed portion of the third portion 113 is 10nm to 20nm, but not limited to the above-mentioned height range, which is determined by practical conditions.
In this embodiment, due to the influence of the etching process, the sidewall of the fin 11 is inclined, and has a wide bottom and a narrow top, that is, the lateral widths of the first portion 111, the second portion 112, and the third portion 113 are gradually reduced to have a wide bottom and a narrow top, so that after the lateral width of a portion of the sidewall of the third portion 113 is reduced, a portion of the sidewall of the third portion 113 is recessed inwards, and the lateral width of a portion of the sidewall of the channel structure is reduced, which can improve the control capability of the gate structure on the channel current, reduce the leakage current of the device, and thereby improve the electrical performance of the fin-type semiconductor device.
Fig. 1 is a flowchart of a method for manufacturing a fin-type semiconductor device according to this embodiment. Referring to fig. 1, the method for fabricating the fin-type semiconductor device includes:
step S1: providing a substrate; and the number of the first and second groups,
step S2: forming a plurality of fins and a dielectric layer on the substrate, wherein the fins are arranged on the substrate at intervals, each fin penetrates through the dielectric layer from the substrate upwards and then continues to extend upwards, the fins comprise a first part, a second part and a third part from bottom to top, the first part is located in the dielectric layer, the second part and the third part are located on the dielectric layer, and one part of the side wall of the third part is inwards recessed so that the transverse width of the third part corresponding to the recessed part is reduced.
Fig. 2A to 2J are schematic cross-sectional views illustrating corresponding steps of a method for fabricating a fin-type semiconductor device according to this embodiment, and the method for fabricating a fin-type semiconductor device according to this embodiment is described in detail with reference to fig. 2A to 2J.
Referring to fig. 2A, step S1 is executed to provide the substrate 10, a material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen, or carbon, and a thickness of the substrate 10 is required to satisfy a certain requirement, so as to form a plurality of fins in the substrate 10 later.
With reference to fig. 2A, step S2 is executed to etch the substrate 10 to form a plurality of trenches spaced apart from each other in the substrate 10, a portion of the substrate 10 located between two adjacent trenches constitutes the fin 11, and the fin 11 includes the first portion 111, the second portion 112, and the third portion 113 from bottom to top. In the present embodiment, the depth of the trench may be 110nm to 140nm, that is, the vertical height of the fin 11 may be 110nm to 140nm, but is not limited to this height range, which is determined by the actual situation. After the substrate 10 is etched to form the trenches, the sidewalls of the fin 11 are inclined, the lateral width of the bottom of the fin 11 is greater than the lateral width of the top of the fin 11, that is, the lateral width of the bottom of the first portion 111 is greater than the lateral width of the top of the third portion 113, and the lateral widths of the first portion 111, the second portion 112, and the third portion 113 are gradually decreased.
With continued reference to fig. 2A, the dielectric layer 20 is filled in a partial depth of the trench, and the top of the dielectric layer 20 is flush with the top of the first portion 111. Specifically, the dielectric layer 20 is filled in the trench, so that the surface of the dielectric layer 20 is higher than the top of the trench, the surface of the dielectric layer 20 is flattened through chemical mechanical polishing, and then the dielectric layer 20 is etched so that the top of the dielectric layer 20 is lower than the top of the trench. In the present embodiment, the material of the dielectric layer 20 may be silicon oxide, but is not limited thereto.
The depth of the dielectric layer 20 filling the trench may be 60nm to 90nm, that is, the vertical height of the first portion 111 may be 60nm to 90nm, but is not limited to this depth range. After a gate structure is formed in a subsequent process, the gate structure surrounds the portion of the fin 11 not covered by the dielectric layer 20, that is, the gate structure covers the outer walls of the second portion 112 and the third portion 113, which requires that the second portion 112 and the third portion 113 form a "thin" shape; the vertical heights of the second portion 112 and the third portion 113 can be adjusted by adjusting the depth of the trench filled with the dielectric layer 20, and the dielectric layer 20 covers part of the side wall of the fin 11, so that the fin 11 is not easily broken or collapsed when the size of the fin 11 is reduced by subsequent etching, and the manufacturing yield of the device can be improved.
Further, a first barrier layer 31 is formed on the dielectric layer 20, and when the first barrier layer 31 is formed, a sacrificial layer 40 is also formed on the first barrier layer 31, and the sacrificial layer 40 covers a part of the sidewall of the third portion 113, specifically, the steps are as follows:
referring to fig. 2B, the first blocking material layer 311 is formed on the dielectric layer 20, and the first blocking material layer 311 covers the outer walls of the dielectric layer 20, the second portion 112 and the third portion 113.
Referring to fig. 2C, a first sub-sacrificial layer 41 is formed on the first barrier material layer 311, specifically, the first sub-sacrificial layer 41 fills the trench and the surface of the first sub-sacrificial layer 41 is higher than the top of the trench, the top of the first sub-sacrificial layer 41 is planarized by chemical mechanical polishing, and then the first sub-sacrificial layer 41 is etched back to make the top of the first sub-sacrificial layer 41 lower than the top of the trench, i.e., the first sub-sacrificial layer 41 is formed on the first barrier material layer 311.
Referring to fig. 2D, a wet etching process is used to remove the first barrier material layer 311 on the outer wall of the third portion 113, and the remaining first barrier material layer 311 forms the first barrier layer 31. Since the first sub-sacrificial layer 41 covers the first barrier material layer 311, the first sub-sacrificial layer 41 protects the covered first barrier material layer 311 during wet etching, after wet etching, the remaining first barrier material layer 311 forms the first barrier layer 31, the top of the first barrier layer 31 is flush with the top of the second portion 112, and a gap (shown in a circular dashed box in the figure) is formed between the first sub-sacrificial layer 41 and the third portion 113, and the gap affects etching of the fin 11 in a subsequent process. In the present embodiment, the first barrier material layer 311 is formed by a chemical vapor deposition process, but is not limited to this process; the material of the first barrier material layer 311 may be silicon nitride, but is not limited thereto. In the wet etching process, a phosphoric acid solution can be used for etching and removing the first barrier material layer 311 on the outer wall of the third portion 113, and since the etching rate of the phosphoric acid solution is low, the etching amount of the first barrier material layer 311 can be controlled by controlling the wet etching time, so that the remaining first barrier material layer 311 is formedThe first barrier layer 31, the top of the first barrier layer 31 is flush with the top of the second portion 112; and the first barrier layer 31 has a thickness of
But is not limited to this thickness range.
Referring to fig. 2E, a second sub-sacrificial layer 42 is formed on the first sub-sacrificial layer 41, and the second sub-sacrificial layer 42 covers the first sub-sacrificial layer 41 and fills a gap between the first sub-sacrificial layer 41 and the third portion 113. Specifically, the surface of the second sub-sacrificial layer 42 is higher than the top of the trench, the top of the second sub-sacrificial layer 42 is planarized by chemical mechanical polishing, the second sub-sacrificial layer 42 is etched back, the second sub-sacrificial layer 42 with a partial thickness is remained, the second sub-sacrificial layer 42 covers a partial sidewall of the third portion 113, and the first sub-sacrificial layer 41 and the second sub-sacrificial layer 42 constitute the sacrificial layer 40.
In the present embodiment, the sacrificial layer 40 is formed by a chemical vapor deposition process, but is not limited to this process; the second sub-sacrificial layer 42 and the first sub-sacrificial layer 41 are made of the same material, and the sacrificial layer 40 may be made of silicon oxide, but is not limited thereto; the sacrificial layer 40 has a thickness of
But is not limited to this thickness range.
Further, a second barrier layer 32 is formed on a portion of the sidewall of the third portion 113, and the specific steps are as follows:
referring to fig. 2F, the second barrier material layer 321 is formed on the sacrificial layer 40 and the remaining outer wall of the third portion 113 by a chemical vapor deposition process, and the second barrier material layer 321 extends to cover the surface of the sacrificial layer 40. In this embodiment, the material of the second barrier material layer 321 may be silicon nitride, and the thickness of the second barrier material layer 321 is
But is not limited to this range of materials and thicknesses.
Referring to fig. 2G, a dry etching process is used to remove the surface of the sacrificial layer 40 and the second barrier material layer 321 on the top of the third portion 113, and the remaining second barrier material layer 321 forms the second barrier layer 32. The formation of the first barrier layer 31 on the dielectric layer 20 is achieved by the previous steps, the top of the first barrier layer 31 is flush with the top of the second portion 112, and the second barrier layer 32 is formed on a portion of the sidewalls of the third portion 113.
Further, referring to fig. 2H, after forming the second barrier layer 32 on a portion of the sidewall of the third portion 113, the sacrificial layer 40 is removed by using a wet etching process, wherein an etchant of the wet etching process may use hydrofluoric acid, but is not limited to this etchant. Although the dielectric layer 20 and the sacrificial layer 40 are made of silicon oxide, the dielectric layer 20 can be prevented from being affected during wet etching due to the existence of the first barrier layer 31. After removing the sacrificial layer 40, a portion of the sidewalls of the third portion 113 is exposed.
Referring to fig. 2I, the third portion 113 is laterally etched by using the first barrier layer 31 and the second barrier layer 32 as etching barrier layers by using a dry etching process, so that a portion of a sidewall of the third portion 113 is recessed inward. In particular using CF4And etching by the mixed gas to reduce the lateral width of a part of the sidewall of the third portion 113, and controlling the etching amount of the part of the sidewall of the third portion 113 by controlling the etching parameters of the dry etching process, wherein the positions indicated by the two arrows in the figure are the etching positions of the third portion 113. After the third portion 113 is etched, a part of the side wall of the third portion 113 is recessed inwards, the lateral width of the partial side wall of the channel structure is reduced, the control capability of the gate structure on channel current can be improved, the leakage current of the device is reduced, and therefore the electrical performance of the fin type semiconductor device is improved.
Referring to fig. 2J, after the third portion 113 is laterally etched by using the first barrier layer 31 and the second barrier layer 32 as etch barrier layers, the method further includes removing the first barrier layer 31 and the second barrier layer 32 by using a wet etching process, where an etchant of the wet etching process may use phosphoric acid, but is not limited to this etchant, which is determined by the actual situation.
In summary, in the fin-type semiconductor device and the method for manufacturing the same provided by the invention, the dielectric layer is located on the substrate; the fins are arranged on the substrate at intervals, each fin penetrates through the dielectric layer from the substrate upwards and then continues to extend upwards, and each fin comprises a first part, a second part and a third part from bottom to top, wherein the first part is located in the dielectric layer, the second part and the third part are both located on the dielectric layer, and one part of the side wall of the third part is inwards recessed so that the transverse width of the corresponding recessed part of the third part is reduced; in the invention, the second part and the third part are used as channel structures of devices, a gate structure formed in a subsequent process can surround the second part and the third part, the side wall of the fin is inclined due to the influence of an etching process, the bottom of the fin is wide, the top of the fin is narrow, the lateral width of one part of the side wall of the third part is reduced, one part of the side wall of the third part is recessed inwards, the lateral width of one part of the side wall of the channel structure is reduced, the control capability of the gate structure on channel current can be improved, the leakage current of the devices is reduced, and the electrical property of the fin type semiconductor devices is improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
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| CN202111045910.8A CN113851530B (en) | 2021-09-07 | 2021-09-07 | Fin type semiconductor device and preparation method thereof |
| PCT/CN2021/143034 WO2023035508A1 (en) | 2021-09-07 | 2021-12-30 | Fin-type semiconductor device and preparation method therefor |
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| CN202111045910.8A CN113851530B (en) | 2021-09-07 | 2021-09-07 | Fin type semiconductor device and preparation method thereof |
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