CN113851178A

CN113851178A - SRAM memory cell

Info

Publication number: CN113851178A
Application number: CN202111151658.9A
Authority: CN
Inventors: 刘中阳; 杨光华; 潘炯
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2021-12-28

Abstract

The invention discloses an SRAM storage unit, comprising: a pair of Schmitt inverters composed of a first Schmitt inverter and a second Schmitt inverter. The input end of the first Schmitt inverter is connected to the output end of the second Schmitt inverter, and the output end of the first Schmitt inverter is connected to the input end of the second Schmitt inverter. The hysteresis effect of the Schmitt inverter is used to improve the noise tolerance of the SRAM memory cell. The present invention can improve noise tolerance.

Description

SRAM memory cell

Technical Field

The present invention relates to semiconductor integrated circuits, and more particularly, to an SRAM memory cell.

Background

The advances in integrated circuit technology nodes present many challenges to chip reliability, one of which is the impact of process variations on circuit performance.

The noise tolerance of the existing 6-transistor, i.e. 6T type SRAM memory cell is not large enough, and a memory cell with larger noise tolerance is needed.

As shown in fig. 1, the circuit diagram of the conventional 6T-type SRAM memory cell is shown, where the conventional 6T-type SRAM memory cell includes a CMOS circuit formed by an NMOS transistor N101 and a PMOS transistor P101, an interlock structure formed by alternately connecting the input and the output of the CMOS circuit formed by an NMOS transistor N102 and a PMOS transistor P102, and further includes pass transistors, which are NMOS transistors N103 and N104, respectively. In fig. 1, node Q is connected to bit line BL through NMOS transistor N103, and node QN is connected to bit line BLB through NMOS transistor N104; the gates of the NMOS transistors N103 and N104 are connected to a word line WL.

As shown in fig. 2, it is a circuit diagram of a conventional Stack (Stack) type SRAM memory cell; the two circuits with input and output interlocking connection are respectively a first stack phase inverter formed by connecting NMOS transistors N101 and N102 and PMOS transistors P101 and P102 and a second stack phase inverter formed by connecting NMOS transistors N103 and N104 and PMOS transistors P103 and P104. The device also comprises transmission tubes which are NMOS tubes N105 and N106 respectively. In fig. 1, node Q is connected to bit line BL through NMOS transistor N105, and node QN is connected to bit line BLB through NMOS transistor N106; the gates of NMOS transistors N105 and N106 are connected to word line WL.

Disclosure of Invention

The invention aims to provide an SRAM memory cell, which can improve the noise tolerance.

In order to solve the above technical problem, the SRAM memory cell provided in the present invention includes: a pair of Schmitt inverters consisting of a first Schmitt inverter and a second Schmitt inverter.

The input end of the first Schmitt phase inverter is connected with the output end of the second Schmitt phase inverter, and the output end of the first Schmitt phase inverter is connected with the input end of the second Schmitt phase inverter.

The hysteresis effect of the Schmitt inverter is utilized to improve the noise tolerance of the SRAM storage unit.

In a further refinement, the first schmitt inverter includes: the first stack inverter is connected with the first hysteresis circuit.

The first hysteresis circuit includes a first pull-down hysteresis path and a first pull-up hysteresis path.

The first stack phase inverter is formed by connecting a first pull-up stack path and a first pull-down stack path, the first pull-up stack path is formed by connecting a plurality of PMOS (P-channel metal oxide semiconductor) tubes in series, the first pull-down stack path is formed by connecting a plurality of NMOS (N-channel metal oxide semiconductor) tubes in series, and the grid electrode of each PMOS tube of the first pull-up stack path and the grid electrode of each NMOS tube of the first pull-down stack path are connected together and used as the input end of the first Schmidt phase inverter.

The junction of the first pull-up stack path and the first pull-down stack path forms an output of the first schmitt inverter.

The first pull-down hysteresis path is formed by connecting more than one PMOS tube in series, and the first pull-up hysteresis path is formed by connecting more than one NMOS tube in series.

The grid electrode of the PMOS tube of the first pull-down hysteresis path and the grid electrode of the NMOS tube of the first pull-up hysteresis path are both connected with the output end of the first Schmidt inverter.

The first pull-down hysteresis path is connected in series between a connection node between the PMOS transistors of the first pull-up stack path and ground.

The first pull-up hysteresis path is connected in series between a connection node between the NMOS transistors of the first pull-down stack path and a supply voltage.

In a further improvement, the first pull-up stack path is formed by two PMOS tubes connected in series.

In a further improvement, the first pull-down stack path is connected in series by two NMOS transistors.

In a further improvement, the first pull-down hysteresis path is composed of a PMOS transistor.

In a further improvement, the first pull-up hysteresis path is composed of an NMOS transistor.

In a further refinement, the second schmitt inverter includes: the second stacked inverter is connected with the second hysteresis circuit.

The second hysteresis circuit includes a second pull-down hysteresis path and a second pull-up hysteresis path.

The second stack phase inverter is formed by connecting a second pull-up stack path and a second pull-down stack path, the second pull-up stack path is formed by connecting a plurality of PMOS tubes in series, the second pull-down stack path is formed by connecting a plurality of NMOS tubes in series, and the grid electrode of each PMOS tube of the second pull-up stack path and the grid electrode of each NMOS tube of the second pull-down stack path are connected together and serve as the input end of the second Schmidt phase inverter.

The junction of the second pull-up stack path and the second pull-down stack path forms an output of the second schmitt inverter.

The second pull-down hysteresis path is formed by connecting more than one PMOS tube in series, and the second pull-up hysteresis path is formed by connecting more than one NMOS tube in series.

The grid electrode of the PMOS tube of the second pull-down hysteresis path and the grid electrode of the NMOS tube of the second pull-up hysteresis path are both connected with the output end of the second Schmitt inverter.

The second pull-down hysteresis path is connected in series between a connection node between the PMOS transistors of the second pull-up stack path and ground.

The second pull-up hysteresis path is connected in series between a connection node between the NMOS transistors of the second pull-down stack path and a supply voltage.

In a further improvement, the second pull-up stack path is formed by connecting two PMOS tubes in series.

In a further improvement, the second pull-down stack path is formed by connecting two NMOS transistors in series.

In a further improvement, the second pull-down hysteresis path is composed of a PMOS transistor.

In a further improvement, the second pull-up hysteresis path is composed of an NMOS transistor.

In a further improvement, the SRAM memory cell further comprises a pair of pass transistors.

The first transmission pipe is connected between the input end of the first Schmitt phase inverter and the first bit line.

The second transmission tube is connected between the output end of the first Schmitt inverter and the second bit line.

And the grid electrode of the first transmission tube and the grid electrode of the second transmission tube are both connected with a word line.

In a further improvement, the first transmission tube is composed of an NMOS tube, and the second transmission tube is composed of an NMOS tube.

In a further improvement, the first transmission pipe is composed of a PMOS pipe, and the second transmission pipe is composed of a PMOS pipe.

In a further improvement, an SRAM memory array is formed by ordering a plurality of SRAM memory cells.

The interlocking two inverters of the SRAM memory cell of the invention both adopt Schmitt inverters, and the Schmitt inverters have hysteresis effect, so that the input end and the output end of the SRAM memory cell can be switched from 0 to 1 and from 1 to 0 by using the hysteresis effect of the Schmitt inverters, and the inversion is not easy to realize when the input end or the output end of the SRAM memory cell generates Noise, so that the invention can improve the Noise tolerance.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a circuit diagram of a prior art 6T SRAM cell;

FIG. 2 is a circuit diagram of a conventional stack-type SRAM memory cell;

FIG. 3 is a circuit diagram of an SRAM memory cell according to an embodiment of the present invention;

FIG. 4 is a simulation waveform of the normal operation of an SRAM memory cell in accordance with an embodiment of the present invention;

FIG. 5A is a simulation diagram of RSNM of the prior art 6T SRAM memory cell shown in FIG. 1;

FIG. 5B is a simulation diagram of HSNM of the prior art 6T type SRAM memory cell shown in FIG. 1;

FIG. 6A is a simulation diagram of RSNM of the conventional stack-type SRAM memory cell shown in FIG. 2;

FIG. 6B is a simulation diagram of HSNM of the prior art stack SRAM memory cell of FIG. 2;

FIG. 7A is a simulation diagram of RSNM of the SRAM memory cell of the embodiment of the invention shown in FIG. 3;

FIG. 7B is a simulation diagram of HSNM of the SRAM memory cell of the embodiment of the invention shown in FIG. 3.

Detailed Description

FIG. 3 is a circuit diagram of an SRAM memory cell according to an embodiment of the present invention; the SRAM memory cell of the embodiment of the invention comprises: and a pair of Schmitt inverters consisting of a first Schmitt inverter and a second Schmitt inverter.

The first Schmitt inverter includes: the first stack inverter is connected with the first hysteresis circuit.

In the embodiment of the present invention, the first pull-up stack path is formed by connecting two PMOS transistors in series, and in fig. 3, the two PMOS transistors of the first pull-up stack path are PMOS transistors P303 and P304, respectively.

The first pull-down stack path is formed by connecting two NMOS transistors in series, and in fig. 3, the two NMOS transistors of the first pull-down stack path are NMOS transistors N303 and N304, respectively.

The first pull-down hysteresis path is composed of a PMOS tube. In fig. 3, the PMOS transistor of the first pull-down hysteresis path is a PMOS transistor P306.

The first pull-up hysteresis path is composed of an NMOS tube. In fig. 3, the NMOS transistor of the first pull-up hysteresis path is NMOS transistor N306.

The second Schmitt inverter includes: the second stacked inverter is connected with the second hysteresis circuit. In the embodiment of the present invention, the structure of the second schmitt inverter is the same as that of the first schmitt inverter, but the corresponding labels of the transistors of the second schmitt inverter are separately marked in fig. 3.

The second pull-up stack path is formed by connecting two PMOS tubes in series. In fig. 3, the two PMOS transistors of the second pull-up stack path are PMOS transistors P301 and P302, respectively.

The second pull-down stack path is formed by connecting two NMOS tubes in series. In fig. 3, the two NMOS transistors of the second pull-down stack path are NMOS transistors N301 and N302, respectively.

The second pull-down hysteresis path is composed of a PMOS tube. In fig. 3, the PMOS transistor of the second pull-down hysteresis path is a PMOS transistor P305.

The second pull-up hysteresis path is composed of an NMOS tube. In fig. 3, the NMOS transistor of the second pull-up hysteresis path is an NMOS transistor N305.

The SRAM memory cell further includes a pair of pass transistors.

The first transfer transistor is connected between the input terminal of the first schmitt inverter, i.e., node Q, and the first bit line BL.

A second pass transistor is connected between the output of the first schmitt inverter, node QN, and a second bit line BLB.

The grid electrode of the first transmission tube and the grid electrode of the second transmission tube are both connected with a word line WL.

The first transmission tube is composed of an NMOS tube N307, and the second transmission tube is composed of an NMOS tube N308.

In other embodiments can also be: the first transmission pipe is composed of PMOS pipes, and the second transmission pipe is composed of PMOS pipes.

An SRAM memory array is formed by sequencing a plurality of SRAM memory cells.

According to the embodiment of the invention, both the two interlocked inverters of the SRAM storage unit adopt the Schmitt inverter, and the Schmitt inverter has the hysteresis effect, so that the input end and the output end of the SRAM storage unit can be switched from 0 to 1 and from 1 to 0 by using the hysteresis effect of the Schmitt inverter, and the input end or the output end of the SRAM storage unit is difficult to turn over when noise occurs, so that the noise tolerance can be improved, and the embodiment of the invention can improve HSNM, RSNM and WM.

The reason why the embodiment of the present invention can improve the noise margin in various situations is explained as follows:

case 1: when the cell stores data "1", the potentials of the internal nodes at this time are Q ═ 1 and QN ═ 0, respectively;

for the QN node, when QN is 0, the PMOS transistor P306 is turned on, and the NMOS transistor N306 is turned off; due to the hysteresis effect of the Schmitt inverter, i.e., the first Schmitt inverter, Vth (0- >1), which is the threshold voltage (Vth) when changing from 0 to 1, increases, and QN becomes more difficult to be 1. That is, PMOS transistor P306 has a pull-down current, so that the difficulty of pulling node QN up from 0 to 1 increases, and Vth (0- >1) increases.

When the node Q is equal to 1, the PMOS transistor P305 is turned off, and the NMOS transistor N305 is turned on; due to the hysteresis effect of the Schmitt inverter, i.e., the second Schmitt inverter, Vth (1- >0), which is the threshold voltage when changing from 1 to 0, increases, and Q becomes more difficult to be 0. That is, the NMOS transistor P305 has a pull-up current, so that the difficulty of pulling down the node Q from 1 to 0 increases, and Vth (1- >0) increases.

Case 2: when the cell stores data "0", the potentials of the internal nodes at this time are QN ═ 0 and Q ═ 1, respectively; in this case, the input and output of case 1 are obtained by being halved, and the two cases are substantially similar. Now, the following is explained:

for the node Q, when Q is equal to 0, the PMOS transistor P305 is turned on, and the NMOS transistor N305 is turned off; due to the hysteresis effect of the Schmitt inverter, i.e., the second Schmitt inverter, Vth (0- >1) increases and Q becomes harder to become 1.

When the node QN is 1, the PMOS transistor P306 is turned off, and the NMOS transistor N306 is turned on; due to the hysteresis effect of the Schmitt inverter, i.e., the first Schmitt inverter, Vth (1- >0) increases, and QN becomes more difficult to become 0.

Therefore, HSNM is large and the final noise margin is also large.

The basic function description of the circuit of the embodiment of the invention is as follows:

FIG. 4 shows simulation waveforms for normal operation of an SRAM memory cell according to an embodiment of the present invention; various functions such as write, hold, and read of an embodiment of the present invention are described in conjunction with fig. 4.

1. Writing: when the word line WL signal is high, the pass transistors, i.e., NMOS transistors N307 and N308, are both in an on state. Data is transferred from the input bit lines BL and BLB through the pass transistors N307 and N308 to the storage nodes Q, QN in the memory cell to perform a write operation.

2. Maintaining: when the word line WL signal is low, pass transistors N307 and N308 are both in an OFF state. The storage nodes Q, QN in the memory cell are locked to each other and hold correct data.

3. Reading: the bit line BL and BLB precharge is complete, the word line WL signal goes high, and pass transistors N307 and N308 are both open. Data is connected to bit lines BL and BLB from storage nodes Q, QN in the memory cell through transfer transistors N307 and N308, thereby performing a read operation.

Description of the high noise margin of the circuit of the embodiment of the invention:

the stability of the memory cell needs to be considered from three operating modes. For read and hold, static noise margin is typically used to evaluate stability, reflecting the maximum dc noise power that the memory cell can withstand.

When word line WL is low, bit lines BL and BLB are charged to supply voltage VDD, the tolerance for noise in hold mode at this time is HSNM.

When the bit lines are precharged to the power supply voltage VDD and then the word lines WL become high, the tolerance to noise in the read mode at this time is RSNM.

When the bit lines are precharged to the corresponding potential and then the word lines WL become high level, the tolerance to noise in the write mode at this time is a write margin.

FIG. 5A is a simulation diagram of RSNM of the conventional 6T SRAM memory cell shown in FIG. 1; the abscissa in fig. 5A is the voltage VQ of the node Q, and the ordinate is the voltage VQN of the node QN. Curve 101 represents the input/output variation curve during reading with VQ as the input voltage and VQN as the output voltage; curve 102 is symmetrical to curve 101, and is an input/output variation curve at the time of reading when VQN is used as an input voltage and VQ is used as an output voltage. The size of RSNM is obtained from the area corresponding to the dashed box 103.

FIG. 5B is a simulation diagram of HSNM of the prior art 6T SRAM memory cell shown in FIG. 1; curve 104 represents the input-output variation curve in the hold mode with VQ as the input voltage and VQN as the output voltage; curve 105 is symmetrical to curve 104 and is the input-output variation curve in the hold mode with VQN as the input voltage and VQ as the output voltage. The size of HSNM is obtained from the area corresponding to the dashed box 106.

FIG. 6A is a simulation diagram of RSNM of the conventional stack-type SRAM memory cell shown in FIG. 2; the abscissa in fig. 6A is the voltage VQ of the node Q, and the ordinate is the voltage VQN of the node QN. Curve 201 represents the input-output variation curve at the time of reading with VQ as the input voltage and VQN as the output voltage; the curve 202 is symmetrical to the curve 201, and is an input/output variation curve when reading with VQN as the input voltage and VQ as the output voltage. The size of RSNM is obtained from the area corresponding to the dashed box 203.

FIG. 6B is a simulation diagram of HSNM of the conventional stack SRAM memory cell shown in FIG. 2; curve 204 represents the input-output variation curve in the hold mode with VQ as the input voltage and VQN as the output voltage; curve 205 is then symmetrical to curve 204 and is the input-output variation curve in the hold mode with VQN as the input voltage and VQ as the output voltage. The size of the HSNM is obtained from the area corresponding to the dashed box 206.

FIG. 7A is a simulation diagram of RSNM of the SRAM memory cell of FIG. 3 according to the embodiment of the present invention; the abscissa in fig. 7A is the voltage VQ of the node Q, and the ordinate is the voltage VQN of the node QN.

Curves

301a and 301b represent input-output variation curves at the time of reading with VQ as an input voltage and VQN as an output voltage;

curves

302a and 302b are both input/output curves at the time of reading with VQN as the input voltage and VQ as the output voltage, and curve 302a is symmetrical to curve 301a and curve 302b is symmetrical to curve 301 b. Since the hysteresis effect is present in the embodiment of the present invention, the threshold voltage corresponding to the change of VQ from 0 to 1, i.e., from low voltage to high voltage, and the threshold voltage corresponding to the change of VQ from 1 to 0 are different, and thus there are two curves, i.e., curves 301a and 301b and

curves

302a and 302b, in both cases, the curve 301a corresponds to the curve corresponding to the change of VQ from 0 to 1, and the curve 301b corresponds to the curve corresponding to the change of VQ from 1 to 0. Finally, the size of RSNM is obtained from the area corresponding to the dashed box 303.

FIG. 7B is a simulation diagram of HSNM of the SRAM memory cell of the embodiment of the invention shown in FIG. 3;

curves

304a and 304b represent input-output variation curves at the time of reading with VQ as an input voltage and VQN as an output voltage; curves 305a and 305b are both input/output curves at the time of reading with VQN as the input voltage and VQ as the output voltage, and curve 305a is symmetrical to curve 304a and curve 305b is symmetrical to curve 304 b. Since the hysteresis effect is present in the embodiment of the present invention, the threshold voltage corresponding to the change of VQ from 0 to 1, i.e., from low voltage to high voltage, and the threshold voltage corresponding to the change of VQ from 1 to 0 are different, and thus there are two curves, i.e., curves 304a and 304b and curves 305a and 305b, in both cases, the curve 304a corresponds to the curve corresponding to the change of VQ from 0 to 1, and the curve 304b corresponds to the curve corresponding to the change of VQ from 1 to 0. Finally, the size of HSNM is obtained from the area corresponding to the dashed box 306. As can be seen from the comparison of the dashed box 605 in fig. 5B and the dashed box 206 in fig. 6B, the HSNM is enlarged because the range of the dashed box 306 in the embodiment of the present invention is enlarged.

Finally, the following values can be obtained by simulation:

the simulation values corresponding to the conventional 6T-type SRAM memory cell shown in fig. 1 include:

RSNM：0.2828，HSNM：0.6209，WM：0.68。

the simulation values corresponding to the conventional stack-type SRAM cell shown in fig. 2 include:

RSNM：0.2231，HSNM：0.6528，WM：0.73。

the simulation value corresponding to the SRAM memory cell of the embodiment of the invention comprises:

RSNM：0.2853，HSNM：0.9230，WM：0.75。

it can be seen that RSNM, HSNM and WM are increased, and HSNM value is better.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. a SRAM storage unit, is characterized in that, comprising: a pair of Schmitt inverters formed by the first Schmitt inverter and the second Schmitt inverter;

The input terminal of the first Schmitt inverter is connected to the output terminal of the second Schmitt inverter, and the output terminal of the first Schmitt inverter is connected to the second Schmitt inverter. The input terminal of the phase device;

The hysteresis effect of the Schmitt inverter is used to improve the noise tolerance of the SRAM memory cell.

2. The SRAM memory cell of claim 1, wherein the first Schmitt inverter comprises: a first stacked inverter connection and a first hysteresis circuit;

the first hysteresis circuit includes a first pull-down hysteresis path and a first pull-up hysteresis path;

The first stack inverter is formed by connecting a first pull-up stack path and a first pull-down stack path, the first pull-up stack path is formed by connecting a plurality of PMOS transistors in series, and the first pull-down stack The path is formed by connecting a plurality of NMOS transistors in series, and the gates of the PMOS transistors of the first pull-up stack path and the gates of the NMOS transistors of the first pull-down stack path are all connected together and serve as the first pull-up stack path. an input of a Schmitt inverter;

The connection of the first pull-up stack path and the first pull-down stack path forms the output end of the first Schmitt inverter;

The first pull-down hysteresis path is formed by connecting more than one PMOS transistor in series, and the first pull-up hysteresis path is formed by connecting more than one NMOS transistor in series;

The gate of the PMOS transistor of the first pull-down hysteresis path and the gate of the NMOS transistor of the first pull-up hysteresis path are both connected to the output end of the first Schmitt inverter;

the first pull-down hysteresis path is connected in series between a connection node between each PMOS transistor of the first pull-up stack path and the ground;

The first pull-up hysteresis path is connected in series between a connection node between the NMOS transistors of the first pull-down stack path and the power supply voltage.

3 . The SRAM memory cell of claim 2 , wherein the first pull-up stack path is connected in series by two PMOS transistors. 4 .

4. The SRAM memory cell of claim 3, wherein the first pull-down stack path is connected in series by two NMOS transistors.

5. The SRAM memory cell of claim 2, wherein the first pull-down hysteresis path is composed of a PMOS transistor.

6. The SRAM memory cell according to claim 5, wherein the first pull-up hysteresis path is composed of an NMOS transistor.

7. The SRAM memory cell according to claim 1 or 2, wherein the second Schmitt inverter comprises: a second stack inverter connection and a second hysteresis circuit;

the second hysteresis circuit includes a second pull-down hysteresis path and a second pull-up hysteresis path;

The second stack inverter is formed by connecting a second pull-up stack path and a second pull-down stack path, the second pull-up stack path is formed by connecting a plurality of PMOS transistors in series, and the second pull-down stack path is composed of A plurality of NMOS transistors are connected in series, and the gates of the PMOS transistors of the second pull-up stack path and the gates of the NMOS transistors of the second pull-down stack path are all connected together and serve as the second densification The input terminal of the special inverter;

The connection of the second pull-up stack path and the second pull-down stack path forms an output end of the second Schmitt inverter;

The second pull-down hysteresis path is formed by connecting more than one PMOS transistor in series, and the second pull-up hysteresis path is formed by connecting more than one NMOS transistor in series;

The gate of the PMOS transistor of the second pull-down hysteresis path and the gate of the NMOS transistor of the second pull-up hysteresis path are both connected to the output end of the second Schmitt inverter;

the second pull-down hysteresis path is connected in series between a connection node between the PMOS transistors of the second pull-up stack path and the ground;

The second pull-up hysteresis path is connected in series between a connection node between the NMOS transistors of the second pull-down stack path and the power supply voltage.

8. The SRAM memory cell of claim 7, wherein the second pull-up stack path is connected in series by two PMOS transistors.

9 . The SRAM memory cell of claim 8 , wherein the second pull-down stack path is connected in series by two NMOS transistors. 10 .

10. The SRAM memory cell of claim 7, wherein the second pull-down hysteresis path is composed of a PMOS transistor.

11. The SRAM memory cell of claim 10, wherein the second pull-up hysteresis path is composed of an NMOS transistor.

12. The SRAM storage unit according to claim 10, wherein the SRAM storage unit further comprises a pair of transmission tubes;

the first transmission tube is connected between the input end of the first Schmitt inverter and the first bit line;

The second transmission tube is connected between the output end of the first Schmitt inverter and the second bit line;

The gate of the first transfer transistor and the gate of the second transfer transistor are both connected to the word line.

13. The SRAM memory cell according to claim 12, wherein the first transfer transistor is composed of an NMOS transistor, and the second transfer transistor is composed of an NMOS transistor.

14. The SRAM memory cell of claim 12, wherein the first transfer transistor is composed of a PMOS transistor, and the second transfer transistor is composed of a PMOS transistor.

15. The SRAM memory cell according to claim 1, wherein an SRAM memory array is formed by ordering a plurality of SRAM memory cells.