CN113840047B - Image playing system, image data transmission device and method - Google Patents

Abstract

The application discloses an image data transmission device with a synchronous data transmission mechanism. The output stage circuit receives and temporarily stores the image data corresponding to a part of the display picture respectively. The main switch circuit is electrically coupled to a main output stage circuit of the output stage circuit, and maintains the control voltage of the control node at a first level when the main picture alignment signal with the latest timing is not received from the main output stage circuit, and converts the control voltage of the control node to a second level when the main picture alignment signal is received. When receiving the control voltage with the second level through the voltage transmission paths with the same signal transmission time, the output stage circuit synchronously outputs the image data to the image data receiving device so as to play the display picture.

Description

Image playback system, image data transmission device and method

Technical Field

The present invention relates to image data processing technology, and more particularly to an image playback system and an image data transmission device and method having a synchronous data transmission mechanism.

Background technique

Some consumer electronic products such as televisions and smart phones are becoming more and more popular with consumers due to their entertainment nature, and therefore have higher and higher specifications. Take LCD TVs as an example. Since large-screen TVs can provide a better viewing experience, the size of TVs has gradually developed from 50 inches to more than 70 inches in recent years.

On such a large-size TV, multiple image data transmission chips are often required to provide image data corresponding to different panel areas to the panel for playback. However, such a design requires the image data transmission chips to transmit synchronized image data to the panel for playback. Therefore, there must be an accurate synchronized data transmission mechanism between the multiple image data transmission chips so that the panel can correctly receive and play the image data transmitted by the image data transmission chips.

Summary of the invention

In view of the problems of the prior art, one object of the present invention is to provide an image playback system and an image data transmission device and method thereof with a synchronous data transmission mechanism to improve the prior art.

One object of the present invention is to provide an image data transmission device with a synchronous data transmission mechanism, and one embodiment thereof includes: a plurality of output stage circuits, a main switch circuit, and a plurality of voltage transmission paths. The output stage circuits are respectively configured to receive and temporarily store one of a plurality of image data, wherein the image data respectively corresponds to a portion of a display screen. The main switch circuit is configured to be electrically coupled to one of the main output stage circuits in the output stage circuits, so that when a main screen alignment signal with the latest timing is not received from the main output stage circuit, the control voltage of the control node is maintained at a first level, and when the main screen alignment signal is received, the control voltage of the control node is converted to a second level. The voltage transmission path is configured to electrically couple the control node to each of the output stage circuits, and the voltage transmission path has the same signal transmission time. When the output stage circuit receives the control voltage with the second level through the voltage transmission path, the image data is synchronously output to the image data receiving device to play the display screen.

Another object of the present invention is to provide an image playback system, one embodiment of which includes: an image data receiving device and an image data transmission device. The image data transmission device includes a plurality of output stage circuits, a main switch circuit and a plurality of voltage transmission paths. The output stage circuits are respectively configured to receive and temporarily store one of a plurality of image data, wherein the image data respectively corresponds to a portion of a display screen. The main switch circuit is configured to be electrically coupled to a main output stage circuit in the output stage circuits, so that when a main screen alignment signal with the latest timing is not received from the main output stage circuit, the control voltage of the control node is maintained at a first level, and when the main screen alignment signal is received, the control voltage of the control node is converted to a second level. The voltage transmission path is configured to electrically couple the control node to each of the output stage circuits, and the voltage transmission path has the same signal transmission time. When the output stage circuit receives the control voltage with the second level through the voltage transmission path, the image data is synchronously output to the image data receiving device to play the display screen.

Another object of the present invention is to provide an image data processing method with a synchronous data transmission mechanism, which is applied to an image data transmission device, and one embodiment of the method includes the following steps: enabling multiple output stage circuits to respectively receive and temporarily store one of multiple image data, wherein the image data respectively corresponds to a portion of a display screen; enabling a main switch circuit electrically coupled to a main output stage circuit in the output stage circuit to maintain a control voltage of a control node at a first level when a main screen alignment signal with a latest timing is not received from the main output stage circuit; enabling the main switch circuit to convert the control voltage of the control node to a second level when the main screen alignment signal is received; and enabling the output stage circuit to synchronously output the image data to an image data receiving device to play a display screen when a control voltage with a second level is received through multiple voltage transmission paths, wherein the voltage transmission path is configured to electrically couple the control node to each of the output stage circuits, and the voltage transmission paths have the same signal transmission time.

The features, implementation and efficacy of the present invention are described in detail below with reference to the accompanying drawings as preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an image playback system according to an embodiment of the present invention;

FIG. 2 shows a circuit diagram of an image data transmission device having a synchronous data transmission mechanism in one embodiment of the present invention;

FIG3 shows a circuit diagram of an image data transmission device with a synchronous data transmission mechanism in another embodiment of the present invention; and

FIG. 4 is a flow chart showing an image data processing method according to an embodiment of the present invention.

Detailed ways

One of the purposes of the present invention is to provide an image data transmission device and method, in which a main switch circuit converts a control voltage level state according to a main screen alignment signal with a latest timing, and then the control voltage in the converted level state synchronously drives an output stage circuit to output image data, thereby achieving an accurate image data synchronization mechanism.

Please refer to FIG. 1 . FIG. 1 shows a block diagram of an image playing system 100 according to an embodiment of the present invention. The image playing system 100 includes an image data transmitting device 110 with a synchronous data transmitting mechanism and an image data receiving device 120 .

In one embodiment, the image playback system 100 is, for example but not limited to, a television. The image data transmission device 110 is a circuit configured to receive the image data IDA-IDD through the image source IS and perform signal processing and transmission. The image data receiving device 120 is a panel configured to receive the image data IDA-IDD from the image data transmission device 110 and play it.

As the size of the panel becomes larger and larger, the image data transmission device 110 often processes and transmits multiple image data IDA~IDD to the image data receiving device 120 for display through different internal circuits. For example, if the overall panel display area is divided into four different panel display areas from left to right, different image data IDA~IDD correspond to four different panel display areas. For example, the image data IDA corresponds to the first panel display area on the left, the image data IDD corresponds to the fourth panel display area on the right, and so on. It should be noted that the number of the above four image data and the division of the panel display area are only an example. In other embodiments, the number of image data corresponding to a complete screen can be any positive integer greater than 1, and the overall panel display area can be divided in different ways.

Therefore, the image data transmission device 110 needs to have a synchronous data transmission mechanism so that the image data receiving device 120 can simultaneously display multiple sets of image data IDA-IDD according to the correct timing to generate a correct picture.

Please refer to FIG2 . FIG2 shows a circuit diagram of an image data transmission device 110 with a synchronous data transmission mechanism in one embodiment of the present invention.

As shown in FIG. 2 , the image data transmission device 110 includes a plurality of image processing paths 200A- 200D, a plurality of output stage circuits 210A- 210D, a main switch circuit 220A, and a plurality of voltage transmission paths 230A- 230D.

The image processing paths 200A-200D are respectively electrically coupled between the image source IS and one of the output stage circuits 210A-210D, and are respectively configured to receive one of the image data IDA-IDD from the image source 110 for processing and transmit to one of the output stage circuits 210A-210D.

In one embodiment, the image processing paths 200A-200D respectively include a plurality of digital signal processing circuits (not shown) to process one of the image data, wherein the digital signal processing circuit may perform, for example but not limited to, data format conversion, scaling control or a combination thereof on the corresponding image data IDA-IDD.

The output stage circuits 210A-210D are respectively configured to receive and temporarily store one of the image data IDA-IDD processed by the image processing paths 200A-200D. In one embodiment, the output stage circuits 210A-210D respectively include a temporary storage circuit 240 and a synchronization control circuit 250.

The temporary storage circuit 240 of the output stage circuits 210A-210D is respectively configured to receive and temporarily store one of the image data IDA-IDD. The synchronous control circuit 250 of the output stage circuits 210A-210D is respectively configured to generate one of the frame alignment signals SYA-SYD, so that the main switch circuit 220A adjusts the control voltage Vc of the control node CP according to one of the frame alignment signals SYA-SYD. In some embodiments, the time when the synchronous control circuit 250 of the output stage circuits 210A-210D generates the frame alignment signals SYA-SYD can be a certain time point after the output stage circuits 210A-210D respectively receive and temporarily store the image data IDA-IDD from the image source IS, or a specific time point defined in the image data IDA-IDD.

Furthermore, the synchronous control circuit 250 of each output stage circuit 210A-210D is electrically coupled to the control node CP via one of the voltage transmission paths 230A-230D to synchronously output the image data IDA-IDD temporarily stored in the temporary storage circuit 240 to the image data receiving device 120 according to the control voltage Vc of the control node CP.

The main switch circuit 220A is configured to be electrically coupled to a main output stage circuit among the output stage circuits 210A-210D to receive the main frame alignment signal from the main output stage circuit. In the present embodiment, the main output stage circuit is exemplified by the output stage circuit 210A. The main switch circuit 220A is configured to receive the frame alignment signal SYA from the output stage circuit 210A. In other embodiments, the main output stage circuit may be another one of the output stage circuits 210B-210D, and the main switch circuit 220A is configured to receive the corresponding one of the frame alignment signals SYB-SYD.

In one embodiment, the frame alignment signal SYA, which is the main frame alignment signal, has the latest timing among all the frame alignment signals SYA-SYD. More specifically, the timing of the frame alignment signal SYA is later than the timings of the other frame alignment signals SYB-SYD.

In another embodiment, the main switch circuit 220A is electrically coupled to the output stage circuit 210A via a main transmission path 260A. The main transmission path 260A may include a delay circuit (not shown) to ensure that the timing of the frame alignment signal SYA being transmitted from the output stage circuit 210A to the main switch circuit 220A via the main transmission path 260A is later than the timing of the other frame alignment signals SYB-SYD.

The main switch circuit 220A maintains the control voltage Vc of the control node CP at the first level when not receiving the frame alignment signal SYA, and switches the control voltage Vc of the control node CP to the second level when receiving the frame alignment signal SYA.

In one embodiment, the control node CP receives the charging current CC from the power source 270 (e.g., a current source or a voltage source) through the resistor R. The main switch circuit 220A is electrically coupled between the control node CP and the ground terminal GND to operate in a first state when the frame alignment signal SYA is not received, so that the control voltage Vc is at a first level, and to operate in a second state when the frame alignment signal SYA is received, so that the control voltage Vc is at a second level.

One of the first state and the second state is to turn on the main switch circuit 220A to draw current from the control node CP to lower the control voltage Vc, and the other is to turn off the main switch circuit 220A to stop drawing current from the control node CP to raise the control voltage Vc.

For example, the main switch circuit 220A may include, for example, but not limited to, a metal oxide semiconductor field effect transistor or a bipolar transistor. For example, the main switch circuit 220A includes an N-type metal oxide semiconductor field effect transistor, whose drain and source are electrically coupled to the control node CP and the ground terminal GND respectively, and whose gate is controlled by the voltage transmitted by the output stage circuit 210A through the main transmission path 260A, so as to be turned on when receiving a high-state voltage and turned off when receiving a low-state voltage.

At this time, the frame alignment signal SYA is a low active signal. In more detail, when the main switch circuit 220A receives a high signal from the output stage circuit 210A, it means that the frame alignment signal SYA has not been received. Therefore, the first state of the main switch circuit 220A is turned on to draw current from the control node CP to pull down the control voltage Vc. In one embodiment, the control voltage Vc pulled to the ground level corresponds to the first level mentioned above.

When the main switch circuit 220A receives a low-state signal from the output stage circuit 210A, it indicates that the frame alignment signal SYA is received. Therefore, the second state of the main switch circuit 220A is disconnected, and stops drawing current from the control node CP. The control voltage Vc of the control node CP will be raised due to the charging current CC of the power source 270. In one embodiment, the control voltage Vc raised to a high-state voltage corresponds to the aforementioned second level.

The voltage transmission paths 230A-230D are configured to electrically couple the control node CP to the synchronous control circuit 250 of each of the output stage circuits 210A-210D, and the voltage transmission paths 230A-230D are configured to have the same signal transmission time. Therefore, when the control voltage Vc is converted from the first level to the second level, the synchronous control circuit 250 of the output stage circuit 210A-210D will be synchronized to receive the control voltage Vc with the second level through the voltage transmission paths 230A-230D.

Furthermore, the synchronous control circuit 250 can synchronously output the image data IDA-IDD temporarily stored in the temporary storage circuit 240 to the image data receiving device 120 for playing and displaying the image according to the control voltage Vc with the second level.

Please refer to FIG3 . FIG3 shows a circuit diagram of an image data transmission device 110 with a synchronous data transmission mechanism in another embodiment of the present invention.

Similar to the image data transmission device 110 of FIG2 , the image data transmission device 110 of FIG3 also includes image processing paths 200A-200D, output stage circuits 210A-210D, a main switch circuit 220A and voltage transmission paths 230A-230D, and its structure and operation are the same as the corresponding components of FIG2 , so they are not described in detail. In this embodiment, the image data transmission device 110 further includes a plurality of secondary switch circuits 220B-220D.

The secondary switch circuits 220B-220D are respectively configured to be electrically coupled to one of the secondary output stage circuits 210A-210D except the primary output stage circuit 210A through the secondary transmission path to receive the secondary frame alignment signal from the secondary output stage circuit. More specifically, the secondary switch circuits 220B-220D are respectively configured to be electrically coupled to one of the output stage circuits 210B-210D through the secondary transmission path 260B-260D to receive the frame alignment signals SYB-SYD from the output stage circuits 210B-210D.

Furthermore, the secondary switch circuits 220B-220D are electrically coupled between the control node CP and the ground GND, respectively.

Similar to the implementation and operation of the main switch circuit 220A, the secondary switch circuits 220B-220D may include metal oxide semiconductor field effect transistors or bipolar transistors. The secondary switch circuits 220B-220D operate in a first state when they have not received the corresponding frame alignment signals SYB-SYD, and operate in a second state when they receive the frame alignment signals SYB-SYD.

Taking the case where the secondary switch circuits 220B-220D are implemented by N-type metal oxide semiconductor field effect transistors and the frame alignment signals SYB-SYD are low-state enabled, the first state is on and the second state is off. Therefore, when the secondary switch circuits 220B-220D have not received the frame alignment signals SYB-SYD, they will be turned on to pull down the control voltage Vc of the control node CP. When the secondary switch circuits 220B-220D receive the frame alignment signals SYB-SYD, they will be turned off to raise the control voltage Vc of the control node CP.

In one embodiment, the timing of the frame alignment signals SYB-SYD is earlier than the latest timing of the frame alignment signal SYA. Therefore, before the main switch circuit 220A has not received the frame alignment signal SYA, even if the sub-switch circuits 220B-220D have received the frame alignment signals SYB-SYD and are turned off, the control voltage Vc of the control node CP is still pulled down to the first level because the main switch circuit 220A maintains the first state of conduction. Until the main switch circuit 220A also receives the frame alignment signal SYA and becomes the second state of disconnection, the control voltage Vc of the control node CP is raised to the second level due to the charging current CC of the power source 270.

In one embodiment, the main transmission path 260A and the secondary transmission paths 260B-260D can be selectively set to have the same signal transmission time, so the timing of the frame alignment signals SYA-SYD will only be related to the time generated by the output stage circuits 210A-210D, and has nothing to do with the path transmitted to the main switch circuit 220A and the secondary switch circuits 220B-220D. However, in this embodiment, regardless of whether the main transmission path 260A and the secondary transmission paths 260B-260D have the same signal transmission time, the synchronization timing will correspond to the frame alignment signal with the latest timing.

Then, the voltage transmission paths 230A-230D with the same signal transmission time can synchronously enable the synchronous control circuit 250 of the output stage circuits 210A-210D to receive the control voltage Vc with the second level when the control voltage Vc is converted from the first level to the second level. Further, the synchronous control circuit 250 can synchronously output the image data IDA-IDD temporarily stored in the temporary storage circuit 240 to the image data receiving device 120 according to the control voltage Vc with the second level so as to play the display screen.

Therefore, the image data transmission device of the present invention can use the frame alignment signal with the latest timing as the main frame alignment signal to ensure that all output stage circuits are ready to output image data. The main switch circuit converts the control voltage level state according to the main frame alignment signal, so that all output stage circuits synchronously receive the control voltage of the converted level state and synchronously output the image data, thereby achieving an accurate image data synchronization mechanism.

It should be noted that in the above embodiments, the output stage circuit 210A is used as an example to describe the case where the main frame alignment signal is generated. In other embodiments, the main frame alignment signal with the latest timing may correspond to other output stage circuits.

Furthermore, under appropriate logic combination adjustment, the primary and secondary frame alignment signals can be selectively implemented as low-state enable or high-state enable, and the primary and secondary switch circuits can also be implemented with N-type metal oxide semiconductor field effect transistors, P-type metal oxide semiconductor field effect transistors, NPN bipolar transistors or PNP bipolar transistors in combination with the primary and secondary frame alignment signals. The present invention is not limited to the implementation methods shown in FIG. 2 and FIG. 3.

Please refer to FIG4 . FIG4 is a flow chart showing an image data processing method 400 according to an embodiment of the present invention.

In addition to the aforementioned devices, the present invention further discloses an image data processing method 400, which is applied to, for example, but not limited to, the image data transmission device 110 of FIG. 2. An embodiment of the image data processing method 400 is shown in FIG. 4, and includes the following steps:

In step S410 : the output stage circuits 210A-210D are respectively configured to receive and temporarily store one of the image data IDA-IDD, wherein the image data IDA-IDD respectively correspond to a portion of the display screen.

In step S420 , it is determined whether the main output stage circuit among the output stage circuits 210A-210D, for example, the main switch circuit 220A electrically coupled to the output stage circuit 210A, receives the main frame alignment signal SYA having the latest timing from the main output stage circuit 210A.

In step S430 : when the main switch circuit 220A has not received the main frame alignment signal SYA from the main output stage circuit 210A, the control voltage Vc of the control node CP is maintained at the first level. Then, the process returns to step S420 to continue the determination.

In step S440 , when the main switch circuit 220A receives the main frame alignment signal SYA, the control voltage Vc of the control node CP is converted to the second level.

In step S450 , when the output stage circuits 210A- 210D receive the control voltage Vc having the second level through the voltage transmission paths 230A- 230D, the image data IDA-IDD are synchronously output to the image data receiving device 120 for playing and displaying the images.

The voltage transmission paths 230A-230D are configured to electrically couple the control node CP to each of the output stage circuits 210A-210D, respectively, and the voltage transmission paths 230A-230D have the same signal transmission time.

It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art may make changes without violating the spirit of the present invention.

In summary, the image data transmission device and method of the present invention can use the main switch circuit to convert the control voltage level state according to the main frame alignment signal with the latest timing to synchronously drive the output stage circuit to output image data, thereby achieving an accurate image data synchronization mechanism.

Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. A person with ordinary knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be based on what is defined in the claims of this specification.

【Symbol Description】

100: Video playback system

110: Image data transmission device

120: Image data receiving device

200A～200D: Image processing path

210A～210D: Output stage circuit

220A: Main switch circuit

220B～220D: Secondary switch circuit

240: Temporary storage circuit

250: Synchronous control circuit

230A～230D: Voltage transmission path

260A: Main transmission path

260B～260D: Secondary transmission path

270: Power Supply

400: Image Data Processing Method

S410～S450: Steps

CC: Charging current

CP: Control Node

GND: Ground terminal

IDA～IDD image data

IS: Image Source

R: Resistance

SYA～SYD: Screen alignment signal

Vc: Control voltage

Claims (10)

1. An image data transmission device with a synchronous data transmission mechanism, characterized in that it comprises: A plurality of output stage circuits are respectively configured to receive and temporarily store one of a plurality of image data, wherein the image data respectively corresponds to a portion of a display screen; a main switch circuit configured to be electrically coupled to a main output stage circuit of the output stage circuits, so as to maintain a control voltage of a control node at a first level when a main frame alignment signal having a latest timing is not received from the main output stage circuit, and to convert the control voltage of the control node to a second level when the main frame alignment signal is received; and a plurality of voltage transmission paths configured to electrically couple the control node to each of the output stage circuits, and the voltage transmission paths have the same signal transmission time; When the output stage circuit receives the control voltage with the second level through the voltage transmission path, the output stage circuit synchronously outputs the image data to an image data receiving device to play the display picture. 2. The image data transmission device of claim 1, wherein the control node receives a charging current from a power source through a resistor, and the main switch circuit is electrically coupled between the control node and a ground terminal, so as to operate in a first state and make the control voltage at the first level when the main frame alignment signal is not received, and operate in a second state and make the control voltage at the second level when the main frame alignment signal is received; One of the first state and the second state is to turn on the main switch circuit to draw current from the control node to lower the control voltage, and the other is to turn off the main switch circuit to stop drawing current from the control node to raise the control voltage. 3 . The image data transmission device as claimed in claim 2 , wherein the main switch circuit comprises a metal oxide semiconductor field effect transistor or a bipolar transistor. 4. The image data transmission device as claimed in claim 2, further comprising a plurality of secondary switch circuits, each configured to be electrically coupled to one of the other plurality of secondary output stage circuits in the output stage circuit except the primary output stage circuit; The secondary switch circuits are further electrically coupled between the control node and the ground terminal, and are respectively configured to operate in the first state when one of the secondary frame alignment signals is not received from the corresponding secondary output stage circuit, and to operate in the second state when one of the secondary frame alignment signals is received, wherein a timing of the secondary frame alignment signal is earlier than the latest timing of the primary frame alignment signal. 5. The image data transmission device as described in claim 4 is characterized in that the main switching circuit and the main output stage circuit are electrically coupled through a main transmission path, and the secondary switching circuit and the secondary output stage circuit are electrically coupled through one of a plurality of secondary transmission paths, respectively, wherein the main transmission path and the secondary transmission path have the same signal transmission time. 6 . The image data transmission device as claimed in claim 4 , wherein the secondary switch circuits each comprise a metal oxide semiconductor field effect transistor or a bipolar transistor. 7. The image data transmission device according to claim 4, wherein the output stage circuits are respectively configured to include: a temporary storage circuit configured to receive and temporarily store one of the image data; and A synchronous control circuit is configured to generate one of a plurality of frame alignment signals, and is configured to enable the image data temporarily stored in the temporary storage circuit to be output to the image data receiving device when receiving the control voltage with the second level, wherein the frame alignment signal includes the primary frame alignment signal and the secondary frame alignment signal. 8. The image data transmission device according to claim 1, further comprising: A plurality of image processing paths are respectively electrically coupled between an image source and one of the output stage circuits, and are respectively configured to receive one of the image data from the image source for processing and then transmit the processed image data to one of the output stage circuits. 9. An image playback system, comprising: an image data receiving device; and An image data transmission device, comprising: A plurality of output stage circuits are respectively configured to receive and temporarily store one of a plurality of image data, wherein the image data respectively corresponds to a portion of a display screen; a main switch circuit configured to be electrically coupled to one of the output stage circuits to maintain a control voltage of a control node at a first level when a main frame alignment signal having a latest timing is not received from the main output stage circuit, and to convert the control voltage of the control node to a second level when the main frame alignment signal is received; and a plurality of voltage transmission paths configured to electrically couple the control node to each of the output stage circuits, and the voltage transmission paths have the same signal transmission time; When the output stage circuit receives the control voltage with the second level through the voltage transmission path, the output stage circuit synchronously outputs the image data to the image data receiving device so as to play the display picture. 10. An image data processing method with a synchronous data transmission mechanism, applied to an image data transmission device, characterized in that it comprises: Allowing a plurality of output stage circuits to respectively receive and temporarily store one of a plurality of image data, wherein the image data respectively corresponds to a portion of a display screen; A main switch circuit electrically coupled to one of the main output stage circuits of the output stage circuits maintains a control voltage of a control node at a first level when a main frame alignment signal with a latest timing is not received from the main output stage circuit; enabling the main switch circuit to convert the control voltage of the control node to a second level when receiving the main frame alignment signal; and When the output stage circuit receives the control voltage having the second level through multiple voltage transmission paths, the image data is synchronously output to an image data receiving device for playing the display screen, wherein the voltage transmission paths are configured to electrically couple the control node to each of the output stage circuits, and the voltage transmission paths have the same signal transmission time.