CN113838937A

CN113838937A - A kind of deep trench superjunction MOSFET power device and preparation method thereof

Info

Publication number: CN113838937A
Application number: CN202111018751.2A
Authority: CN
Inventors: 王钦; 李海松; 陈飞鹭; 易扬波
Original assignee: Wuxi Chipown Micro Electronics Ltd
Current assignee: Wuxi Chipown Micro Electronics Ltd
Priority date: 2021-09-01
Filing date: 2021-09-01
Publication date: 2021-12-24

Abstract

The invention discloses a deep trench super-junction MOSFET power device, comprising a drain electrode, a substrate, an epitaxial layer, a body region, a source region, a gate structure and a source electrode arranged in sequence from bottom to top. A plurality of trenches are formed by etching, and the plurality of trenches are not connected to each other and are arranged in the vertical direction. is larger than its upper end width; each trench is filled with at least two layers of filling layers, the number of filling layers in multiple trenches is the same, and the height of the upper end surface of each filling layer remains the same, and the doping of the filling layer in a single trench The concentration decreases from bottom to top. The invention optimizes the structure of the device under the condition that the doping concentration of the epitaxial layer of the device remains unchanged, and no longer requires the growth of an epitaxial layer whose doping concentration changes linearly, which not only reduces the difficulty of the process, but also saves the production cost and shortens the time. processing time.

Description

Deep-groove super-junction MOSFET power device and preparation method thereof

Technical Field

The invention relates to a deep-groove super-junction MOSFET power device and a corresponding preparation method thereof, belonging to the technical field of semiconductors.

Background

A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a Field-Effect Transistor that can be widely used in analog circuits and digital circuits. As shown in fig. 1, in the conventional super junction MOSFET structure, the drift region has P columns and N columns with opposite doping types. When reverse bias is applied, the N column and the P column of the drift region are mutually depleted, and the charge balance enables the whole vertical device to be similar to a P-I-N structure and to resist high voltage; when a forward bias is applied, the depletion region of the PN junction is narrowed, and a current path is enough to conduct a large current, so that the super junction structure is formed for an ideal voltage-resistant structure and is also a common structure of such power devices.

In the actual device processing process, due to process limitation, the etched P-type region often has a certain angle, and under the condition that other conditions are not changed, the smaller the angle is, that is, the narrower the groove of the P-type column region is, the lower the on-resistance of the device is, the more vertical the groove of the P-type column region is, and the higher the on-resistance of the device is. Meanwhile, due to the diffusion of the impurities at the bottom, the doping concentration at the bottom of the P column is obviously reduced under the influence of the diffusion of the impurities at the bottom. Therefore, under the condition that the NP doping concentration is the same, the groove angle of the P-type column region is smaller, the radian of the upper end of an electric field curve is larger, the difference between the upper end of the electric field curve and an ideal rectangular electric field is larger, and the upper limit of the withstand voltage of the traditional super junction structure is lower. In order to overcome the above problems, the prior art mainly changes the doping concentration of the epitaxial N layer, but if an epitaxial layer with a doping concentration varying linearly needs to be grown, the process flow is complex, and the consumption in terms of cost and time is also huge.

Due to the above defects in the prior art, a new super junction MOS power semiconductor device is urgently needed to solve the contradiction between the withstand voltage value and the on-resistance caused by the actual process on the premise of ensuring that the concentration of the epitaxial layer is not changed.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a deep trench super junction MOSFET power device and a corresponding manufacturing method thereof, as follows.

A deep-groove super-junction MOSFET power device comprises a drain electrode, a substrate, an epitaxial layer, a body region, a source region, a grid structure and a source electrode which are sequentially arranged from bottom to top, wherein a plurality of grooves are formed in the epitaxial layer in an etching mode, the grooves are not communicated with one another and are all arranged in the vertical direction, the included angle range between the side wall of each groove and the horizontal plane is 80-90 degrees, and the width of the bottom end of each groove is not larger than that of the top end of each groove; at least two filling layers are filled in each groove, the number of the filling layers in the grooves is the same, the height of the upper end face of each filling layer is kept consistent, and the doping concentration of the filling layer in each groove decreases from bottom to top.

Preferably, the doping type of the substrate is n-type, the doping type of the epitaxial layer is n-type and is formed on the substrate, the doping concentration of the epitaxial layer is lower than that of the substrate, and the drain electrode is located below the substrate.

Preferably, the material of the filling layer is p-type silicon, the upper end surface of each layer of the filling layer is kept horizontal, and the side surface of each layer of the filling layer is in contact with the inner wall of the groove.

Preferably, in a single trench, based on the doping concentration at the central point in the vertical direction of the trench, the difference between the doping concentration of the filling layer located at the uppermost layer and the doping concentration of the filling layer located at the lowermost layer and the reference is not more than 50% of the reference.

Preferably, the doping type of the body region is p-type, the body region is formed above the trenches, and the epitaxial layer between two adjacent trenches in the horizontal direction is not penetrated by the body region.

Preferably, the source region is formed above the body region and is formed by a source and a source contact layer, the source contact layer is located on the outer side of the source in the horizontal direction, the doping type of the source is n-type and the doping concentration of the source is higher than that of the epitaxial layer and the body region, the doping type of the source contact layer is p-type and the doping concentration of the source contact layer is higher than that of the body region, and ohmic contact is formed between the source and the source contact layer.

Preferably, the gate structure is composed of a gate oxide layer, a polysilicon gate and a gate dielectric protection layer, the gate oxide layer is made of silicon dioxide and covers the body region and the source region, the polysilicon gate is located on the gate oxide layer and completely covers the upper end face of the gate oxide layer, and the gate dielectric protection layer is made of an insulating material and is located above and covers the gate oxide layer and the polysilicon gate.

Preferably, the source electrode is located above the source region and the gate structure, and a lower end surface of the source electrode is in contact with upper end surfaces of the source electrode and the source contact layer, respectively.

A method for preparing a deep-groove super-junction MOSFET power device is used for processing the deep-groove super-junction MOSFET power device and comprises the following steps:

s1, taking a substrate, forming a dense epitaxial layer on the substrate, then forming a plurality of grooves on the epitaxial layer by utilizing an etching process, controlling the included angle between the side wall of each groove and the horizontal plane to be 80-90 degrees, and ensuring that the grooves are not communicated with each other and are all arranged along the vertical direction;

s2, filling the groove for multiple times by using p-type silicon until the groove is completely filled, wherein in the filling process, the doping concentration of the used p-type silicon is sequentially reduced along with the filling times;

s3, forming a body region on the upper end face of the epitaxial layer by using the process of ion implantation and annealing diffusion, and then forming a source region on the upper end face of the body region by using the process of ion implantation and annealing diffusion again;

s4, combining the gate oxide layer, the polysilicon gate and the gate dielectric protection layer in sequence from bottom to top to form a gate structure, and then arranging the gate structure on the body region and the source region;

s5, arranging a source electrode above the source region and the grid structure, and ensuring that the lower end face of the source electrode is respectively in contact with the upper end faces of the source electrode and the source contact layer;

and S6, arranging the drain electrode below the substrate, and ensuring that the upper end face of the drain electrode is in contact with the lower end face of the substrate.

Compared with the prior art, the invention has the advantages that:

the structure of the deep-groove super-junction MOSFET power device provided by the invention is optimized under the condition of ensuring that the doping concentration of the epitaxial layer of the device is not changed, and the epitaxial layer with the doping concentration changing linearly is not required to grow, so that the process difficulty is reduced, the production cost is saved, and the processing time is shortened.

In the technical scheme of the invention, the multi-time slot filling technology is used, and the maximum withstand voltage value of the super junction power device with the angle and subjected to slot filling once is improved, so that the scheme has lower requirement on the verticality of the angle of the deep slot on the device, and even has more obvious optimization effect on the super junction structure with the deep slot with smaller angle. And compared with a vertical deep-groove super-junction structure, the deep-groove super-junction structure with a smaller angle has lower on-resistance, so that a technician can adopt the deep-groove super-junction with the angle under the guidance of the technical scheme of the invention to reduce the on-resistance as much as possible on the premise of not reducing the voltage resistance value.

The following detailed description of the embodiments of the present invention is provided in connection with the accompanying drawings for the purpose of facilitating understanding and understanding of the technical solutions of the present invention.

Drawings

Fig. 1 is a schematic structural diagram of a super junction MOSFET device processed by a uniform epitaxy and uniform trench filling technique;

fig. 2 is one of the schematic structural diagrams of a deep trench super junction MOSFET power device in the present invention;

fig. 3 is a second schematic structural diagram of a deep trench super junction MOSFET power device in the present invention;

FIG. 4 is a graph showing a comparison of electric field curves along A-A' of the devices of FIGS. 1-3.

Wherein: 1. a drain electrode; 2. a substrate; 3. an epitaxial layer; 4. a filling layer; 5. a body region; 6. a source electrode; 7. a source contact layer; 8. a gate oxide layer; 9. a polysilicon gate; 10. a gate dielectric protection layer; 11. a source electrode.

Detailed Description

The invention aims to provide a deep-groove super-junction MOSFET power device and a corresponding preparation method thereof, which are as follows.

The utility model provides a deep groove surpasses knot MOSFET power device, includes by lower supreme drain electrode 1, substrate 2, epitaxial layer 3, somatic region 5, source region, grid structure and the source electrode 11 that sets gradually in proper order, its characterized in that: a plurality of grooves are formed in the epitaxial layer 3 in an etching mode, the grooves are not communicated with one another and are arranged in the vertical direction, the included angle range between the side wall of each groove and the horizontal plane is 80-90 degrees, and the width of the bottom end of each groove is not larger than that of the upper end of each groove.

At least two layers of filling layers 4 are filled in each groove, the number of the filling layers 4 in the grooves is the same, the height of the upper end face of each layer of filling layer 4 is kept consistent, and the doping concentration of the single filling layer 4 in the groove decreases from bottom to top, namely, the filling layer 4 at the lowest layer has the highest doping concentration and the filling layer 4 at the uppermost layer has the lowest doping concentration.

In the application process of the actual scheme, it is emphasized that the trench is filled with a plurality of filling layers 4, and the number of the filling layers 4 and the thickness of each layer of the filling layer 4 can be adjusted according to the actual scheme, which do not affect the overall implementation of the scheme. Under the idea of the present invention, a schematic structural diagram of the trench filled with two filling layers (i.e., after two times of trench filling) is shown in fig. 2, and a schematic structural diagram of the trench filled with five filling layers (i.e., after five times of trench filling) is shown in fig. 3.

The doping type of the substrate 2 is n-type, the doping type of the epitaxial layer 3 is n-type and is formed on the substrate 2, the doping concentration of the epitaxial layer 3 is lower than that of the substrate 2, and the drain electrode 1 is a metalized drain and is positioned below the substrate 2.

The filling layers 4 are made of p-type silicon, the upper end face of each filling layer 4 is kept horizontal, and the side face of each filling layer is in contact with the inner wall of the groove.

In a single groove, with the doping concentration at the central point in the vertical direction of the groove as a reference, the difference between the doping concentration of the filling layer 4 positioned at the uppermost layer and the reference and the difference between the doping concentration of the filling layer 4 positioned at the lowermost layer and the reference do not exceed 50% of the reference.

Compared with the existing super junction MOSFET device processed by the uniform epitaxy and uniform groove filling technology, the voltage withstanding value of the scheme of the invention is obviously improved along with the reduction of the groove angle, and the breakdown voltage can be improved by more than 10% when the included angle between the side wall of the groove and the horizontal plane is 89 degrees.

The doping type of the body region 5 is p-type and is formed above the trenches, and it should be noted here that the epitaxial layer between two adjacent trenches in the horizontal direction is not penetrated by the body region 5.

The source region is formed on the body region 5 and is formed by a source electrode 6 and a source electrode contact layer 7, the source electrode contact layer 7 is located on the outer side of the source electrode 6 in the horizontal direction, the doping type of the source electrode 6 is n-type and the doping concentration of the source electrode 6 is higher than that of the epitaxial layer 3 and the body region 5, the doping type of the source electrode contact layer 7 is p-type and the doping concentration of the source electrode contact layer is higher than that of the body region 5, and ohmic contact is formed between the source electrode 6 and the source electrode contact layer 7 to reduce the forward on resistance.

The grid structure is composed of a grid oxide layer 8, a polycrystalline silicon grid 9 and a grid medium protection layer 10, the grid oxide layer 8 is made of silicon dioxide and covers the body region 5 and the source region, the polycrystalline silicon grid 9 is located on the grid oxide layer 8 and completely covers the upper end face of the grid oxide layer 8, and the grid medium protection layer 10 is made of an insulating material and is located above and covers the grid oxide layer 8 and the polycrystalline silicon grid 9.

The source electrode 11 is located above the source region and the gate structure, and the lower end surface of the source electrode 11 is in contact with the upper end surfaces of the source electrode 6 and the source contact layer 7 respectively.

In summary, the structure of the deep-trench super-junction MOSFET power device provided by the invention is optimized under the condition that the doping concentration of the epitaxial layer of the device is not changed, and the epitaxial layer with the doping concentration changing linearly is not required to grow, so that the process difficulty is reduced, the production cost is saved, and the processing time is shortened.

In addition, the voltage resistance is improved, meanwhile, the on-resistance of the trapezoidal super junction is hardly increased, and when the angle of a groove of the existing super junction MOSFET device processed by utilizing the uniform epitaxy and uniform groove filling technology is changed from 90 degrees to 89 degrees, the reverse withstand voltage is reduced by about 10 percent, and the on-resistance is improved by about 10 percent. By using the scheme of the invention, the voltage withstanding value of the MOSFET device with the groove angle of 89 degrees can be improved to the level which is equal to the voltage withstanding value of the MOSFET device with the vertical groove, and the on-resistance is improved by less than 2 percent. As can be seen from FIG. 4, as the number of times of filling the grooves increases, the electric field curve along A-A' is closer to the ideal rectangle, and the voltage resistance is stronger.

Corresponding to the product scheme, the scheme of the invention also comprises a preparation method of the deep-groove super-junction MOSFET power device, which is used for processing the deep-groove super-junction MOSFET power device and comprises the following steps:

s1, taking a substrate 2, forming a dense epitaxial layer 3 on the substrate, then forming a plurality of grooves on the epitaxial layer 3 by utilizing an etching process, controlling the included angle range between the side wall of each groove and the horizontal plane to be 80-90 degrees, and ensuring that the grooves are not communicated with each other and are arranged along the vertical direction;

s3, forming a body region 5 on the upper end face of the epitaxial layer 3 by using the process of ion implantation and annealing diffusion, and then forming a source region on the upper end face of the body region 5 by using the process of ion implantation and annealing diffusion again;

s4, combining the gate oxide layer 8, the polysilicon gate 9 and the gate dielectric protection layer 10 in sequence from bottom to top to form a gate structure, and then arranging the gate structure on the body region 5 and the source region;

s5, disposing the source electrode 11 above the source region and the gate structure, so as to ensure that the lower end surface of the source electrode 11 is in contact with the upper end surfaces of the source electrode 6 and the source contact layer 7, respectively;

and S6, arranging the drain electrode 1 below the substrate 2, and ensuring that the upper end face of the drain electrode 1 is in contact with the lower end face of the substrate 2.

The preparation method can be seen that the scheme of the invention also provides reference for other related problems in the same field, can be expanded and extended on the basis of the reference, is applied to related schemes of other MOSFET technologies in the field, and has a very wide application prospect.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein, and any reference signs in the claims are not intended to be construed as limiting the claim concerned.

Finally, it should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should integrate the description, and the technical solutions in the embodiments can be appropriately combined to form other embodiments understood by those skilled in the art.

Claims

1. A deep-trough super-junction MOSFET power device, comprising a drain electrode (1), a substrate (2), an epitaxial layer (3), a body region (5), a source region, a gate, which are sequentially arranged from bottom to top The electrode structure and the source electrode (11) are characterized in that: a plurality of trenches are formed by etching in the epitaxial layer (3), the plurality of trenches are not connected to each other and are all arranged in a vertical direction, the The angle between the sidewall of the trench and the horizontal plane ranges from 80° to 90°, and the width of the bottom end of the trench is not greater than the width of the upper end; each of the trenches is filled with at least two layers of filling layers (4 ), the number of filling layers (4) in a plurality of the trenches is the same, and the height of the upper end face of each filling layer (4) remains the same, and the doping concentration of a single filling layer (4) in the trench is from bottom to top Decrease.

2. A deep trench superjunction MOSFET power device according to claim 1, characterized in that: the doping type of the substrate (2) is n-type, and the doping type of the epitaxial layer (3) is n-type and formed on the substrate (2), the doping concentration of the epitaxial layer (3) is lower than the doping concentration of the substrate (2), and the drain electrode (1) is located on the below the substrate (2).

3 . The deep trench superjunction MOSFET power device according to claim 1 , wherein the material of the filling layer ( 4 ) is p-type silicon, and the upper end face of each layer of the filling layer ( 4 ) keeps The horizontal, side faces are in contact with the inner wall of the groove.

4 . The deep trench superjunction MOSFET power device according to claim 1 , wherein in a single trench, based on the doping concentration at the center point in the vertical direction of the trench, the The difference between the doping concentration of the uppermost filling layer (4) and the reference and the difference between the doping concentration of the filling layer (4) located in the lowermost layer and the reference do not exceed 50% of the reference.

5 . The deep trench super-junction MOSFET power device according to claim 1 , wherein the doping type of the body region ( 5 ) is p-type and is formed above the trench in a horizontal direction. 6 . , the epitaxial layer between two adjacent trenches will not be penetrated by the body region (5).

6 . The deep trench superjunction MOSFET power device according to claim 1 , wherein the source region is formed on the body region ( 5 ), and consists of a source electrode ( 6 ) and a source electrode contact layer. 7 . (7) Commonly formed, in the horizontal direction, the source contact layer (7) is located outside the source (6), the source (6) doping type is n-type and its doping concentration Higher than the epitaxial layer (3) and the body region (5), the doping type of the source contact layer (7) is p-type and its doping concentration is higher than that of the body region (5), so An ohmic contact is formed between the source electrode (6) and the source electrode contact layer (7).

7 . The deep trench superjunction MOSFET power device according to claim 1 , wherein the gate structure is composed of a gate oxide layer ( 8 ), a polysilicon gate ( 9 ) and a gate dielectric protection layer ( 10 ). 8 . ) together, the gate oxide layer (8) is made of silicon dioxide and covers the body region (5) and the source region, and the polysilicon gate (9) is located on the gate Above the oxide layer (8) and completely covering the upper end surface of the gate oxide layer (8), the gate dielectric protection layer (10) is made of an insulating material and is located on the gate oxide layer (8) and the gate oxide layer (8). The polysilicon gates (9) are placed above the two and the two are covered inside.

8 . The deep trench superjunction MOSFET power device according to claim 6 , wherein the source electrode ( 11 ) is located above the source region and the gate structure, and the source electrode ( 11 ) is located above the source region and the gate structure. 9 . The lower end surfaces of 11) are respectively in contact with the upper end surfaces of the source electrode (6) and the source electrode contact layer (7).

9. a preparation method of deep groove super junction MOSFET power device, for processing a kind of deep groove super junction MOSFET power device as described in any one of claim 1～8, is characterized in that, comprises the steps:

S1. Take a substrate (2), form a dense epitaxial layer (3) on it, and then use an etching process to open a plurality of trenches on the epitaxial layer (3) to control the size of the trenches The included angle between the side wall and the horizontal plane ranges from 80° to 90°, ensuring that a plurality of the grooves are not connected to each other and are all arranged in the vertical direction;

S2, using p-type silicon to fill the trenches for several times until the trench is completely filled, and during the filling process, the doping concentration of the p-type silicon used decreases sequentially with the filling times;

S3. A body region (5) is formed on the upper end face of the epitaxial layer (3) by using the process of ion implantation, annealing and diffusion, and then the body region (5) is formed by the process of ion implantation, annealing and diffusion again. The end face forms a layer of source region;

S4. The gate oxide layer (8), the polysilicon gate (9) and the gate dielectric protection layer (10) are combined in order from bottom to top to form a gate structure, and then the gate structure is arranged on the a body region (5) and above the source region;

S5. Disposing the source electrode (11) above the source region and the gate structure to ensure that the lower end surface of the source electrode (11) is in contact with the source electrode (6) and the source electrode respectively The upper end faces of the layer (7) are in contact with each other;

S6. Disposing the drain electrode (1) under the substrate (2), ensuring that the upper end surface of the drain electrode (1) is in contact with the lower end surface of the substrate (2).