CN113838830A - Package substrates and flip-chip packages - Google Patents
Package substrates and flip-chip packages Download PDFInfo
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- CN113838830A CN113838830A CN202010582715.8A CN202010582715A CN113838830A CN 113838830 A CN113838830 A CN 113838830A CN 202010582715 A CN202010582715 A CN 202010582715A CN 113838830 A CN113838830 A CN 113838830A
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- 239000000758 substrate Substances 0.000 title claims abstract description 84
- 229910000679 solder Inorganic materials 0.000 claims abstract description 11
- 238000004806 packaging method and process Methods 0.000 claims description 23
- 239000011159 matrix material Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 238000009826 distribution Methods 0.000 abstract description 4
- 238000003466 welding Methods 0.000 description 25
- 238000010586 diagram Methods 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000003796 beauty Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
Abstract
本发明提供一种封装基板及倒装芯片封装组件，所述封装基板上的焊垫呈长条状，至少部分所述焊垫的延伸方向与其他所述焊垫的延伸方向不同；在所述封装基板与所述芯片相焊接过程中，芯片上的至少部分所述导电凸块受到的应力的主方向与其他部分所述导电凸块受到的应力的主方向不同，整个芯片上受到的应力方向比较分散，优化所述芯片受到的应力分布，且不同方向的应力能够有一定的抵消作用，从而，即使所述芯片受到外部的作用力，如机台的震动等，所述芯片也不易产生偏移，能够有效避免导电凸块与对应的焊垫之间接触不良的情况发生，同时降低了相邻焊垫之间桥接短路的几率。
The present invention provides a package substrate and a flip-chip package assembly. The solder pads on the package substrate are elongated, and at least some of the solder pads extend in a direction different from that of other solder pads; During the bonding process between the package substrate and the chip, the main direction of the stress on at least part of the conductive bumps on the chip is different from the main direction of the stress on other parts of the conductive bumps, and the stress direction on the entire chip is It is relatively dispersed, the stress distribution on the chip is optimized, and the stress in different directions can have a certain offset effect, so that even if the chip is subjected to external forces, such as vibration of the machine, the chip is not easy to be biased. It can effectively avoid the occurrence of poor contact between the conductive bump and the corresponding pad, and at the same time reduce the probability of bridging and short circuit between adjacent pads.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a packaging substrate capable of reducing flip chip offset and a flip chip packaging assembly with the packaging substrate.
Background
The flip chip packaging technology is characterized in that a chip is arranged on a packaging substrate in a downward mode in the front face, a conductive lug is arranged on one side, facing the packaging substrate, of the chip, welding pads in one-to-one correspondence with the conductive lugs are arranged on the packaging substrate, the conductive lugs are electrically connected with the corresponding welding pads to achieve fixed connection and electrical connection between the chip and the packaging substrate, lead bonding is not needed, a shortest circuit is formed, resistance is reduced, the packaging size is reduced, and the light, thin and short packaging requirements can be met.
As shown in fig. 1, which is a package substrate 1 in the prior art, the bonding pads 11 are generally in a long strip shape, such as an oval shape, a rectangle shape, etc., and most of the extending directions of the bonding pads are parallel to each other, after the chip is fixedly connected to the package substrate, the conductive bumps are located at the centers of the corresponding bonding pads, and the stress of the chip is easily accumulated and accumulated in the extending directions of the bonding pads in the same direction, so that the stress of the chip in the extending directions is much greater than that in other directions, at this time, if there is an influence of an external environment, such as vibration of a machine, etc., the chip is easily deviated, causing situations of a short circuit between the bonding pads or poor contact between the conductive bumps and the corresponding bonding pads.
In view of the above, it is desirable to provide a novel package substrate and a flip chip package assembly having the same to solve the above problems.
Disclosure of Invention
The invention aims to provide a packaging substrate capable of reducing flip chip offset and a flip chip packaging assembly with the packaging substrate.
In order to achieve the purpose, the invention adopts the following technical scheme: a packaging substrate comprises a substrate and a plurality of welding pads arranged on the substrate; the welding pads are in a long strip shape, and the extending direction of at least part of the welding pads is different from the extending direction of other welding pads.
As a further improved technical solution of the present invention, the substrate includes a plurality of sub-regions, the extending directions of the plurality of pads in each sub-region are parallel, and the extending directions of the pads in the adjacent sub-regions are different.
As a further improved technical solution of the present invention, a plurality of the sub-regions are arranged row by row, or a plurality of the sub-regions are arranged column by column, or a plurality of the sub-regions are arranged in a matrix, or a plurality of the sub-regions are arranged in sequence along a circumferential direction.
As a further improved technical scheme of the invention, the included angle between the extending direction of at least part of the welding pads and the straight line of the extending direction of other welding pads is 90 degrees.
As a further improved technical scheme of the invention, the included angle between the straight line of the extending direction of the welding pad and the horizontal line is 0 degree, or 90 degrees, or 45 degrees, or 135 degrees.
As a further improved technical scheme of the invention, the welding pad is oval or rectangular.
As a further improved technical solution of the present invention, the package substrate further includes a substrate circuit disposed on the substrate, and the pad is connected to the substrate circuit; the distance between adjacent substrate lines is the same as the width of the substrate lines.
In order to achieve the above object, the present invention further provides a flip chip package assembly, which includes a chip and the package substrate, wherein the chip is provided with a plurality of conductive bumps; the welding pads correspond to the conductive bumps one by one.
As a further improved technical scheme of the invention, the distance between the conductive bump and the adjacent welding pad is more than 15 μm.
As a further improved technical scheme of the invention, the distance between the adjacent conductive bumps is more than 40 μm.
The invention has the beneficial effects that: according to the packaging substrate, the extending direction of at least part of the welding pads is set to be different from the extending direction of other welding pads, in the welding process of the packaging substrate and the chip, the main direction of stress borne by at least part of the conductive bumps on the chip is different from the main direction of stress borne by other parts of the conductive bumps, the stress directions borne by the whole chip are relatively dispersed, the stress distribution borne by the chip is optimized, and the stresses in different directions can be offset to a certain extent, so that even if the chip is subjected to external acting force, such as vibration of a machine table and the like, the chip is not easy to offset, the condition that the contact between the conductive bumps and the corresponding welding pads is poor can be effectively avoided, and the probability of bridging short circuit between the adjacent welding pads is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a package substrate in the prior art.
Fig. 2 is a schematic structural diagram of a package substrate according to a first embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a package substrate according to a second embodiment of the invention.
Fig. 4 is a schematic structural diagram of a package substrate according to a third embodiment of the present invention.
Fig. 5 is an enlarged schematic view of a structure at a in fig. 4.
Fig. 6 is a schematic structural diagram of another embodiment of a package substrate according to a third embodiment of the invention.
Fig. 7 is an enlarged schematic view of the structure at B in fig. 6.
Fig. 8 is a schematic structural diagram of a package substrate according to a fourth embodiment of the present invention.
Fig. 9 is a schematic structural view of a flip chip package assembly in the present invention.
Fig. 10 is a schematic view of a structure of the bonding pad and the conductive bump in the invention.
Detailed Description
The present invention will be described in detail with reference to the embodiments shown in the drawings, and reference is made to fig. 2 to 10, which are preferred embodiments of the present invention. It should be noted that these embodiments are not intended to limit the present invention, and those skilled in the art should be able to make functional, methodical, or structural equivalents or substitutions according to these embodiments without departing from the scope of the present invention.
It should be noted that fig. 2-8 illustrate the package substrate of the present invention, and for convenience of describing the position relationship between the conductive bumps in the chip and the bonding pads on the package substrate, the conductive bumps are shown together in fig. 2-8.
Referring to fig. 2 to 10, the present invention provides a package substrate 2, which includes a substrate 21 and a plurality of bonding pads 22 disposed on the substrate 21, wherein the package substrate 2 is used to cooperate with a flip chip 3, the bonding pads 22 correspond to conductive bumps 31 on the chip 3 one by one, one end of each conductive bump 31 facing the bonding pad 22 has a solder, and the conductive bumps 31 and the corresponding bonding pads 22 are soldered together by the solder, so as to realize the fixed connection and the electrical connection between the package substrate 2 and the chip 3.
The package substrate 2 of the present invention can adopt the conventional design except for the bonding pad 22, and thus, the details thereof are not repeated.
The bonding pads 22 are in an elongated shape, and it can be understood that, in the process of bonding the package substrate 2 and the chip 3, the stress applied to the conductive bumps 31 in the extending direction of the corresponding elongated bonding pads 22 is greater than that applied to the other directions. The extending direction of the pad 22 refers to the extending direction of the length of the pad 22.
Specifically, the pad 22 may be configured to be oval or rectangular; of course, this is not a limitation.
At least part the extending direction of the welding pad 22 is different from the extending direction of other welding pads 22, in the process of welding the packaging substrate 2 and the chip 3, the main direction of the stress received by the conductive bump 31 is different from the main direction of the stress received by the conductive bump 31, the stress directions received by the whole chip 3 are relatively dispersed, the stress distribution received by the chip 3 is optimized, and the stresses in different directions can have certain counteraction effect, therefore, even if the chip 3 is subjected to external acting force, such as vibration of a machine table and the like, the chip 3 is not easy to generate deviation, poor contact between the conductive bump 31 and the corresponding welding pad 22 can be effectively avoided, and the probability of short circuit bridging between the adjacent welding pads 22 is reduced.
In a specific embodiment, an included angle between the extending direction of at least a portion of the bonding pads 22 and the straight line of the extending direction of the other bonding pads 22 is 90 °, and in the process of welding the package substrate 2 and the chip 3, the chip 3 is subjected to perpendicular stresses, and the offset effect between the perpendicular stresses is large, so that the chip 3 is not easy to generate offset, the processing of the bonding pads 22 is facilitated, and the neatness and the attractiveness of the whole package substrate 2 are enhanced; of course, this is not a limitation.
Further, in an embodiment where an included angle between the extending direction of at least some of the pads 22 and the straight line of the extending direction of other pads 22 is 90 °, an included angle between the straight line of the extending direction of the pads 22 and the horizontal line is set to be 0 °, or 90 °, or 45 °, or 135 °, which facilitates processing of the pads 22 and enhances the overall neatness and beauty of the package substrate 2; it can be understood that, when an angle between a line in which the extending direction of at least a portion of the pads 22 is located and a horizontal line is 0 °, an angle between a line in which the extending direction of another portion of the pads 22 is located and the horizontal line is 90 °, and when an angle between a line in which the extending direction of at least a portion of the pads 22 is located and the horizontal line is 45 °, an angle between a line in which the extending direction of another portion of the pads 22 is located and the horizontal line is 135 °; of course, this is not a limitation.
Further, the substrate 21 includes a plurality of sub-regions, the extending directions of the plurality of pads 22 in each sub-region are parallel, the extending directions of the pads 22 in adjacent sub-regions are different, so as to facilitate the modular arrangement of the plurality of pads 22, and simplify the preparation of the package substrate 2, in the process of welding the package substrate 2 and the chip 3, the main directions of the stresses applied to the conductive bumps 31 corresponding to each sub-region are the same, and the main directions of the stresses applied to the conductive bumps 31 corresponding to two adjacent sub-regions are different, that is, the main directions of the stresses applied to the regions corresponding to two adjacent sub-regions on the chip 3 are different, so that the directions of the stresses on the chip 3 are relatively dispersed, and the stresses in different directions can have a certain counteracting effect, and thus the chip 3 is not easy to generate an offset.
In an embodiment where an included angle between the extending direction of at least some of the pads 22 and a straight line where the extending directions of other pads 22 are located is 90 °, an included angle between straight lines where the extending directions of the pads 22 in the adjacent sub-regions are located is 90 °.
Further, referring to fig. 2, in the first embodiment of the present invention, the sub-regions are arranged in rows, that is, the extending directions of the pads 22 in each row are parallel, and the extending directions of the pads 22 in adjacent rows are different.
Specifically, in the present embodiment, the included angle of the straight line in which the extending directions of the pads 22 in the adjacent columns are located is 90 °, which is not limited to this.
Specifically, the angle α between the line in which the extending direction of the pad 22 in the first column is located and the horizontal line is 90 °, the angle α between the line in which the extending direction of the pad 22 in the second column is located and the horizontal line is 0 °, and so on, and of course, this is not a limitation, i.e., the angle between the line in which the extending direction of the pad 22 is located and the horizontal line is not limited to 0 ° and 90 °, and may be set to 45 ° or 135 °, or other angles, as long as the angle between the line in which the extending direction of the pad 22 in the adjacent column is 90 °.
Referring to fig. 3, in the second embodiment of the present invention, the sub-regions are arranged row by row, that is, the extending directions of the pads 22a in each row are parallel, and the extending directions of the pads 22a in adjacent rows are different.
Specifically, in the present embodiment, the included angle of the straight line along which the extending directions of the pads 22a in the adjacent rows are located is 90 °, which is not limited to this.
Specifically, in this embodiment, an angle α between a line in which the extending direction of the pad 22a in the first row is located and a horizontal line is 45 °, an angle α between a line in which the extending direction of the pad 22a in the second row is located and a horizontal line is 135 °, and so on, but not limited thereto, that is, an angle between a line in which the extending direction of the pad 22a is located and a horizontal line is not limited to 45 ° and 135 °, and may be set to 0 ° or 90 °, or other angles as long as an angle between a line in which the extending direction of the pad 22a in an adjacent row is 90 °.
In the third embodiment of the present invention, the sub-regions are sequentially arranged along a circumferential direction, that is, the extending directions of the pads in each sub-region are parallel, and the extending directions of the pads in the sub-regions adjacent to each other along the circumferential direction are different.
Specifically, referring to the specific embodiment shown in fig. 4-5, the region where the plurality of pads 22b are located is rectangular, and the region is divided into four sub-regions along the diagonal lines (i.e., the separation lines) of the rectangular region where the plurality of pads 22b are located, and the sub-regions are sequentially arranged along the circumferential direction of the center of the rectangular region, it can be understood that the region where the plurality of pads 22b are located may also be square; in another embodiment shown in fig. 6-7, the plurality of pads 22c are distributed in a square matrix, and are divided into four sub-regions along a central line (i.e., a separation line) of a square region where the plurality of pads 22c are located, and the sub-regions are sequentially arranged along a circumferential direction of the center of the square region; of course, the number of the pads may be circular, and the circular area is sequentially divided into a plurality of sub-areas along the circumferential direction of the circular area.
Specifically, in the present embodiment, the included angle between the straight lines along which the extending directions of the pads 22b and 22c in the adjacent sub-regions are located is 90 °, which is not limited to this.
Specifically, in the embodiment shown in fig. 4 to 5, an angle α between a straight line where the extending direction of the pad 22b in one of the two adjacent sub-regions is located and a horizontal line is 90 °, an angle α between a straight line where the extending direction of the pad 22b in the other sub-region is located and a horizontal line is 0 °, and so on, and of course, the present invention is not limited thereto, that is, an angle between a straight line where the extending direction of the pad 22b is located and a horizontal line is not limited to 0 ° or 90 °, and may be set to 45 ° or 135 °, or other angles, as long as an angle between a straight line where the extending direction of the pad 22b in the two adjacent sub-regions is 90 °.
Specifically, in another embodiment shown in fig. 6 to 7, an angle α between a straight line where the extending direction of the pad 22c in one of the two adjacent sub-regions is located and a horizontal line is 135 °, an angle α between a straight line where the extending direction of the pad 22c in the other sub-region is located and a horizontal line is 45 °, and so on, of course, this is not limited thereto, that is, an angle between a straight line where the extending direction of the pad 22c is located and a horizontal line is not limited to 45 ° and 135 °, and may be set to 0 ° or 90 °, or other angles as long as an angle between a straight line where the extending direction of the pad 22c in the two adjacent sub-regions is 90 °.
Meanwhile, in the embodiment in which a plurality of the sub-regions are arranged in sequence in one circumferential direction, the extending direction of the pads 22b, 22c located on the separation line is not particularly limited. In the embodiment shown in fig. 4-5, the extending directions of the pads 22b on the diagonal line (i.e., the separation line) are the same, and the included angle α between the straight line and the horizontal line is 0 °, and in other embodiments, the extending directions of the pads 22b, 22c on the diagonal line (i.e., the separation line) may be different.
Referring to fig. 8, in the fourth embodiment of the present invention, the sub-regions are arranged in a matrix form, that is, the extending directions of the bonding pads 22d in each sub-region are parallel, and the extending directions of the bonding pads 22d in two adjacent sub-regions are different.
It is understood that, in the present embodiment, the two adjacent sub-regions include two sub-regions that are laterally adjacent and vertically adjacent.
Specifically, in the present embodiment, the included angle of the straight line along which the extending direction of the pad 22d in the adjacent sub-regions is 90 °, which is not limited to this.
Specifically, an angle α between a straight line where the extending direction of the pad 22d in one of the two adjacent sub-regions is located and a horizontal line is 45 °, an angle α between a straight line where the extending direction of the pad 22d in the other sub-region is located and a horizontal line is 135 °, and so on, and certainly, the included angle is not limited thereto, that is, the included angle between the straight line where the extending direction of the pad 22d is located and the horizontal line is not limited to 45 ° and 135 °, and may be set to 0 ° or 90 °, or other angles as long as the included angle between the straight line where the extending direction of the pad 22d in the two adjacent sub-regions is 90 °.
Of course, the separation manner of the sub-regions is not limited to the first to fourth embodiments, and the sub-regions may be separated in other manners, which is not described herein again.
Further, the package substrate 2 further includes a substrate circuit (not shown) disposed on the substrate 21, and the pads 22, 22a, 22b, 22c, and 22d are connected to the substrate circuit; the distance between adjacent substrate lines is the same as the width of the substrate lines, and specifically, the distance between adjacent substrate lines refers to the distance between two adjacent pads 22, 22a, 22b, 22c, 22 d.
Further, referring to fig. 9, the present invention also provides a flip chip package assembly 100, which includes a chip 3 and the package substrate 2, wherein the chip 3 is provided with a plurality of conductive bumps 31, and the bonding pads 22, 22a, 22b, 22c, and 22d are in one-to-one correspondence with the conductive bumps 31.
Referring to fig. 10, the length L and the width W of the pads 22, 22a, 22b, 22c, 22d and the diameter R of the conductive bump are related as follows: w is more than or equal to 25 microns and less than or equal to 0.7R microns, L is more than or equal to R +25 microns, on one hand, the width of the welding pads 22, 22a, 22b, 22c and 22d is less than the diameter of the conductive bump 31, after the chip 3 is welded with the packaging substrate 2, part of the structure of the conductive bump 31 covers the insulating layer of the packaging substrate 2, a certain limiting effect can be achieved on the conductive bump 31, and the chip 3 is further prevented from deviating; on the other hand, the length of the pads 22, 22a, 22b, 22c, 22d is greater than the diameter of the conductive bump 31, so that when the chip 3 and the package substrate 2 are packaged by a machine, a certain offset is relatively generated between the two, and under the condition that a small offset is ensured, the conductive bump 31 can be in good contact with the corresponding pads 22, 22a, 22b, 22c, 22 d.
After the package substrate 2 and the chip 3 are soldered, the distance between the conductive bump 31 and the adjacent pads 22, 22a, 22b, 22c, and 22d is set to be greater than 15 μm, and an offset is preset to prevent a short circuit between the conductive bump 31 and the adjacent substrate circuit due to the offset of the chip 3.
Further, the distance between the adjacent conductive bumps 31 is greater than 40 μm, and the gap width between the adjacent conductive bumps 31 is increased to provide a larger filler flowing space, which is beneficial for the subsequent glue filling process between the chip 3 and the package substrate 2.
In summary, in the package substrate 2 of the present invention, by setting the extending direction of at least some of the pads 22, 22a, 22b, 22c, and 22d to be different from the extending direction of other pads 22, 22a, 22b, 22c, and 22d, during the process of soldering the package substrate 2 and the chip 3, the main direction of the stress applied to at least some of the conductive bumps 31 on the chip 3 is different from the main direction of the stress applied to other portions of the conductive bumps 31, the stress applied to the entire chip 3 is relatively distributed, the stress distribution applied to the chip 3 is optimized, and the stresses in different directions can have a certain counteracting effect, so that even if the chip 3 is subjected to an external acting force, such as vibration of a machine, the chip 3 is not easily deviated, and the conductive bumps 31 and the corresponding pads 22 can be effectively avoided from being deviated from each other, and the conductive bumps 31 and the corresponding pads 22 can be vibrated by the machine, and the like, 22a, 22b, 22c, 22d, while reducing the chance of bridging shorts between adjacent pads 22, 22a, 22b, 22c, 22 d.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010582715.8A CN113838830A (en) | 2020-06-23 | 2020-06-23 | Package substrates and flip-chip packages |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010582715.8A CN113838830A (en) | 2020-06-23 | 2020-06-23 | Package substrates and flip-chip packages |
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| CN113838830A true CN113838830A (en) | 2021-12-24 |
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| CN202010582715.8A Pending CN113838830A (en) | 2020-06-23 | 2020-06-23 | Package substrates and flip-chip packages |
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| CN103367293A (en) * | 2012-03-27 | 2013-10-23 | 联发科技股份有限公司 | Semiconductor package |
| CN110447099A (en) * | 2017-04-20 | 2019-11-12 | 罗姆股份有限公司 | Semiconductor devices |
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2020
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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