CN113821068A

CN113821068A - Multi-power system management circuit and method in chip

Info

Publication number: CN113821068A
Application number: CN202111097765.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Sichuan Chuang'an Microelectronics Co ltd
Current assignee: Sichuan Chuang'an Microelectronics Co ltd
Priority date: 2021-09-18
Filing date: 2021-09-18
Publication date: 2021-12-21
Anticipated expiration: 2041-09-18
Also published as: CN113821068B

Abstract

The invention discloses a multi-power system management circuit and a method thereof in a chip, wherein the multi-power system management circuit comprises a booster circuit, a first pull-down circuit and a plurality of delay circuits; one end of the booster circuit is connected with an external reset signal, the other end of the booster circuit is connected with a first pull-down circuit, the first pull-down circuit is connected with the input end of a first delay circuit, and the output end of the first delay circuit outputs a reset signal 1; the output end of the first delay circuit is also connected with a second delay circuit, and the output end of the second delay circuit outputs a reset signal 2; … … the output end of the N-1 th delay circuit is also connected with the Nth delay circuit, the output end of the Nth delay circuit outputs the reset signal N; each reset signal is connected to each functional unit in the chip; each delay circuit is correspondingly connected to a corresponding power supply system VDD; the multi-power system management circuit realizes that the reset state of the chip is sequentially released after each power system is powered on, and the chip enters the reset state in time when the power is off.

Description

Multi-power system management circuit and method in chip

Technical Field

The invention relates to the technical field of power management inside a chip, in particular to a multi-power system management circuit and a method inside the chip.

Background

In the process of supplying power to the chip by an external power supply, the common mode is that the power is divided by a voltage divider and then supplied to each functional unit in the chip, and each functional unit corresponds to one power supply system, so that a plurality of power supply systems are arranged in the chip. Due to the fact that certain delay exists in the transmission process, the power supply systems detect the voltages in a certain sequence. This results in the functional unit that first detects the voltage being powered up first and then the functional unit that detects the voltage being powered up later, rather than in the required order.

In a word, abnormal actions of the chip are likely to occur in the power-on process and the power-down process of each power supply system when the chip is powered on. Therefore, a circuit and a method for managing multiple power supplies inside a chip are needed.

Disclosure of Invention

The invention aims to solve the technical problem that abnormal actions of chips are likely to occur in the power-on process and the power-off process of each power supply system when the chips are powered on. The invention aims to provide a multi-power system management circuit and a method in a chip, which can realize that the reset state of the chip is sequentially released after the power supply is powered on, and the chip enters the reset state in time when the power failure occurs.

The invention is realized by the following technical scheme:

in a first aspect, the present invention provides a multi-power system management circuit on a chip, the multi-power system management circuit comprising a boost circuit, a first pull-down circuit, and a plurality of delay circuits, the plurality of delay circuits comprising a first delay circuit, a second delay circuit, … …, an N-1 th delay circuit, an nth delay circuit;

one end of the booster circuit is connected with an external reset signal, the other end of the booster circuit is connected with a first pull-down circuit, the first pull-down circuit is connected with the input end of a first delay circuit, and the output end of the first delay circuit outputs a reset signal 1; the output end of the first delay circuit is also connected with a second delay circuit, and the output end of the second delay circuit outputs a reset signal 2; … …, the output end of the N-1 th delay circuit is connected with the Nth delay circuit, and the output end of the Nth delay circuit outputs a reset signal N; each reset signal is connected to each functional unit in the chip;

the boosting circuit is connected to a first power system VDD1, the first delay circuit is connected to a first power system VDD1, the second delay circuit is connected to second power systems VDD2 and … …, the N-1 th delay circuit is connected to a second power system VDD (N-1), and the N-th delay circuit is connected to an N-th power system VDDN;

the multi-power system management circuit realizes that the reset state of the chip is sequentially released after each power system is powered on, and the chip enters the reset state in time when the power is off.

Furthermore, each delay circuit adopts a delay circuit with threshold voltage detection, and the delay circuit with threshold voltage detection comprises a first inverter, an RC circuit, a threshold voltage detection circuit, a fourth pull-down circuit and a second inverter;

the first phase inverter is connected with an RC circuit, the RC circuit is connected with a threshold voltage detection circuit, the threshold voltage detection circuit is connected with a fourth pull-down circuit, the fourth pull-down circuit is connected with a second phase inverter, and the second phase inverter outputs a corresponding reset signal; the output end of the first inverter is marked as point A, and the output end of the RC circuit is marked as point B;

the threshold voltage detection circuit comprises P-channel type MOS tubes MP2, MP3, MP4 and MP5, N-channel type MOS tubes MN2, MN3, MN4 and MN5, wherein the source electrode of the MOS tube MP2 is connected with a corresponding power supply system, the gate electrode of the MOS tube MP2 is connected with the gate electrode of the MOS tube MP3, the drain electrode of the MOS tube MP2 is connected with the source electrode of the MOS tube MP3, the drain electrode of the MOS tube MP3 is connected with the drain electrode of the MOS tube MN3, the gate electrode of the MOS tube MN3 is connected with the gate electrode of the MOS tube MN2, the source electrode of the MOS tube MN3 is connected with the drain electrode of the MOS tube MN2, and the source electrode of the MOS tube MN2 is grounded; the common end of the grid of the MOS transistor MP2 and the grid of the MOS transistor MP3 is connected with the common end of the grid of the MOS transistor MN3 and the grid of the MOS transistor MN2, and is connected with the output end of the RC circuit;

the common end of the drain of the MOS tube MP2 and the source of the MOS tube MP3 is connected with the source of the MOS tube MP4, the gate of the MOS tube MP4 is connected with the drain of the MOS tube MP5, the drain of the MOS tube MP4 is connected with the drain of the MOS tube MN4, the source of the MOS tube MN4 is connected with the common end of the source of the MOS tube MN3 and the drain of the MOS tube MN2, the gate of the MOS tube MN4 is connected with the drain of the MOS tube MN5, the source of the MOS tube MN5 is grounded, the gate of the MOS tube MN5 is connected with the gate of the MOS tube MP5, and the source of the MOS tube MP5 is connected with a corresponding power supply system;

the common end of the drain of the MOS transistor MP3 and the drain of the MOS transistor MN3 is connected with the common end of the drain of the MOS transistor MP4 and the drain of the MOS transistor MN4, and the common end of the drain of the MOS transistor MP4 and the drain of the MOS transistor MN4 is connected with the common end of the gate of the MOS transistor MN5 and the gate of the MOS transistor MP 5; the common end of the drain electrode of the MOS transistor MP5 and the drain electrode of the MOS transistor MN5 is connected with a fourth pull-down circuit;

the common end of the drain electrode of the MOS transistor MP4 and the drain electrode of the MOS transistor MN4 is used as a point C, and the common end of the drain electrode of the MOS transistor MP5 and the drain electrode of the MOS transistor MN5 is used as a point D;

when the threshold voltage detection circuit works: when the level of the node B is changed from low to high, the MOS tubes MN2, MN3 and MN4 are conducted, positive feedback is formed by a loop from a point C, the MOS tube MP5 and a loop from the MOS tube MN4 to the point C, impedance changes (the MOS tubes MN3 and MN4 are connected in parallel and then connected in series with the MOS tube MN 2), and the threshold voltage is increased to a first threshold Vthr;

when the level of the node B changes from high to low, the MOS transistors MP2, MP3, and MP4 are turned on, and a positive feedback is formed by the loop from the point C, MN5, and MP4 to the point C, the impedance changes (the MOS transistors MP3 and MP4 are connected in parallel, and then connected in series with the MOS transistor MP 2), and the threshold voltage is reduced to the second threshold Vthd.

Furthermore, the RC circuit includes a resistor R and a capacitor C, one end of the resistor R is connected to the output end of the first inverter, the other end of the resistor R is connected to the capacitor C, and the capacitor C is grounded;

the first phase inverter comprises a P-channel type MOS tube MP1 and an N-channel type MOS tube MN1, the source electrode of the MOS tube MP1 is connected with a corresponding power supply system, the grid electrode of the MOS tube MP1 is connected with the grid electrode of the MOS tube MN1, the drain electrode of the MOS tube MP1 is connected with the drain electrode of the MOS tube MN1, and the source electrode of the MOS tube MN1 is grounded; the drain electrode of the MOS tube MP1 and the common end of the drain electrode of the MOS tube MN1 are connected with a resistor R;

the second phase inverter comprises a P-channel type MOS tube MP6 and an N-channel type MOS tube MN6, the source electrode of the MOS tube MP6 is connected with a corresponding power supply system, the grid electrode of the MOS tube MP6 is connected with the grid electrode of the MOS tube MN6, the drain electrode of the MOS tube MP6 is connected with the drain electrode of the MOS tube MN6, and the source electrode of the MOS tube MN6 is grounded; the common end of the grid of the MOS tube MP6 and the grid of the MOS tube MN6 is connected with the fourth pull-down circuit, and the common end of the drain of the MOS tube MP6 and the drain of the MOS tube MN6 is used as an output end.

Furthermore, the first pull-down circuit and the fourth pull-down circuit are both realized in a resistor or MOS tube mode.

Furthermore, the output end of each delay circuit is connected with a second pull-down circuit, and each delay circuit outputs a corresponding reset signal after passing through the corresponding second pull-down circuit;

the second pull-down circuit is realized by adopting a resistor or MOS mode.

Further, the boost circuit comprises a third pull-down circuit, an N-channel MOS transistor MN7, a P-channel MOS transistor MP7, and an N-channel MOS transistor MN 8;

one end of the third pull-down circuit is connected with an external reset signal, the other end of the third pull-down circuit is connected with the grid electrode of the MOS tube MN7, the source electrode of the MOS tube MN7 is grounded, the drain electrode of the MOS tube MN7 is connected with VDD1 through a resistor, and the drain electrode of the MOS tube MN7 is also connected with the common end of the grid electrode of the MOS tube MP7 and the grid electrode of the MOS tube MN 8;

the gate of the MOS transistor MP7 is connected with the gate of the MOS transistor MN8, the source of the MOS transistor MP7 is connected with VDD1, the drain of the MOS transistor MP7 is connected with the drain of the MOS transistor MN8, and the source of the MOS transistor MN8 is grounded; the drain electrode of the MOS transistor MP7 and the common end of the drain electrode of the MOS transistor MN8 are connected with a first pull-down circuit.

Further, the third pull-down circuit is implemented in a resistor or MOS transistor manner.

Further, the voltage value relationship of each power supply system is as follows: VDDN < VDD (N-1) < … … < VDD2 < VDD 1.

In a second aspect, the invention also provides a method for managing a system with multiple power supplies in a chip, which is applied to the management circuit of the system with multiple power supplies in the chip and comprises three stages before power-on, during power-on and during power-off;

in a pre-power-on stage, the method comprises:

when the external reset signal is in a steady state or an unsteady state, the voltage of the external reset signal is fixed at a low potential of 0V through a third pull-down circuit, and at the moment, the booster circuit does not work;

the first pull-down circuit is connected in front of the VDD1 delay circuit, the second pull-down circuit is connected after the VDD1 delay circuit is combined, the voltage of nodes in front of and behind the VDD1 delay circuit is fixed at a low potential, and therefore the reset signal is prevented from false operation;

in the power-on process, each power system realizes the freedom of the power-on sequence; the method comprises the following steps:

after the external reset signal is powered on, a reset signal 1 is obtained, and after the delay time T1, the reset signal 1 is raised;

after the rising reset signal 1 is electrified, a reset signal 2 is obtained, and after the delay time T2, the reset signal 2 rises;

……

after the boosted reset signal N-1 is electrified, a reset signal N is obtained, and after the delay time TN, the reset signal N is boosted;

in the power-down period, the method comprises the following steps:

after the first power supply system VDD1 is powered off, the voltage of the delay circuit is reduced to a low potential, the output reset signal becomes a low potential, and the reset signal 1 immediately enters a reset state;

after the second power system VDD2 is powered down, the reset signal 2 enters the reset state immediately;

……

after the power failure of the power supply system VDD (N-1) of the N-1 th, the reset signal N-1 immediately enters a reset state;

after the power down of the Nth power supply system VDDN, the reset signal N immediately enters a reset state.

Compared with the prior art, the invention has the following advantages and beneficial effects:

1. when the external reset signal is in an unsteady state, before the voltage is electrified, the voltage of the external reset signal is fixed at a potential by adopting a third pull-down circuit, and the booster circuit does not work; meanwhile, the node voltages before and after the delay circuit of the VDD1 are fixed to low potential by the first pull-down circuit and the second pull-down circuit, so that the reset signal is prevented from misoperation in the voltage electrifying process.

2. The delay circuit can sequentially remove the reset state of the chip when the power is on and timely reset when the power is off, so that the freedom of the power-on sequence of a multi-power-supply system outside the chip is realized; and a delay circuit is introduced to realize accurate control of the delay time of each reset signal after the power supply is powered on.

3. The invention forms positive feedback by introducing a threshold voltage detection circuit, so that signals are enhanced, and chip misoperation caused by burrs is eliminated.

4. Before the external reset signal is not changed and VDD is not electrified, because of the action of the pull-down circuit, the node potential behind the booster circuit is fixed to the low potential, and each reset signal is also fixed to the low potential, so that misoperation cannot occur. In the power-on process of each power supply, some unnecessary burrs may occur, and because a threshold detection circuit is introduced, the influence of the burrs can be eliminated, and the misoperation of a chip in the power-on process is avoided. After the power-on of each voltage is completed, the external reset signal goes high, and the reset state is released after the delay time T1 of the reset signal 1; after the reset signal 1 rises, the reset signal 2 releases the reset state after the delay time T2; after the reset signal 2 rises, the reset signal 3 releases the reset state after the delay time T3, and the reset signals of the chip are all released and enter the normal operating state. During the power-down process of VDD1/VDD2/VDD3, because the power voltage of the delay circuit with threshold voltage detection drops to low potential, the output reset signal immediately enters a reset state to protect the internal circuit of the chip following the change of the power voltage to low potential.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a management circuit diagram of a system with multiple power supplies in a chip according to embodiment 1 of the present invention;

FIG. 2 is a delay circuit with threshold voltage detection according to embodiment 1 of the present invention;

fig. 3 is a timing diagram of a management circuit of a system with multiple power supplies in a chip according to embodiment 1 of the present invention;

FIG. 4 is a schematic diagram illustrating the principle of the glitch phenomenon;

fig. 5 is a schematic diagram of the threshold voltage detection circuit according to the present invention for eliminating glitches.

Detailed Description

Hereinafter, the term "comprising" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

In various embodiments of the invention, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B, or may include both a and B.

Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.

It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.

The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Example 1

As shown in fig. 1 to 5, a multi-power system management circuit in a chip according to the present invention, as shown in fig. 1, the multi-power system management circuit provided in this embodiment includes a boost circuit, a first pull-down circuit, and three delay circuits, where the three delay circuits include a first delay circuit, a second delay circuit, and a third delay circuit;

one end of the booster circuit is connected with an external reset signal, the other end of the booster circuit is connected with a first pull-down circuit, the first pull-down circuit is connected with the input end of a first delay circuit, and the output end of the first delay circuit outputs a reset signal 1; the output end of the first delay circuit is also connected with a second delay circuit, and the output end of the second delay circuit outputs a reset signal 2; the output end of the third delay circuit outputs a reset signal 3; each reset signal is connected to each functional unit in the chip; the boosting circuit is connected to a first power system VDD1, the first delay circuit is connected to a first power system VDD1, the second delay circuit is connected to a second power system VDD2, and the third delay circuit is connected to an Nth power system VDD 3;

To further illustrate the present embodiment, each delay circuit employs a delay circuit with threshold voltage detection, which includes a first inverter, an RC circuit, a threshold voltage detection circuit, a fourth pull-down circuit, and a second inverter, as shown in fig. 2;

the first phase inverter is connected with an RC circuit, the RC circuit is connected with a threshold voltage detection circuit, the threshold voltage detection circuit is connected with a fourth pull-down circuit, the fourth pull-down circuit is connected with a second phase inverter, and a corresponding reset signal is output after passing through the second phase inverter; the output end of the first inverter is marked as point A, and the output end of the RC circuit is marked as point B;

the invention sets a threshold voltage detection circuit to eliminate false operation of the chip caused by the burr phenomenon. The operating principle of the threshold voltage detection circuit for eliminating the influence of the burrs is as follows:

as shown in fig. 4, when the reset signal enters the delay circuit, a node B may introduce a glitch for some reason, which may cause an abnormality in signals at the point C and the point D, and finally cause a malfunction of the chip (causing a reset to cause the chip to be inoperative).

When the signal at point C is inverted during the rising of the voltage at node B, the voltage at point B is the threshold voltage Vth. The voltage at point B undergoes a process of gradually rising to a voltage maximum and then gradually falling again, so that point B will reach the threshold voltage Vth twice. Under the normal condition, in the time period of reaching the threshold voltage Vth twice, the voltage of the point B is higher than the Vth, and the chip works normally; when the burr phenomenon occurs at the point B, the voltage detected at the point B is smaller than the threshold voltage Vth in the time period, and as a result, signals at the point C and the point D are abnormal, so that the chip generates misoperation.

In view of the above problems, the present invention designs a threshold voltage detection circuit to solve the above problems. When the threshold voltage detection circuit is adopted, the voltage of the point B when the point C signal is inverted is set to be Vthr (margin is Vthr-Vth) according to requirements, when the point B signal generates a burr phenomenon due to some reason, the voltage of the point B is lower than the Vth in a certain period of time, the chip still works normally, and the probability of generating misoperation is reduced.

The working principle of the threshold voltage detection circuit is as follows: when the level of the node B is changed from low to high, the MOS tubes MN2, MN3 and MN4 are conducted, positive feedback is formed by a loop from a point C, the MOS tube MP5 and a loop from the MOS tube MN4 to the point C, impedance changes (the MOS tubes MN3 and MN4 are connected in parallel and then connected in series with the MOS tube MN 2), and the threshold voltage is increased to a first threshold Vthr;

Specifically, fig. 5 is a schematic diagram of the threshold voltage detection circuit of the present invention for eliminating glitches.

To further illustrate the present embodiment, the RC circuit includes a resistor R and a capacitor C, one end of the resistor R is connected to the output end of the first inverter, the other end of the resistor R is connected to the capacitor C, and the capacitor C is grounded;

The first inverter is used for improving the driving capability of a subsequent delay circuit and shortening the rising time or the falling time of the voltage at the point A; similarly, the second inverter functions to shorten the rise time or fall time of the voltage at the OUT point.

To further explain the present embodiment, the first pull-down circuit and the fourth pull-down circuit are both implemented by using resistors or MOS transistors.

To further describe this embodiment, the output end of each of the delay circuits is connected to a second pull-down circuit, and each of the delay circuits outputs a corresponding reset signal after passing through a corresponding second pull-down circuit.

Wherein, pull-down circuit adopts resistance or MOS pipe mode to realize, and pull-down circuit's effect is: before power-on, the first pull-down circuit and the second pull-down circuit fix the node voltages before and after the delay circuit at low potential, so that the reset signal does not generate misoperation in the power-on process. To further illustrate the present embodiment, the voltage boost circuit includes a third pull-down circuit, an N-channel MOS transistor MN7, a P-channel MOS transistor MP7, and an N-channel MOS transistor MN 8;

To further illustrate the present embodiment, the third pull-down circuit is implemented in a resistor or MOS transistor manner.

Before power-on, when the external reset signal is in a stable state or an unstable state, the third pull-down circuit fixes the voltage of the external reset signal at a low potential, and the booster circuit does not work. An inverter is composed of VDD1, a MOS tube MP7 and a MOS tube MN8, so that on one hand, the driving capability of the node voltage after the booster circuit and before the first pull-down circuit can be improved; on the other hand, the inverter blocks the front resistor and the rear resistor, and ensures that the voltage value is stabilized at VDD1 after an external reset signal passes through the booster circuit.

To further explain the present embodiment, the voltage value relationship of each power supply system: VDD3 < VDD2 < VDD 1.

When the voltage of the booster circuit is greater than or equal to the voltage of the first delay circuit, the chip can normally work, otherwise, through current is generated, and large current is generated. The reason is that when the voltage of the external reset signal is different from VDD1 and is greater than Vth, both the P-transistor and the N-transistor are turned on, resulting in excessive current. In order to avoid the large current phenomenon, preferably, the voltage of the boosting circuit is accessed to VDD1, the voltage of the external reset signal passing through the boosting circuit is kept at VDD1, no voltage difference exists between the voltage and the accessed voltage of the first delay circuit, and the chip works normally.

When the external reset signal is in an unsteady state, the voltage of the external reset signal is fixed at a low potential (at the moment, the voltage is in a stable state) through the first pull-down circuit, and the reset signal is ensured not to generate misoperation in the voltage electrifying process; after power-on is completed, the reset state of the chip interior is sequentially released; and entering a reset state in time when power is down. According to the invention, by introducing the delay circuit, the delay time of each reset signal after the power supply is powered on can be accurately controlled; the invention prevents the false operation of the reset signal caused by the power supply jitter in the power-on process of the power supply by introducing the threshold voltage detection circuit.

Specifically, the method comprises the following steps: before the external reset signal is not changed and VDD is not powered on, because of the action of the first pull-down circuit, the potential of a node behind the booster circuit is fixed to a low potential, and each reset signal is also fixed to the low potential, so that malfunction cannot occur.

In the power-on process of each power supply system, some unnecessary burrs may occur, and due to the introduction of the threshold voltage detection circuit, the influence of the burrs can be eliminated, and the malfunction of a chip in the power-on process is avoided.

After the power-on of each voltage is completed, the external reset signal goes high, and the reset state is released after the delay time T1 of the reset signal 1; after the reset signal 1 rises, the reset signal 2 releases the reset state after the delay time T2; after the reset signal 2 rises, the reset signal 3 releases the reset state after the delay time T3, so that the functional units in the chip are sequentially powered on according to the sequence of receiving the reset signals 1, 2 and 3.

During the power-down process of VDD1/VDD2/VDD3, because the power voltage of the delay circuit with threshold voltage detection drops to low potential, the output reset signal immediately enters a reset state to protect the internal circuit of the chip following the change of the power voltage to low potential.

Example 2

The difference between the embodiment and the embodiment 1 is that the embodiment provides a method for managing a system with multiple power supplies in a chip, which is applied to a management circuit of the system with multiple power supplies in the chip in the embodiment 1, and the method comprises three stages before power-on, during power-on and during power-off;

in a pre-power-on stage, the method comprises:

when the external reset signal is in a stable state or an unstable state, the voltage of the external reset signal is fixed at a low potential of 0V through a third pull-down circuit, and the booster circuit does not work at the moment;

the pull-down circuit can be realized in various ways such as a resistor structure and an MOS tube.

The pull-down circuit functions as: the voltage of an external reset signal is fixed at a low potential through the pull-down circuit, so that the chip is prevented from generating misoperation (namely, the chip is prevented from working abnormally).

In the power-on process, each power system realizes the freedom of power-on sequence, and the method comprises the following steps:

after the rising reset signal 3 is electrified, the reset signal 3 is obtained, and after the delay time T3, the reset signal 3 rises;

the function of the delay circuit is: the time at which the reset signal rises (i.e., the time at which the reset state is released) is controlled. The pull-down circuit is arranged after the delay circuit, and the advantage is that the reset signal is fixed to be low potential before the reset signal is not started.

In the power-down period, the method comprises the following steps:

the reset bit number 3 enters the reset state immediately after the third power system VDD3 is powered down.

The working principle is as follows: during the power-on process of VDD1/VDD2/VDD3 (wherein VDD3 < VDD2 < VDD1), the power-on sequence of the three voltage systems is free. The node voltage before the delay circuit with threshold voltage detection of VDD1 before voltage power-on is fixed to low potential by the pull-down circuit, and meanwhile, each output reset signal is also fixed to low potential through the pull-down circuit, so that each reset signal is prevented from malfunction in the voltage power-on process.

When the power-on of each power supply system is completed, after the external reset signal goes high, the reset signal 1 releases the reset state after the delay time T1 elapses; after the reset signal 1 goes high, the reset signal 2 releases the reset state after the delay time T2 elapses; after the reset signal 2 goes high, the reset signal 3 releases the reset state after the delay time T3 elapses.

During the power-down process of VDD1/VDD2/VDD3, after the power-down of VDD1, the reset signal 1 enters the reset state directly without delay; after VDD2 is powered down, reset signal 2 goes to the reset state directly without delay; after VDD3 is powered down, reset signal 3 goes to the reset state directly without delay;

the invention achieves the following beneficial effects:

1. when the external reset signal is in an unsteady state, before voltage power-on, node voltages before and after the delay circuit of the VDD1 are fixed to low potential by the first pull-down circuit and the second pull-down circuit, so that the reset signal is prevented from false operation in the voltage power-on process.

2. The delay circuit (the reset state of the chip is removed in sequence when the chip is powered on, and the delay is not caused when the chip is powered off), so that the power-on sequence freedom of a multi-power-supply system outside the chip is realized. And a delay circuit is introduced to realize accurate control of the delay time of each reset signal after the power supply is powered on.

3. By introducing a threshold voltage detection circuit, positive feedback is formed, so that signals are enhanced, and chip misoperation caused by burrs is eliminated.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A multi-power system management circuit in a chip is characterized by comprising a boosting circuit, a first pull-down circuit and a plurality of delay circuits, wherein the plurality of delay circuits comprise a first delay circuit, a second delay circuit, … …, an N-1 th delay circuit and an Nth delay circuit;

one end of the booster circuit is connected with an external reset signal, the other end of the booster circuit is connected with a first pull-down circuit, the first pull-down circuit is connected with the input end of a first delay circuit, and the output end of the first delay circuit outputs a reset signal 1; the output end of the first delay circuit is also connected with a second delay circuit, and the output end of the second delay circuit outputs a reset signal 2; … … the output end of the N-1 th delay circuit is also connected with the Nth delay circuit, the output end of the Nth delay circuit outputs the reset signal N; each reset signal is connected to each functional unit in the chip;

2. The on-chip multi-power-supply system management circuit of claim 1, wherein each delay circuit employs a delay circuit with threshold voltage detection, and the delay circuit with threshold voltage detection comprises a first inverter, an RC circuit, a threshold voltage detection circuit, a fourth pull-down circuit and a second inverter;

when the threshold voltage detection circuit works: when the level of the node B is changed from low to high, the MOS tubes MN2, MN3 and MN4 are conducted, a loop from a point C to a point C, the MOS tube MP5 and the MOS tube MN4 to the point C form positive feedback, impedance changes, and the threshold voltage is increased to a first threshold Vthr;

when the level of the node B changes from high to low, the MOS transistors MP2, MP3, and MP4 are turned on, and a positive feedback is formed by the loop from the point C, MN5, and MP4 to the point C, so that the impedance changes, and the threshold voltage decreases to the second threshold Vthd.

3. The on-chip multi-power-supply system management circuit as claimed in claim 2, wherein the RC circuit comprises a resistor R and a capacitor C, one end of the resistor R is connected to the output end of the first inverter, the other end of the resistor R is connected to the capacitor C, and the capacitor C is grounded;

4. The on-chip multi-power system management circuit of claim 2, wherein the first pull-down circuit and the fourth pull-down circuit are implemented by using resistors or MOS transistors.

5. The on-chip multi-power-supply system management circuit of claim 1, wherein an output end of each delay circuit is connected with a second pull-down circuit, and each delay circuit outputs a corresponding reset signal after passing through the corresponding second pull-down circuit;

the second pull-down circuit is realized by adopting a resistor or MOS mode.

6. The on-chip multi-power system management circuit of claim 1, wherein the boost circuit comprises a third pull-down circuit, an N-channel MOS transistor MN7, a P-channel MOS transistor MP7, an N-channel MOS transistor MN 8;

7. The on-chip multi-power system management circuit according to claim 6, wherein the third pull-down circuit is implemented in a resistor or MOS (metal oxide semiconductor) transistor manner.

8. The on-chip multi-power-supply system management circuit according to claim 1, wherein the voltage value relationship of each power supply system is as follows: VDDN < VDD (N-1) < … … < VDD2 < VDD 1.

9. A method for managing a system with multiple power supplies in a chip is characterized in that the method is applied to a circuit for managing the system with multiple power supplies in the chip as claimed in any one of claims 1 to 8, and the method comprises three stages before power-on, during power-on and during power-off;

in a pre-power-on stage, the method comprises:

the first pull-down circuit is connected in front of the VDD1 delay circuit, and the second pull-down circuit is connected behind the VDD1 delay circuit, so that the voltage of nodes in front of and behind the VDD1 delay circuit is fixed at a low potential;

……

in the power-down period, the method comprises the following steps:

……