Disclosure of Invention
In order to solve the above-mentioned problems, the present invention provides a light emitting diode module with a sleep mode to overcome the problems of the prior art. Therefore, the light emitting diode module with sleep mode of the invention comprises: and the detection circuit receives the light-emitting driving signal through the power line. The driving circuit receives the light-emitting driving signal and is coupled with the detecting circuit, and the driving circuit comprises: the control unit is coupled with the detection circuit. And at least one light emitting diode coupled to the control unit. The control unit obtains and stores a lighting command according to the lighting driving signal, and controls the lighting behavior of the light emitting diode according to the lighting command; the detection circuit provides a first detection signal and a second detection signal, when the driving circuit knows that the luminous driving signal falls to be smaller than a first threshold value through the first detection signal provided by the detection circuit, the driving circuit performs signal identification of the luminous driving signal, and when the signal identification of the luminous driving signal is completed, the driving circuit enters a sleep mode from a working mode; when the driving circuit knows that the light-emitting driving signal falls to be smaller than a second threshold value through the second detection signal, the driving circuit reduces the discharge speed of the light-emitting driving signal.
In an embodiment, when the driving circuit detects that the light-emitting driving signal rises to be greater than or equal to the second threshold value through the second detection signal, the driving circuit returns to the working mode from the sleep mode.
In one embodiment, the detection circuit includes: and a voltage dividing circuit for receiving the light emission driving signal. The first comparator receives the first reference voltage and is coupled to the voltage dividing circuit. And the second comparator receives the second reference voltage and is coupled with the voltage dividing circuit. The first comparator provides a first detection signal according to the first reference voltage and the partial voltage value of the corresponding light-emitting driving signal, and the second comparator provides a second detection signal according to the second reference voltage and the partial voltage value of the corresponding light-emitting driving signal.
In one embodiment, the detection circuit includes: and one end of the first resistor receives the light-emitting driving signal, and the other end of the first resistor receives the first reference voltage. The first switch comprises an input end, an output end and a control end, wherein the input end is connected with a light driving signal receiving and transmitting device, and the control end is coupled with the other end of the first resistor. And the voltage dividing circuit is coupled with the output end of the first switch and the control unit. The voltage dividing circuit divides the voltage of the output end of the first switch to provide a first detection signal and a second detection signal.
In one embodiment, the driving circuit further includes: and the oscillator is used for receiving the light-emitting driving signal and is coupled with the control unit. In the working mode, the oscillator provides a clock pulse signal to the control unit according to the light-emitting driving signal; in the sleep mode, the sleep signal provided by the control unit turns off the oscillator, so that the oscillator does not provide the clock signal to the control unit, and simultaneously, the analog circuit is also turned off.
In one embodiment, an oscillator includes: the first inverter comprises an input end, an output end and a power supply end, wherein the input end is coupled with one end of the second resistor and one end of the first capacitor, the output end is coupled with the other end of the second resistor, and the power supply end is connected with the optical drive signal and the sleep signal. The second inverter comprises an input end, an output end and a power supply end, wherein the input end is coupled with the other ends of the first inverter and the second resistor, the output end is coupled with the other end of the first capacitor and the control unit, and the power supply end receives and transmits the optical drive signal and the sleep signal.
In one embodiment, the driving circuit includes: the latch circuit receives the light-emitting driving signal and the first detection signal. When the latch circuit knows that the time of the light-emitting driving signal smaller than the first threshold value is longer than or equal to the duration time according to the first detection signal, the latch signal provided by the latch circuit enables the control unit to store the identified light-emitting driving signal as a light-emitting command.
In one embodiment, the control unit includes: the logic circuit is coupled with the detection circuit. And a register coupled to the logic circuit. The latch circuit is composed of logic gates and is integrated in the logic circuit; when the time that the light-emitting driving signal is smaller than the first threshold value is longer than or equal to the duration time, the latch signal provided by the logic gate enables the logic circuit to inform the register to store the identified light-emitting driving signal as a light-emitting command.
In one embodiment, the latch circuit includes: the second switch comprises an input end, an output end and a control end, wherein the output end is coupled with one end of the power line and one end of the second capacitor, the input end is coupled with the other end of the second capacitor, one end of the third resistor and the control unit, and the control end receives the first detection signal. The third switch comprises an input end, an output end and a control end, wherein the input end is coupled with the other end of the second resistor, the output end is coupled with the grounding point, and the control end receives the first detection signal.
In one embodiment, the latch circuit includes: the second switch comprises an input end, an output end and a control end, wherein the output end is coupled with the power line, the input end is coupled with one end of the third resistor, and the control end receives the first detection signal. The third switch comprises an input end, an output end and a control end, wherein the input end is coupled with the other end of the second resistor, one end of the second capacitor and the control unit, the output end is coupled with the other end of the second capacitor and the grounding point, and the control end receives the first detection signal.
In one embodiment, the driving circuit includes: the discharging circuit receives the second detection signal and is coupled to the power line. When the discharge circuit knows that the light-emitting driving signal is smaller than the second threshold value through the second detection signal, the discharge circuit reduces the discharge speed of the light-emitting driving signal.
In one embodiment, the discharge circuit includes: the discharging switch comprises an input end, an output end and a control end, wherein the input end is coupled with the power line, the output end is coupled with the grounding point, and the control end receives a second detection signal.
In order to solve the above-mentioned problems, the present invention provides a light emitting diode light string with a sleep mode to overcome the problems of the prior art. Therefore, the LED light string with the sleep mode comprises the following components: and the power line receives the direct-current working voltage. And a control module coupled to the power line and including: and the power switch is coupled with the power line. And a controller coupled to the power switch. The at least one LED module is coupled with the control module through a power line and receives the luminous driving signal and the direct-current working voltage transmitted by the control module through the power line; when the controller controls the power switch to be turned on, the direct-current working voltage forms a power supply loop for supplying power to at least one LED module through a power supply line; when the controller is to generate a light-emitting driving signal belonging to at least one light-emitting diode module, the controller continuously switches on and off the power switch according to the light-emitting command, so that the DC working voltage of the power line forms a plurality of pulses to be combined into the light-emitting driving signal, and the light-emitting driving signal is transmitted to the light-emitting diode module through the power line.
The main purpose and effect of the present invention is that when the driving circuit is in the sleep mode, the driving circuit does not work (i.e. the oscillator and the circuit and the analog circuit controlled by the clock signal provided by the oscillator are mainly turned off to turn off the main power consumption components of the driving circuit), so as to achieve the effect of saving the power consumption of the light emitting diode module.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to limit the invention, so that those skilled in the art may better understand the invention and practice it.
The technical content and detailed description of the present invention are as follows in conjunction with the drawings:
fig. 1A is a circuit block diagram of a light emitting diode string with sleep mode according to a first embodiment of the present invention. The LED light string 100 includes a power line 10, a control module 20, at least one LED module 30-1 to 30-n, and a rectifier 40, wherein the rectifier 40 is coupled to the power line 10 and receives an input power Vac to rectify the input power Vac into a DC operating voltage Vdc. The control module 20 receives the DC operating voltage Vdc and controls the light emitting behavior of at least one LED module 30-1 to 30-n. Among them, the light emitting behavior is such as, but not limited to, a color change, a bright-dark (dark) manner, a bright-dark frequency …, and the like. The control module 20 is coupled to the power line 10, and is coupled to the LED modules 30-1 to 30-n through the power line 10. The LED modules 30-1 to 30-n are coupled in series or parallel (in this embodiment, the LED modules are illustrated in series), and receive the light-emitting driving signal Sd and the DC operating voltage Vdc transmitted by the control module 20 through the power line 10. The dc operating voltage Vdc may be obtained by adding a dc converter (not shown) to the front stage, or the dc operating voltage Vdc may be obtained by installing a battery in the led string 100.
Specifically, the control module 20 includes a power switch SW and a controller 202, an input terminal X and an output terminal Y of the power switch SW are coupled to the power line 10, and a control terminal Z of the power switch SW is coupled to the controller 202. The controller 202 receives the dc operating voltage Vdc through the power line 10 and provides a switching signal Ssw to control the power switch SW to be turned on and off. When the controller 202 controls the power switch SW to be turned on, the DC operating voltage Vdc forms a power supply loop for supplying power to the LED modules 30-1 to 30-n through the power line 10. When the controller 202 is about to generate the light-emitting driving signal Sd of one of the led modules 30-1 to 30-n (assuming the first led module) according to the light-emitting command of the led module 30-1, the controller continuously switches the power switch SW on and off, so that the dc operating voltage Vdc on the power line 10 forms a plurality of pulses to combine into the light-emitting driving signal Sd of the led module 30-1, and the light-emitting driving signal Sd is transmitted to the led module 30-1 through the power line 10.
The controller 202 may receive an external lighting command Clo from outside in addition to the built-in lighting command by a wired (wireless) or wireless (wireless) manner, so that the controller 202 may control the on/off of the power switch SW according to the lighting command or the content of the external lighting command Clo to generate a lighting driving signal Sd for lighting control of the LED modules 30-1 to 30-n by the lighting driving signal Sd. For example, the user can send the external lighting command Clo to the controller 202 in a wired manner by operating the computer, so that the controller 202 performs lighting control according to the external lighting command Clo. Alternatively, the user may wirelessly transmit the external lighting command Clo to the controller 202 by operating the mobile phone or the wearable device, so that the controller 202 performs lighting control according to the external lighting command Clo. The present invention is not limited by the manner in which the external illumination command Clo is transmitted and the user device that operates.
Taking the controller 202 as an example, to correspondingly transmit the light-emitting driving signal Sd belonging to the led module 30-1 according to the light-emitting command belonging to the led module 30-1, the controller 202 can generate the notification signal of the command transmission by controlling the switching of the power switch SW. When the LED modules 30-1 to 30-n receive the notification signal, the command receiving stage is performed. Then, the controller 202 converts the light emitting command belonging to the light emitting diode module 30-1 into the light emitting driving signal Sd by controlling the on and off of the power switch SW. The pulse wave of the light-emitting driving signal Sd can be formed by adding address data in the form of 0 and 1 and the brightness 11 and the color 10 of the LED lamp. The light-emitting driving signal Sd includes, for example and without limitation, 10 pulses, and the address data corresponds to the address of the first LED module 30-1. When the LED modules 30-1 to 30-n receive the address data, the LED module 30-1 knows that the sequentially transmitted light-emitting driving signal Sd belongs to the self-light-emitting driving signal Sd, so as to perform signal identification on the light-emitting driving signal Sd. After the 9 pulses are identified, the controller 202 generates a notification signal (i.e. the last pulse) for completing the command transmission by controlling the switching of the power switch SW, and the led module 30-1 generates a latch signal according to the notification signal to store the light-emitting command corresponding to the 9 pulses, and generates a light-emitting action according to the stored light-emitting command. It should be noted that the led module 30-1 has various control modes, but the spirit is substantially the same as that of the control mode described above, and the control mode of the led module 30-2 to 30-n is also the same as that of the led module 30-1, and will not be described herein.
Fig. 1B is a circuit block diagram of a second embodiment of a light emitting diode light string with sleep mode according to the present invention, and fig. 1A is combined. The difference between the LED light string 100 'of the present embodiment and the LED light string 100 of FIG. 1A is that the LED light string 100' does not include the rectifier 40, and the LED modules 30-1 to 30-n are coupled in parallel. The control module 20 of the LED string 100 receives the DC operating voltage Vdc provided from the outside and controls the LED modules 30-1 to 30-n to emit light. It should be noted that, in an embodiment of the present invention, the coupling relationship and the control manner of the elements of the led string 100' are the same as those of fig. 1A, and are not described herein.
Fig. 1C is a schematic waveform diagram of a light-emitting driving signal according to the present invention, and fig. 1A to 1B are combined. The light-emitting driving signal Sd of the present embodiment is illustrated by pulses of 10 periods, and when the controller 202 controls the power switch SW to be turned on, the dc operating voltage Vdc forms a power supply loop for supplying power to the led modules 30-1 to 30-n through the power line 10. When the controller 202 wants to generate the light-emitting driving signal Sd, the controller continuously switches on and off the power switch SW according to the light-emitting command, so that the dc operating voltage Vdc on the power line 10 is switched to form the light-emitting driving signal Sd composed of 10 periods of pulse Pu, and the light-emitting driving signal Sd is transmitted to the light-emitting diode module 30-1 through the power line 10. When the last pulse Pu is at the low level for a longer time, the led module 30-1 detects the pulse Pu as a notification signal for completing the command transmission. I.e. the last pulse Pu is at the low level longer than the duration Th of the first 9 pulses at the low level. At this time, the LED modules 30-1 to 30-n generate latch signals according to the notification signals to store the light emitting commands corresponding to the 9 pulses Pu, and generate light emitting behaviors according to the stored light emitting commands.
Fig. 2A is a circuit block diagram of an led module with a sleep mode according to the present invention, fig. 2B is a pulse waveform diagram of an led driving signal according to the present invention, and fig. 1A to 1B are combined, and fig. 2A and 2B are repeated. Each of the led modules 30-1 to 30-n includes a detection circuit 302, a driving circuit 304 and at least one led 306 (three leds 306 are taken as an illustrative example in this embodiment), and the driving circuit 304 is coupled to the detection circuit 302 and the leds 306. The detection circuit 302 receives the dc operating voltage Vdc or the light-emitting driving signal Sd through the power line 10, and provides the first detection signal S1 and the second detection signal S2 to the driving circuit 304 according to the light-emitting driving signal Sd. The driving circuit 304 receives the dc operating voltage Vdc or the light emitting driving signal Sd through the power line 10, and the driving circuit 304 operates in the operating mode when the driving circuit 304 receives the dc operating voltage Vdc. At this time, the control unit 304A in the driving circuit 304 controls the light emitting behavior of the light emitting diode 306 according to the light emitting command Cl obtained by the light emitting driving signal Sd previously supplied from the controller 202. In an embodiment of the present invention, the detection circuit 302 and the driving circuit 304 in the LED modules 30-1 to 30-n can be controllers packaged together, but not limited thereto. In other words, the whole LED modules 30-1 to 30-n can be packaged together according to actual requirements, or the components inside the LED modules 30-1 to 30-n can be independently arranged.
When the driving circuit 304 receives the light-emitting driving signal Sd, the driving circuit 304 adjusts the operation mode according to the first detection signal S1 and the second detection signal S2. Specifically, as shown in fig. 2B, the power switch SW is turned off at time t0, so that the light emission drive signal Sd starts to fall. When the driving circuit 304 knows that the light-emitting driving signal Sd falls below the first threshold V1 (time t 1) through the first detection signal S1, the driving circuit 304 performs signal identification of the light-emitting driving signal Sd. At this time, the driving circuit 304 still operates in the operation mode, and the signal identification of the light-emitting driving signal Sd is completed at time t 2. After the light-emitting driving signal Sd is completed (after time t 2), the driving circuit 304 enters the sleep mode from the operation mode. When the driving circuit 304 knows that the light-emitting driving signal Sd falls below the second threshold V2 (time t 3) through the second detection signal S2, the driving circuit 304 decreases the discharging speed of the light-emitting driving signal Sd (i.e. the slope of the voltage drop changes). Finally, at time t4, the voltage of the pulse wave rises from less than the second threshold V2 to greater than the first threshold V1, so that the driving circuit 304 returns from the sleep mode to the operation mode. At this time, the driving circuit 304 wakes up to enter the operation mode. Therefore, it can be seen that the driving circuit 304 is in the sleep mode when the voltage of the pulse wave rises from less than the second threshold V2 to greater than the first threshold V1 after the light-emitting driving signal Sd is identified, and the driving circuit 304 is in the operation mode.
Further, as shown in FIG. 2A, the driving circuit 304 includes an oscillator 3042, a latch circuit 3044, a discharging circuit 3046 and a control unit 304A, and the control unit 304A includes a logic circuit 304A-1, a register 304A-2 and a driver 304A-3. When the driving circuit 304 is in the operation mode, the above-mentioned elements are all operated by receiving the dc operation voltage Vdc or the light-emitting driving signal Sd. Since the clock signal CLK generated by the oscillator 3042 is closely related to the operation of the control unit 304A, and the oscillator 3042 is a main power consumption element when the driving circuit 304 is in the operation mode, the main purpose and effect of the present invention is that the driving circuit 304 does not operate (i.e. the oscillator 3042 is turned off mainly to turn off the main power consumption element of the driving circuit 304) and the analog circuit when the driving circuit 304 is in the sleep mode. And due to the turn-off of the oscillator 3042, the circuits (such as but not limited to the driver 304A-3, the logic circuit 304A-1 and part of the circuits of the register 304A-2) operated by the clock signal CLK in the control unit 304A are turned off at the same time, so as to save the power consumption of the LED modules 30-1-30-n. It should be noted that, since the latch circuit 3044 does not use the clock signal CLK, the latch circuit 3044 can still provide the latch signal Sl according to the first detection signal S1 in the sleep mode when the oscillator 3042 is turned off. In addition, the logic circuit 304A-1 is a digital passive device, so that even when the driving circuit 304 is in the sleep mode, the passive logic circuit 304A-1 can wake up all devices in the driving circuit 304 through the output of the signal as long as the voltage of the light-emitting driving signal Sd pulse rises from less than the second threshold V2 to greater than the first threshold V1 so that the second detection signal S2 changes.
Referring back to fig. 2A, the control unit 304A receives the dc operating voltage Vdc or the light-emitting driving signal Sd as a power source required for operation. The logic circuit 304A-1 is coupled to the detection circuit 302, and performs signal identification of the light-emitting driving signal Sd according to the first detection signal S1, and provides the sleep signal Ss to the oscillator 3042 according to the second detection signal S2. The register 304A-2 is coupled to the logic circuit 304A-1, and when the logic circuit 304A-1 receives the latch signal Sl, the logic circuit 304A-1 provides the recognized light-emitting driving signal Sde to the register 304A-2, so that the register 304A-2 stores the light-emitting driving signal as the light-emitting command Cl. The driver 304A-3 is coupled to the register 304A-2 and the LED 306, and the register 304A-2 controls the driver 304A-3 to drive the LED 306 according to the light-emitting command Cl, so that the LED 306 generates a light-emitting action. It should be noted that the control unit 304A of the present invention provides the plurality of pulses in the light-emitting driving signal Sd to the register 304A-2 for storage at a time, so that the register 304A-2 can store the complete light-emitting command Cl at a time, instead of receiving the pulse once, the light-emitting behavior of the light-emitting diode 306 is adjusted according to the single pulse, so as to avoid the situation that the light-emitting command Cl is easy to be wrong and the light-emitting diode 306 generates wrong light-emitting behavior.
The oscillator 3042 receives the DC operating voltage Vdc or the light-emitting driving signal Sd, and is coupled to the control unit 304A and the logic circuit 304A-1 in the control unit 304A. In the operation mode, the oscillator 3042 provides the clock signal CLK to the control unit 304A according to the dc operating voltage Vdc or the light-emitting driving signal Sd, so that a part of the devices (not shown) in the control unit 304A requiring the clock signal CLK operate according to the clock signal CLK. In the sleep mode, the logic circuit 304A-1 provides the sleep signal Ss according to the second detection signal S2 such that the oscillator 3042 is turned off and the clock signal CLK is not provided to the control unit 304A. Therefore, in the sleep mode, the oscillator 3042 with higher power consumption and the part of the devices operated by the clock signal CLK stop operating, so as to save the power consumption of the LED modules 30-1 to 30-n. When the sleep mode returns to the operation mode, the second detection signal S2 changes, so that the logic circuit 304A-1 adjusts the sleep signal Ss according to the change of the second detection signal S2, and wakes up the oscillator 3042 by the provided sleep signal Ss. It should be noted that, in an embodiment of the present invention, in addition to the oscillator 3042 being turned off, the logic circuit 304A-1 can also turn off other analog circuits (not shown) in the driving circuit 304 in the sleep mode according to the sleep signal Ss provided by the second detection signal S2, and then restart the other analog circuits (not shown) when the driving circuit returns to the operation mode from the sleep mode. For example, but not limited to, the sleep signal Ss may control the sleep or operation of a signal detection circuit, a protection circuit, etc. of the portion. Therefore, the power consumption of the LED modules 30-1 to 30-n can be further saved.
The latch circuit 3044 receives the DC operating voltage Vdc or the light-emitting driving signal Sd, and provides a latch signal Sl to the logic circuit 304A-1 according to the first detection signal S1. Specifically, the latch circuit 3044 controls the supplied latch signal Sl with the length of time. When the pulse width of the light-emitting driving signal Sd is too short, the latch signal Sl provided by the latch circuit 3044 causes the logic circuit 304A-1 not to provide the light-emitting command Cl to the register 304A-2. When the pulse width in the light emission drive signal Sd is sufficiently long, the time representing that the light emission drive signal Sd is smaller than the first threshold V1 is longer than or equal to the duration. At this time, the latch signal Sl provided by the latch circuit 3044 causes the logic circuit 304A-1 to inform the register 304A-2 to provide the recognized light-emitting driving signal Sde to the register 304A-2 for storing as the light-emitting command Cl according to the latch signal Sl.
The discharging circuit 3046 is coupled to the detecting circuit 302 and the power line 10, and the discharging circuit 3046 reduces the discharging speed of the light-emitting driving signal Sd when the light-emitting driving signal Sd is smaller than the second threshold V2 according to the second detecting signal S2. Specifically, since some control units 304A do not have the function of power-off memory. That is, after the dc operating voltage Vdc or the light-emitting driving signal Sd is too low, the data stored in the control unit 304A is cleared (e.g. but not limited to the light-emitting command Cl), so the voltage of the light-emitting driving signal Sd at the low level must be kept above the minimum operating voltage Vm (as shown in fig. 2B) to avoid the control unit 304A from being Reset (Reset) due to the too low voltage. The discharging circuit 3046 primarily minimizes the discharging speed of the light-emitting driving signal Sd as much as possible, so that the voltage value of the light-emitting driving signal Sd is not too fast reduced, and the time of the last pulse Pu at the low level (because the time of the last pulse Pu at the low level is longer) is more easily extended. The present invention utilizes the discharging circuit 3046 to reduce the discharging speed of the light-emitting driving signal Sd when the light-emitting driving signal Sd is smaller than the second threshold V2, so as to avoid the effect that the voltage value is lower than the minimum operating voltage Vm due to the too fast discharging of the light-emitting driving signal Sd.
The LED modules 30-1 to 30-n further include an analog circuit 3048, wherein the analog circuit 3048 receives the DC operating voltage Vdc or the light-emitting driving signal Sd as a power source and is coupled to the control unit 304A. The led modules 30-1 to 30-n are light strings with burning function, so each led module 30-1 to 30-n has digital and analog circuits for burning light emitting data and address data, such as a light emitting control unit for controlling light emission, an address signal processing unit for processing address signals, and an address burning unit for burning addresses (not shown). In the sleep mode, the control unit 304A turns off the oscillator 3042 and the analog circuit 3048 in addition to the sleep signal Ss, so as to save the power consumption of the LED modules 30-1 to 30-n.
The led modules 30-1 to 30-n further include an energy storage capacitor C coupled between the input end and the output end of the led modules 30-1 to 30-n, and configured to stabilize the voltage across the led modules 30-1 to 30-n (i.e., the input end and the output end) when the dc operating voltage Vdc or the light-emitting driving signal Sd is transmitted from the input end to the output end of the led modules 30-1 to 30-n (via the power line 10), so as to reduce the instability of the control error of the led modules 30-1 to 30-n caused by the voltage floating across the led modules 30-1 to 30-n. It should be noted that, in an embodiment of the present invention, the energy storage capacitor C is only used for stabilizing the voltage across the LED modules 30-1 to 30-n, and is not an essential element of the LED modules 30-1 to 30-n, and is therefore indicated by a dotted line.
Fig. 2C is a schematic diagram illustrating a logic circuit for enabling a sleep mode according to the present invention, and fig. 1A to 2B are combined. The logic circuit 304A-1 may enable the sleep mode of the driver circuit 304 by, for example and without limitation, a simple logic gate. As shown in fig. 2C, an input terminal of the AND gate AND receives a completion signal Se indicating that the signal of the optical driving signal Sd is recognized, AND whether the signal is recognized is obtained by the logic circuit 304A-1 according to the input of the first detection signal S1. The other input terminal of the AND gate receives the second detection signal S2, AND when the completion signal Se AND the second detection signal S2 are both 1, the AND gate provides the sleep signal Ss of 1 to the oscillator 3042, so that the oscillator 3042 is turned off. When one of the input terminals of the AND gate AND is not 1, the AND gate AND provides a sleep signal Ss of 0 to the oscillator 3042, so that the oscillator 3042 is awakened.
Fig. 3A is a circuit diagram of a first embodiment of the detection circuit according to the present invention, and fig. 1A to fig. 2B are combined. The detection circuit 302 includes a voltage dividing circuit 302A, a first comparator 302B, and a second comparator 302C, and the voltage dividing circuit includes voltage dividing resistors Ra, rb. The circuit connection is only for illustration, and the detection circuit 302 capable of providing the first detection signal S1 and the second detection signal S2 according to the variation of the light-emitting driving signal Sd is not limited to the present invention. One end of the voltage dividing resistor Ra receives the dc operating voltage Vdc or the light emitting driving signal Sd, the other end of the voltage dividing resistor Ra is coupled to one end of the voltage dividing resistor Rb, and the other end of the voltage dividing resistor Rb is coupled to the ground point. The first comparator 302B and the second comparator 302C respectively include a first input (+) and a second input (-) and an output O, and the first input (+) of the first comparator 302B and the second comparator 302C is coupled between the voltage dividing resistors Ra and Rb. The second input (-) of the first comparator 302B is coupled to the first reference voltage Vref1, and the second input (-) of the second comparator 302C is coupled to the second reference voltage Vref2. After the dc operating voltage Vdc or the light emission driving signal Sd is divided by the voltage dividing resistors Ra and Rb, a divided voltage value is generated at the node a between the voltage dividing resistors Ra and Rb. The first comparator 302B provides a first detection signal S1 at the output terminal O of the first comparator 302B according to the divided value of the first reference voltage Vref1 and the corresponding light-emitting driving signal Sd, and the second comparator 302C provides a second detection signal S2 at the output terminal O of the second comparator 302C according to the divided value of the second reference voltage Vref2 and the corresponding light-emitting driving signal Sd. Wherein, the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2.
When the voltage value of the light-emitting driving signal Sd is greater than the first reference voltage Vref1 and the second reference voltage Vref2, the first comparator 302B and the second comparator 302C are high-level outputs, so that the driving circuit 304 is in the working mode. When the voltage value of the light-emitting driving signal Sd is between the first reference voltage Vref1 and the second reference voltage Vref2, the first comparator 302B is a low level output, and the second comparator 302C is a high level output. At this time, the driving circuit 304 performs signal recognition of the light emission driving signal Sd. After the light-emitting driving signal Sd is identified (the voltage value of the light-emitting driving signal Sd is between the first reference voltage Vref1 and the second reference voltage Vref 2), the driving circuit 304 enters the sleep mode from the operation mode. When the voltage value of the light-emitting driving signal Sd is smaller than the first reference voltage Vref1 and the second reference voltage Vref2, the first comparator 302B and the second comparator 302C are low-level outputs, so that the driving circuit 304 reduces the discharging speed of the light-emitting driving signal Sd. It should be noted that, since the dc operating voltage Vdc is a fixed voltage value, the first detection signal S1 after being compared by the first comparator 302B is also a fixed value. That is, only the light-emitting driving signal Sd with pulse variation will change the result compared by the first comparator 302B, and the second comparator 302C is similar.
Fig. 3B is a circuit diagram of a second embodiment of the detection circuit according to the present invention, and fig. 1a to 3a are combined. The difference between the detection circuit 302 'of the present embodiment and the detection circuit 302 of fig. 3A is that the detection circuit 302' includes a first resistor R1, a first switch Q1, and a voltage dividing circuit 302A, and the voltage dividing circuit 302A includes voltage dividing resistors Ra, rb. The circuit connection is only for illustration, and the detection circuit 302 capable of providing the first detection signal S1 and the second detection signal S2 according to the variation of the light-emitting driving signal Sd is not limited to the present invention. One end of the first resistor R1 receives the dc operating voltage Vdc or the light emitting driving signal Sd, and the other end of the first resistor R1 receives the first reference voltage Vref1. The first switch Q1 includes an input terminal X, an output terminal Y, and a control terminal Z, where the input terminal X of the first switch Q1 receives the dc operating voltage Vdc or the light-emitting driving signal Sd, and the control terminal Z is coupled to the other end of the first resistor R1. One end of the voltage dividing resistor Ra is coupled to the output end Y of the first switch Q1, the other end of the voltage dividing resistor Ra is coupled to one end of the voltage dividing resistor Rb, and the other end of the voltage dividing resistor Rb is coupled to the ground point. The node between the voltage dividing resistor Ra and the output terminal Y of the first switch Q1 provides the first detection signal S1, and the node between the voltage dividing resistors Ra, rb provides the second detection signal S2.
When the voltage value of the light-emitting driving signal Sd is greater than the first reference voltage Vref1, the first switch Q1 is turned on, and the first detection signal S1 and the second detection signal S2 are output at high levels, so that the driving circuit 304 is in the working mode. When the voltage value of the light-emitting driving signal Sd is smaller than the first reference voltage Vref1, the first switch Q1 is turned on, the first detection signal S1 is output at a low level, and the second detection signal S2 is output at a high level. At this time, the driving circuit 304 performs signal recognition of the light emission driving signal Sd. After the light-emitting driving signal Sd is identified (the voltage value of the light-emitting driving signal Sd is smaller than the first reference voltage Vref1 until the first switch Q1 is turned off), the driving circuit 304 enters the sleep mode from the operation mode. When the voltage value of the light-emitting driving signal Sd is too low, the first switch Q1 is turned off, and the first detection signal S1 and the second detection signal S2 are output at low level, so that the driving circuit 304 reduces the light-emitting driving signal Sd. It should be noted that, in the digital circuit, the buffer gate is required to be used to increase the signal strength of the analog-to-digital signal, so that the buffer gate B can be added on the path of the output of the first detection signal S1 and the second detection signal S2 to increase the signal strength of the first detection signal S1 and the second detection signal S2.
Fig. 4 is a schematic circuit diagram of an oscillator according to the present invention, and fig. 1A to 3B are combined. The oscillator 3042 includes a first inverter In1, a second inverter In2, a second resistor R2 and a first capacitor C1, and the circuit connection is merely illustrative, and the invention is not limited thereto, and the oscillator 3042 capable of generating the clock signal CLK is included In the scope of the invention. The first inverter In1 includes an input terminal X, an output terminal Y and a power terminal P, the input terminal X is coupled to one end of the second resistor R2 and one end of the first capacitor C1, the output terminal Y is coupled to the other end of the second resistor R2, and the power terminal P receives the light-emitting driving signal Sd and the sleep signal Ss. The second inverter In2 includes an input terminal X, an output terminal Y and a power terminal P, the input terminal X is coupled to the other ends of the first inverter In1 and the second resistor R2, the output terminal Y is coupled to the other ends of the first capacitor C1 and the control unit 304A, and the power terminal P receives the light-emitting driving signal Sd and the sleep signal Ss. The first inverter In1 and the second inverter In2 are CMOS transistor circuit inverters, and can realize the requirements of accurate control and low power consumption by designing different transistor sizes and enabling and disabling control.
When In the operation mode, the sleep signal Ss enables the first inverter In1 and the second inverter In2 of the oscillator 3042 (e.g. before time t3 or after time t4 In fig. 2B), so that the oscillator 3042 can provide the clock signal CLK with full power operation. When the light-emitting driving signal Sd is detected to be reduced to be smaller than the second threshold V2 (as shown In fig. 2B, time t 3-t 4), the sleep signal Ss provided by the logic circuit 304A-1 controls the first inverter In1 and the second inverter In2 to be In a disabled state, so as to completely turn off the oscillator 3042 and enter the sleep mode. However, the connection, number, size and control signal of the inverters are only illustrative and not intended to limit the present invention.
Fig. 5A is a circuit schematic diagram of a latch circuit according to a first embodiment of the present invention, and fig. 1A to fig. 4 are combined. The latch circuit 3044 includes the second switch Q2, the third switch Q3, the second capacitor C2 and the third resistor R3, and the circuit connection is merely illustrative, and the latch circuit 3044 capable of providing the latch signal Sl according to the variation of the first detection signal S1 is included in the scope of the present invention. Specifically, the second switch Q2 includes an input terminal X, an output terminal Y, and a control terminal Z, and the output terminal Y of the second switch Q2 is coupled to the power line 10 and one end of the second capacitor C2, and receives the dc operating voltage Vdc or the light-emitting driving signal Sd through the power line 10. The input terminal X of the second switch Q2 is coupled to the other end of the second capacitor C2, one end of the third resistor R3 and the logic circuit 304A-1, and the control terminal Z of the second switch Q2 receives the first detection signal S1. The third switch Q3 includes an input terminal X, an output terminal Y, and a control terminal Z, the input terminal X of the third switch Q3 is coupled to the other end of the third resistor R3, the output terminal Y of the third switch Q3 is coupled to the ground point, and the control terminal Z of the third switch Q3 receives the first detection signal S1.
When the first detection signal S1 provided by the detection circuit 302 represents that the light-emitting driving signal Sd is greater than the first threshold V1 (e.g. fig. 2B, before time t 1), the second switch Q2 is turned off, and the third switch Q3 is turned on, so that the second capacitor C2 stores energy. When the light emission driving signal Sd decreases from greater than the first threshold V1 to less than the first threshold V1, the second switch Q2 is turned on, and the third switch Q3 is turned off, so that the second capacitor C2 starts to discharge. When the time when the light emission driving signal Sd is smaller than the first threshold V1 is greater than or equal to the duration, the second capacitor C2 has discharged the internally stored energy to below a predetermined value. At this time, the latch signal Sl provided at the node between the second capacitor C2 and the third resistor R3 causes the logic circuit 304A-1 to notify the register 304A-2 to store the recognized light-emitting driving signal Sde as the light-emitting command Cl. It should be noted that the buffer gate B may be added to the path of the latch signal Sl, and the function is as described in fig. 3B.
Fig. 5B is a circuit schematic diagram of a latch circuit according to a second embodiment of the present invention, and fig. 1A to 5A are combined. The latch circuit 3044' of the present embodiment is different from the latch circuit 3044 of fig. 5A in the coupling position and control manner of the second switch Q2, the third switch Q3, the second capacitor C2 and the third resistor R3. The circuit connection is merely illustrative, and the latch circuit 3044' capable of providing the latch signal Sl according to the variation of the first detection signal S1 is not limited to the present invention. Specifically, the output terminal Y of the second switch Q2 is coupled to the power line 10, and receives the dc operating voltage Vdc or the light-emitting driving signal Sd through the power line 10. The input terminal X of the second switch Q2 is coupled to one end of the third resistor R3, and the control terminal Z of the second switch Q2 receives the first detection signal S1. The input end of the third switch Q3 is coupled to the other end of the third resistor R3, one end of the second capacitor C2 and the logic circuit 304A-1, the output end Y of the third switch Q3 is coupled to the other end of the second capacitor C2 and the ground point, and the control end Z of the third switch Q3 receives the first detection signal S1.
When the first detection signal S1 provided by the detection circuit 302 represents that the light-emitting driving signal Sd is greater than the first threshold V1 (e.g. fig. 2B, before time t 1), the second switch Q2 is turned on, and the third switch Q3 is turned off, so that the second capacitor C2 stores energy. When the light emission driving signal Sd decreases from greater than the first threshold V1 to less than the first threshold V1, the second switch Q2 is turned off and the third switch Q3 is turned on, so that the second capacitor C2 starts to discharge. When the time when the light emission driving signal Sd is smaller than the first threshold V1 is greater than or equal to the duration, the second capacitor C2 has discharged the internally stored energy to below a predetermined value. At this time, the latch signal Sl provided at the node between the third resistor R3 and the second capacitor C2 causes the logic circuit 304A-1 to notify the register 304A-2 to store the recognized light-emitting driving signal Sde as the light-emitting command Cl. It should be noted that the buffer gate B may be added to the path of the latch signal Sl, and the function is as described in fig. 3B.
Fig. 5C is a circuit diagram of a latch circuit according to a third embodiment of the present invention, and fig. 1A to 5B are combined. The latch circuit 3044 'of the present embodiment is different from the latch circuit 3044 of fig. 5A in that the latch circuit 3044' is composed of logic gates, which may be composed of AND gates, OR gates, and inversion gates, and is integrated into the logic circuit 304A-1. When the time of the light-emitting driving signal Sd is less than the first threshold V1 AND is greater than or equal to the duration, the latch signal Sl provided by the logic gate of the latch circuit 3044″ causes the output of the AND gate to change in the logic circuit 304A-1. The logic circuit 304A-1 notifies the register 304A-2 to store the recognized light-emitting driving signal Sde as a light-emitting command Cl according to the change. It should be noted that the output of the AND gate may be judged by an additional logic gate (not shown) (e.g., but not limited to, a protection logic circuit, etc.), AND the recognized light-emitting driving signal Sde may be outputted, so that the output of the AND gate AND the recognized light-emitting driving signal Sde are shown by the dotted line.
Fig. 6 is a schematic circuit diagram of a discharge circuit according to the present invention, and fig. 1A to 5C are combined. The discharging circuit 3046 includes a discharging switch Q4, and the discharging switch Q4 has an input terminal X, an output terminal Y, and a control terminal Z. The input end of the discharging switch Q4 is coupled to the power line 10, the output end Y of the discharging switch Q4 is coupled to the ground, and the control end Z of the discharging switch Q4 receives the second detection signal S2. The circuit connection is only for illustration, and is not limited to the present invention, as long as the discharge speed of the light-emitting driving signal Sd can be adjusted according to the variation of the second detection signal S2. When the light-emitting driving signal Sd is greater than the second threshold V2, the second detection signal S2 controls the discharge switch Q4 to be turned on, so that the light-emitting driving signal Sd generates a current path to rapidly discharge. When the light-emitting driving signal Sd is smaller than the second threshold V2, the second detection signal S2 controls the discharge switch Q4 to turn off, so that the light-emitting driving signal Sd floats (flows), and the light-emitting driving signal Sd decreases the discharge speed through the turn-off of the discharge switch Q4. It should be noted that, in order to avoid that the current flowing to the ground point through the discharge switch Q4 is too large when the discharge switch Q4 is turned on, the fourth resistor R4 may be installed on the current path from the light-emitting driving signal Sd to the ground point to limit the current of the current path.
The above-described embodiments are merely preferred embodiments for fully explaining the present invention, and the scope of the present invention is not limited thereto. Equivalent substitutions and modifications will occur to those skilled in the art based on the present invention, and are intended to be within the scope of the present invention. The protection scope of the invention is subject to the claims.