CN113809172A - InAlAs-based HEMT structure with silicon-based heterogeneous integration - Google Patents
InAlAs-based HEMT structure with silicon-based heterogeneous integration Download PDFInfo
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- CN113809172A CN113809172A CN202111073898.1A CN202111073898A CN113809172A CN 113809172 A CN113809172 A CN 113809172A CN 202111073898 A CN202111073898 A CN 202111073898A CN 113809172 A CN113809172 A CN 113809172A
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
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- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
- H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
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- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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Abstract
本发明公开了一种硅基异质集成的InAlAs基HEMT结构，属于半导体制造领域。该结构包括Si衬底和在Si衬底上从下至上依次生长的缓冲层、InXGa1‑XAs沟道层、InXAl1‑XAs空间隔离层、平面掺杂层、InXAl1‑XAs势垒层、InXGa1‑XAs盖帽层；缓冲层包括从下至上依次形成采用低温生长的第一GaAs缓冲层、采用中温生长的InXGa1‑XAs/GaAs超晶格缓冲层、采用高温生长的第二GaAs缓冲层、采用低温生长的InXAl1‑XAs组分渐变缓冲层。本发明可以大幅降低高速HEMT器件的成本，还可以利用硅基材料高集成度的特性实现化合物半导体器件与集成电路的结合。
The invention discloses a silicon-based hetero-integrated InAlAs-based HEMT structure, which belongs to the field of semiconductor manufacturing. The structure includes a Si substrate and a buffer layer, an InXGa1 - XAs channel layer, an InXAl1 - XAs space isolation layer, a planar doping layer, an InXAs layer, which are sequentially grown on the Si substrate from bottom to top. Al 1-X As barrier layer, In X Ga 1-X As capping layer; the buffer layer includes a first GaAs buffer layer grown at a low temperature, In X Ga 1-X As/GaAs grown at a medium temperature in sequence from bottom to top A superlattice buffer layer, a second GaAs buffer layer grown at high temperature, and an In X Al 1-X As composition graded buffer layer grown at low temperature. The invention can greatly reduce the cost of high-speed HEMT devices, and can also realize the combination of compound semiconductor devices and integrated circuits by utilizing the high integration characteristics of silicon-based materials.
Description
Technical Field
The invention relates to a silicon-based heterogeneous integrated InAlAs-based HEMT structure, belonging to the field of semiconductor manufacturing.
Background
In the millimeter wave band, an InP HEMT (High electron mobility transistor) device has High breakdown voltage, and the properties of large conduction band discontinuity, large two-dimensional electron gas concentration, High electron mobility in a channel, and the like at the interface of the heterojunction inaias/InGaAs (indium aluminum arsenide/indium gallium arsenide) are more suitable for High-frequency application. At present, InP (indium phosphide) -based HEMTs are widely applied to the fields of satellite communication, millimeter wave radars, microwave circuits, active and passive millimeter wave imaging and the like. However, the small size, high cost, fragility, etc. of InP substrates limit their large-scale, low-cost production.
The realization of the InP-like HEMT material on the silicon substrate can reduce the manufacturing cost of the compound semiconductor, and can realize the combination of the compound semiconductor device and the integrated circuit by utilizing the high integration characteristic of the silicon-based material, thereby having important economic and application values.
Disclosure of Invention
In order to solve the technical problem, the invention provides a silicon-based hetero-integrated InAlAs-based HEMT structure.
The invention adopts the following technical scheme for solving the technical problems:
the invention provides a silicon-based heterogeneous integrated InAlAs-based HEMT structure, which comprises: si substrate, and buffer layer and In which are grown on the Si substrate from bottom to top In sequenceXGa1-XAs channel layer and InXAl1-XAs space isolation layer, planar doping layer, InXAl1- XAs barrier layer and InXGa1-XAn As cap layer; the buffer layer comprises a first GaAs buffer layer formed by low-temperature growth and In formed by medium-temperature growth from bottom to top In sequenceXGa1-XAs/GaAs superlattice buffer layer, second GaAs buffer layer grown at high temperature, and In grown at low temperatureXAl1-XAnd the As component is gradually changed to form the buffer layer.
The invention can utilize the epitaxial growth technologies of MOCVD (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), UHVCVD (ultra-high vacuum chemical vapor deposition) and the like to complete the following structure.
1) A p-type high-resistance Si material single crystal is selected as a substrate.
2) Growing a first GaAs buffer layer on the substrate under a low-temperature condition, wherein the thickness of the first GaAs buffer layer is 300-600 nm.
3) Growing In on the first GaAs buffer layer under a medium temperature conditionXGa1-XAs/GaAs superlattice buffer layer using In with periodic epitaxyXGa1-XAs/GaAs superlattice structure and GaAs, the period number is 3-5 InXGa1-XThe number of cycles of the As/GaAs superlattice structure is 5-10 InXGa1-XIn As/GaAs superlattice structureXGa1-XThe thickness of As is 10-15 nm, the In component x is 0.15-0.2, the thickness of GaAs is 10-15 nm, and the thickness of GaAs on the superlattice structure is 200-300 nm.
4) And growing a second GaAs buffer layer on the superlattice buffer layer at a high temperature, wherein the thickness of the second GaAs buffer layer is 400-800 nm.
5) Growing In under low temperature conditions on the second GaAs buffer layerXAl1-XThe As component gradient buffer layer adopts an In component gradient epitaxial method, the In component x is changed from 0 gradient to 0.52-0.7, and each layer of InXAl1-XAs has a thickness of 100 to 250nm and each In layerXAl1-XThe In component x gradient interval Deltax of As is 0.1-0.15.
6) InXAl1-XIn grows on the As component gradual change buffer layer under the condition of medium temperatureXGa1-XThe As channel layer has a thickness of 10 to 30nm and an In component x of 0.53 to 0.8.
7) Growing In on the channel layerXAl1-XThe As space isolation layer has a thickness of 3-10 nm, and the In component x is 0.52-0.7.
8) Growing a planar doping layer on the space isolation layer, wherein the dosage of doping Si is 2.0 multiplied by 1012cm-2～6.0×1012cm-2。
9) Growing In on the planar doped layerXAl1-XThe As barrier layer has a thickness of 8 to 40nm and an In component x of 0.52 to 0.7.
10) Growing In on the barrier layerXGa1-XThe As cap layer is 3-20 nm thick, and the In component x is 0.53-0.7.
The invention has the following beneficial effects:
1. the substitution of the Si substrate for the InP substrate can reduce the manufacturing cost of the compound semiconductor, and can realize the combination of the compound semiconductor device and the integrated circuit by utilizing the high integration of the silicon-based material.
2. By epitaxial InXGa1-XThe As/GaAs superlattice buffer layer can effectively filter threading dislocation, and complicated process steps such As manufacturing a pattern substrate are not needed to reduce the threading dislocation.
3. By using InXAl1-XThe As component gradient material is used As a buffer layer of HEMT epitaxy, and the In component of the As component gradient material can be changed to adjust the epitaxy structure and the energy band structure of HEMT, so that the silicon-based HEMT material with high electron mobility can be obtained.
Drawings
Fig. 1 is a schematic diagram of a silicon-based hetero-integrated inaias-based HEMT structure proposed by the present invention.
Wherein: 101. a p-type Si substrate; 102. a first GaAs buffer layer; 103. inXGa1-XAn As/GaAs superlattice buffer layer; 104. a second GaAs buffer layer; 105. inXAl1-XAn As component gradient buffer layer; 106. inXGa1-XAn As channel layer; 107. inXAl1- XAn As space isolation layer; 108. a planar doping layer; 109. inXAl1-XAn As barrier layer; 110. inXGa1-XAn As cap layer.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
The invention provides a silicon-based hetero-integrated InAlAs-based HEMT structure, as shown in figure 1, comprising: a p-type Si substrate 101, and a buffer layer and In sequentially grown on the p-type Si substrate 101 from bottom to topXGa1-XAs channel layer 106, InXAl1-XAs space isolation layer 107, planar doping layer 108, InXAl1-XAs barrier layer 109, InXGa1-XAn As cap layer 110; the buffer layer comprises a first GaAs buffer layer 102 formed from bottom to top in sequence and adopting low-temperature growthIn grown at a moderate temperatureXGa1-XAs/GaAs superlattice buffer layer 103, second GaAs buffer layer 104 grown at high temperature, and In grown at low temperatureXAl1-XAn As composition graded buffer layer 105.
The p-type Si substrate 101 is a p-type high-resistance Si material single crystal.
The first GaAs buffer layer 102 is made of GaAs materials, the growth temperature is 400 ℃, the GaAs buffer layer is not doped, and the thickness of the GaAs buffer layer is 300-600 nm.
InXGa1-XAs/GaAs superlattice buffer layer 103 adopts In of periodic epitaxyXGa1-XAs/GaAs superlattice structure and GaAs, the growth temperature is 500 ℃, the period number is 3-5, InXGa1-XThe number of cycles of the As/GaAs superlattice structure is 5-10 InXGa1-XIn As/GaAs superlattice structureXGa1-XThe thickness of As is 10-15 nm, the In component x is 0.15-0.2, the thickness of GaAs is 10-15 nm, the thickness of GaAs on the superlattice structure is 200-300 nm, and the superlattice buffer layer is mainly used for filtering threading dislocation extending from the first GaAs buffer layer 102 to the upper layer.
The second GaAs buffer layer 104 is made of GaAs material, the growth temperature is 600 ℃, the second GaAs buffer layer is not doped, and the thickness of the second GaAs buffer layer is 400-800 nm.
InXAl1-XThe As component gradient buffer layer 105 adopts an In component gradient epitaxial method, the growth temperature is 400 ℃, the In component x is changed from 0 gradient to 0.52-0.7, and each layer of InXAl1-XAs has a thickness of 100 to 250nm and each In layerXAl1- XIn component x gradient interval Deltax of As is 0.1-0.15, the layer InXAl1-XThe As buffer layer enables the surface to be flat in a mode of slowly releasing stress, and the As buffer layer is used As an epitaxial platform of the HEMT.
InXGa1-XThe As channel layer 106 is grown at 500 ℃ and provides a conductive channel for two-dimensional electron gas, the thickness of the As channel layer is 10-30 nm, and the In component x is 0.53-0.8.
InXAl1-XAn As space isolation layer 107 grown at 500 deg.C for ionizing donor impurities at the center (planar doping layer 108) and two-dimensional electron gas layer (In)XGa1-XAs channel layer 106) is spatially isolated and has a thickness of 3 to 10nm and an In component x of 0.52 to 0.7, thereby reducing ionization scattering.
A planar doping layer 108 with a growth temperature of 500 ℃ and a Si doping dose of 2.0 × 1012cm-2～6.0×1012cm-2For providing free electrons.
InXAl1-XThe As barrier layer 109 is grown at a temperature of 500 ℃ to form a Schottky contact with the gate metal, and allows free electrons generated from the planar doping layer 108 to migrate to the channel layer 106, wherein the thickness of the As barrier layer is 8 to 40nm, and the In component x is 0.52 to 0.7.
InXGa1-XThe As cap layer 110 is grown at 500 ℃, heavily doped to improve ohmic contact In device preparation, and the barrier layer 109 is prevented from being directly exposed to air to generate an oxidation reaction, the thickness is 3-20 nm, and the In component x is 0.53-0.7.
Example 1:
the following structure was completed using a Molecular Beam Epitaxy (MBE) growth method.
1) Selecting a p-type high-resistance Si material single crystal As a p-type Si substrate 101, heating the substrate to 1100 ℃ under the protection of As atmosphere, stopping for 10min to remove an oxide film on the surface of the Si substrate, and cooling the substrate to 400 ℃ to wait for growth;
2) growing an undoped first GaAs buffer layer 102 with the thickness of 400nm, and heating the substrate to 500 ℃;
3) continuing to grow In0.15GaAs/GaAs superlattice buffer layer, In of 5 periods grows first0.15GaAs/GaAs superlattice structure, In0.15The thickness of GaAs and GaAs is 10nm, then GaAs with the thickness of 200nm is grown on the superlattice structure, the growth process (superlattice and GaAs with the thickness of 200 nm) is repeated for 3 times, and the temperature of the rear substrate is raised to 600 ℃;
4) continuing to grow a second undoped GaAs buffer layer 104 with the thickness of 500nm, and cooling the rear substrate to 400 ℃;
5) continuing to grow InAlAs component gradient buffer layer 105, and growing AlAs and In sequence0.15AlAs、In0.25AlAs、In0.35AlAs、In0.45AlAs、In0.52AlAs, grown thickThe temperature is 200nm, and the temperature of the rear substrate is raised to 500 ℃;
6) continuing to grow In with a thickness of 14nm0.65A GaAs channel layer;
7) continuing to grow In 10nm thick0.52An AlAs space isolation layer;
8) continuing to grow a planar doping layer 108, opening a baffle plate of the Si source furnace under the protection of As atmosphere, wherein the dosage of the doped Si is 4.0 multiplied by 1012cm-2；
9) Continuing to grow In with a thickness of 36nm0.52An AlAs barrier layer;
10) continuing to grow In 20nm thick0.53A GaAs cap layer.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A silicon-based heterogeneous integrated InAlAs-based HEMT structure is characterized by comprising a Si substrate, a buffer layer, In and a hole, wherein the buffer layer and the In are sequentially grown on the Si substrate from bottom to topXGa1-XAs channel layer and InXAl1-XAs space isolation layer, planar doping layer, InXAl1- XAs barrier layer and InXGa1-XAn As cap layer; the buffer layer comprises a first GaAs buffer layer formed by low-temperature growth and In formed by medium-temperature growth from bottom to top In sequenceXGa1-XAs/GaAs superlattice buffer layer, second GaAs buffer layer grown at high temperature, and In grown at low temperatureXAl1-XAnd the As component is gradually changed to form the buffer layer.
2. The InAlAs-based HEMT structure of claim 1, wherein the Si substrate is p-type high-resistance Si.
3. The InAlAs-based HEMT structure of the silicon-based hetero-integration, as claimed in claim 1, wherein the thickness of the first GaAs buffer layer is 300-600 nm, and the thickness of the second GaAs buffer layer is 400-800 nm.
4. The InAlAs-based HEMT structure of claim 1, wherein In is InXGa1-XThe As/GaAs superlattice buffer layer adopts In with periodic epitaxyXGa1-XAs/GaAs superlattice structure and GaAs material, In epitaxial on superlattice structureXGa1-XThe total period number of the As/GaAs superlattice structure and the GaAs material epitaxial thereon is 3-5, InXGa1-XThe number of cycles of the As/GaAs superlattice structure is 5-10 InXGa1-XIn As/GaAs superlattice structureXGa1-XThe thickness of As is 10-15 nm, the In component x is 0.15-0.25, the thickness of GaAs is 10-15 nm, and the thickness of GaAs extending on the superlattice structure is 200-300 nm.
5. The InAlAs-based HEMT structure of claim 1, wherein In is InXAl1-XThe As component gradient buffer layer is generated by an epitaxial method with gradient variation of In components, the gradient of the In component x is changed from 0 to 0.52-0.7, and each layer of In isXAl1-XAs has a thickness of 100 to 250nm and each In layerXAl1-XThe In component x gradient interval Deltax of As is 0.1-0.15.
6. The InAlAs-based HEMT structure of claim 1, wherein In is InXGa1-XThe As channel layer has a thickness of 10 to 30nm and an In component x of 0.53 to 0.8.
7. The InAlAs-based HEMT structure of claim 1, wherein In is InXAl1-XThe As space isolation layer has a thickness of 3-10 nm, and the In component x is 0.52-0.7.
8. The InAlAs-based HEMT structure of claim 1, wherein the Si doping dose of the planar doping layer is 2.0 x 1012cm-2～6.0×1012cm-2。
9. The InAlAs-based HEMT structure of claim 1, wherein In is InXAl1-XThe As barrier layer has a thickness of 8 to 40nm and an In component x of 0.52 to 0.7.
10. The InAlAs-based HEMT structure of claim 1, wherein In is InXGa1-XThe As cap layer is 3-20 nm thick, and the In component x is 0.53-0.7.
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