CN113809162B - Power element - Google Patents

Abstract

The present invention provides a power element, comprising: an epitaxial layer having a trench extending from a first surface of the epitaxial layer to a second surface; an isolation field plate located in the trench; an insulating filling layer located in the trench wherein, surrounding the sidewall and bottom of the lower portion of the isolation field plate; a first gate and a second gate, located in the trench and on the insulating filling layer; and a dielectric layer surrounding the first sidewalls of the gate and the second gate, wherein the lower portion of the dielectric layer has a maximum width of the dielectric layer, and wherein the isolation field plate includes a first portion and a second portion, the first portion adjacent to the lower portion of the dielectric layer, and has a higher doping concentration than the second portion.

Description

power components

technical field

The present invention relates to a technical field of semiconductor elements, and in particular to a power element.

Background technique

Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a voltage-type control element. Its driving circuit is simple, its driving power is large, its switching speed is fast, and it has a high operating frequency. It is a switch widely used in various electronic application components. element.

Trench gate MOSFET is a power MOSFET whose gate is buried in the substrate or epitaxial layer to have a vertical channel. The power metal-oxide-semiconductor field-effect transistor has a small unit size and a small on-resistance, and is suitable for a power MOSFET of a medium and low voltage.

A split gate trench gate (Split Gate Trench, SGT) metal oxide semiconductor field effect transistor is a power MOSFET that splits a single gate into two gates and separates the two gates with an isolation field plate. . The isolation field plate deep into the epitaxial layer can increase the lateral depletion and increase the N-driftdoping concentration. Isolating the field plates also reduces gate and drain overlap and therefore reduces gate-to-drain capacitance. Therefore, the structure has excellent performance in both static and dynamic characteristics.

However, due to the complex process of the SGT MOSFET, leakage current is easily generated between the gate and the isolation field plate, so that the breakdown voltage of the component is insufficient. On the other hand, if the doping concentration of the epitaxial layer is reduced in order to reduce the leakage current between the gate and the isolation field plate, the on-resistance (Ron) will increase, and the gate charge (QG) will increase. and affect the performance of the device.

Contents of the invention

The present invention proposes a power element that can reduce the leakage current between the gate and the isolation field plate, increase the breakdown voltage of the element, reduce the on-resistance, reduce the charge of the gate (QG), and improve the figure of merit. FOM), to improve the performance of the device.

A power element according to an embodiment of the present invention includes a power element, comprising: an epitaxial layer having a trench extending from a first surface of the epitaxial layer to a second surface; a doped drain layer located on the epitaxial layer on the second surface of the layer; the first body region and the second body region are located in the epitaxial layer on both sides of the trench; the first source doped region and the second source doped region are respectively located In the first body region and the second body region; the isolated field plate is located in the trench; the insulating filling layer is located in the trench and surrounds the sidewall and the bottom of the lower part of the isolated field plate; A gate and a second gate are located in the trench and on the insulating filling layer, wherein the first gate is located between the isolation field plate and the first base region, and the second a gate is located between the isolation field plate and the second base region; and a dielectric layer surrounds sidewalls of the first gate and the second gate, wherein a lower portion of the dielectric layer has The maximum width of the dielectric layer, and wherein the isolation field plate includes a first portion and a second portion, the first portion is adjacent to the lower portion of the dielectric layer and has a higher doping concentration than the second portion .

Based on the above, there is a sufficiently thick oxide layer at the bottom corner of the gate trench, so the leakage current between the gate and the isolation field plate can be reduced, and the breakdown voltage of the element can be increased. On the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (QG), improve the quality factor (FOM), and improve the performance of the device.

Description of drawings

1A to 1J are schematic cross-sectional views of a method for manufacturing a power device according to a first embodiment of the present invention.

FIG. 2 is an enlarged schematic view of region R in FIG. 1J .

3A to 3E are schematic cross-sectional views of a manufacturing method of a power device according to a second embodiment of the present invention.

4A to 4E are schematic cross-sectional views of a manufacturing method of a power device according to a third embodiment of the present invention.

5A to 5D are schematic cross-sectional views of a manufacturing method of a power device according to a fourth embodiment of the present invention.

FIG. 6 shows a schematic cross-sectional view of two units of the power device.

Reference signs:

10: Substrate

12: Drain doped layer

14: epitaxial layer

14a: first surface

14b: Second surface

16: Ditch

18, 18a: insulating filling layer

20, 20a, 20a', 20c, 31: conductor layer

20b: doped layer, doped region

20b', 20d: doped regions

22: First gate trench

24: Second gate trench

30, 46: dielectric layer

30a: first gate dielectric layer

30b: second gate dielectric layer

30c: first insulating layer

30d: Second insulating layer

30L: lower part

30U: upper part

32, 32': the first grid

34, 34': the second gate

36: First matrix area

38: Second matrix area

42: The first source doped region

44: Second source doped region

52: First contact window opening

54: second contact window opening

62: The first doped region

64, 64': the second doped region

72: First contact window

74, 74': second contact window

C1, C1': unit

PL: isolated field plate

P1: Part I

P2: Part Two

P3: The third part

IMP 1, IMP 2, IMP3: ion implantation process

T _min1 , T _min2 : minimum thickness

T _max1 , T _max2 : maximum thickness

α1, α2, β1, β2: bottom angle

θ: included angle

Detailed ways

1A to 1J are schematic cross-sectional views of a method for manufacturing a power device according to a first embodiment of the present invention. Power components are, for example, SGT MOSFETs.

Referring to FIG. 1A , the method for manufacturing a power device includes forming a doped drain layer 12 in a substrate 10 . The substrate 10 may be a semiconductor substrate 10, such as a silicon substrate. The drain doped layer 12 can be formed by an in-situ doping process during wafer fabrication. The drain doped layer 12 has dopants of the first conductivity type. The dopant of the first conductivity type is an N-type dopant, such as phosphorus or arsenic. Next, an epitaxial layer 14 is formed on the drain doped layer 12 . The method for forming the epitaxial layer 14 is, for example, a selective epitaxial growth process. The epitaxial layer 14 has dopants of the first conductivity type. The dopant of the first conductivity type is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the epitaxial layer 14 is, for example, lower than that of the drain doping layer 12 . The dopants of the epitaxial layer 14 can be formed in-situ during the selective epitaxial growth process, or formed by ion implantation after the selective epitaxial growth process.

Thereafter, trenches 16 are formed in epitaxial layer 14 . The trench 16 extends from the first surface 14 a to the second surface 14 b of the epitaxial layer 14 . The trench 16 can be formed by photolithography and etching processes. The etching process may be an anisotropic etching process, an isotropic etching process or a combination thereof. Afterwards, an insulating filling layer 18 and a conductive layer 20 are formed on the epitaxial layer 14 and in the trench 16 . The material of the insulating filling layer 18 is, for example, silicon oxide, silicon nitride or a combination thereof formed by chemical vapor deposition. The conductive layer 20 is formed on the insulating filling layer 18 and fills up the remaining space of the trench 16 . The conductive layer 20 may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by chemical vapor deposition.

Referring to FIG. 1B , an etch-back process is performed on the conductive layer 20 to remove the conductive layer 20 outside the trench 16 to leave the conductive layer 20 a in the trench 16 . In some embodiments, the top surface of conductor layer 20 a is lower than the top surface of epitaxial layer 14 .

Referring to FIG. 1C, a doped layer (or called a doped region) 20b is formed on or in the conductive layer 20a. The doped layer/doped region 20b has the same conductivity type dopant as the conductor layer 20a, for example, the first conductivity type dopant. The dopant of the first conductivity type is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the doped layer/doped region 20b is, for example, higher than that of the conductive layer 20a. In some embodiments, the doping concentration of the doped layer/region 20 b ranges from 5E18 1/cm ³ to 5E20 1/cm ³ . The thickness/depth of the doped layer/doped region 20b greater than 1500 angstroms can facilitate the control of the subsequent etching process for forming the gate trench. The thickness/depth range of the doped layer/doped region 20b is, for example, 1600 angstroms to 2500 angstroms.

In one embodiment, the doped region 20b is located in the conductive layer 20a. The method for forming the doped region 20b is, for example, performing an ion implantation process IMP 1 on the conductor layer 20a. The ion implantation process IMP 1 implants dopants into the conductor layer 20a in a manner perpendicular to the surface of the substrate 10 . In another embodiment, the doped layer 20b is located on the conductive layer 20a. The method of forming the doped layer 20b is, for example, to perform an in-situ chemical vapor deposition process after the conductive layer 20a is formed, so as to form the doped layer 20b on the conductive layer 20a with a concentration higher than that of the conductive layer 20a.

Afterwards, referring to FIG. 1D , a conductive layer 20 c is formed on the doped layer/doped region 20 b. The method for forming the conductive layer 20 c is, for example, to perform an etch-back process after forming the conductive layer on the insulating filling layer 18 and the doped layer/doped region 20 b to remove the conductive layer outside the trench 16 . The conductive layer 20c may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by chemical vapor deposition. The top surface of the conductor layer 20 c may be coplanar with or lower than the first surface 14 a of the epitaxial layer 14 .

Thereafter, referring to FIG. 1E , an etch-back process is performed on the insulating filling layer 18 to remove the insulating filling layer 18 outside the trench 16 to leave the insulating filling layer 18 a in the trench 16 . The insulating filling layer 18a surrounds the sidewall and bottom surface of the conductor layer 20a, and surrounds the sidewall of a part of the doped layer/doped region 20b, and the top surface of the insulating filling layer 18a is between the top surface and the bottom surface of the doped region 20b. between. In other words, the insulating filling layer 18a has a first gate trench 22 and a second gate trench 24 thereon. The sidewalls of the first gate trench 22 and the second gate trench 24 expose the epitaxial layer 14, the conductor layer 20c and part of the doped region 20b, and the first gate trench 22 and the second gate trench The bottom surface of 24 exposes the top surface of insulating filling layer 18a. The etch back process is, for example, an anisotropic etch process, an isotropic etch process or a combination thereof.

Referring to FIG. 1F , a dielectric layer 30 is formed on the epitaxial layer 14 and the conductive layer 20 c and in the first gate trench 22 and the second gate trench 24 . The dielectric layer 30 may be silicon oxide formed by thermal oxidation or chemical vapor deposition. In some embodiments where the dielectric layer 30 is a silicon oxide layer formed by thermal oxidation, the doping concentration of the doped region 20b is greater than that of the epitaxial layer 14, and compared with the epitaxial layer 14, the doped region 20b is denser. prone to oxidation. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the doped region 20 b is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the epitaxial layer 14 . In addition, since the doping concentration of the doped region 20b is greater than that of the conductive layer 20c, the doped region 20b is easier to oxidize than the conductive layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the doped region 20b is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20c. Describe it.

Referring to FIG. 1G , a conductive layer 31 is formed on the dielectric layer 30 . The conductive layer 31 fills up the remaining space between the first gate trench 22 and the second gate trench 24 . The conductive layer 31 may be a semiconductor material, such as doped polysilicon formed by chemical vapor deposition.

Please refer to FIG. 1H, etch back the conductive layer 31, and remove the conductive layer 31 except the first gate trench 22 and the second gate trench 24, so that the first gate trench 22 and the second gate A first gate 32 and a second gate 34 are formed in the trench 24 . Top surfaces of the first gate 32 and the second gate 34 may be coplanar with the first surface 14 a of the epitaxial layer 14 or lower than the first surface 14 a of the epitaxial layer 14 .

Please continue to refer to FIG. 1H , a first body region 36 and a second body region 38 are formed in the epitaxial layer 14 on both sides of the trench 16 . The first body region 36 and the second body region 38 extend from the first surface 14 a to the second surface 14 b of the epitaxial layer 14 . The first body region 36 and the second body region 38 have dopants of the second conductivity type, such as P-type dopants. The P-type dopant is, for example, boron or boron trifluoride. The formation method of the first body region 36 and the second body region 38 is, for example, an ion implantation method. In another embodiment, the first body region 36 and the second body region 38 may be formed before the trench 16 is formed. For example, the first body region 36 and the second body region 38 can be formed in-situ during the selective epitaxial growth process for forming the epitaxial layer 14, or can be formed by ions after the selective epitaxial growth process. Implantation process to form it.

Next, a first doped source region 42 and a second doped source region 44 are respectively formed in the first body region 36 and the second body region 38 . The first doped source region 42 and the second doped source region 44 . It has a dopant of the first conductivity type, such as an N-type dopant. N-type dopant, such as phosphorus or arsenic. A method for forming the first doped source region 42 and the second doped source region 44 is, for example, an ion implantation method.

1I, a dielectric layer 46 is formed on the epitaxial layer 14 to cover the first source doped region 42, the second source doped region 44, the first gate 32, the second gate 34 and the dielectric Layer 30. The dielectric layer 46 is, for example, borophosphosilicate glass (BPSG), silicon oxide, silicon nitride or a combination thereof formed by chemical vapor deposition. Next, photolithography and etching processes are performed to form a first contact opening 52 and a second contact opening 54 in the dielectric layer 46 to expose the first doped source region 42 and the second doped source region respectively. District 44. Thereafter, a first doped region 62 and a second doped region 64 are respectively formed in the first body region 36 and the second body region 38 . There are dopants of the second conductivity type in the first doped region 62 and the second doped region 64 . The dopant of the second conductivity type can be a P-type dopant, such as boron or boron trifluoride. The method for forming the first doped region 62 and the second doped region 64 is, for example, an ion implantation method.

Please refer to FIG. 1J, after that, the first contact window 72 contacting the first doped region 62 and the second contact window contacting the second doped region 64 are respectively formed in the first contact opening 52 and the second contact opening 54. The contact window 74, and the first contact window 72 and the second contact window 74 are electrically connected to each other. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate 32 to the second gate 34 .

Referring to FIG. 1J , in this embodiment, the conductive layer 20 a , the doped layer/doped region 20 b and the conductive layer 20 c may be collectively referred to as a source polysilicon layer or an isolation field plate PL. The isolated field plate PL can even out the electric field distribution of the epitaxial layer 14 below the first p-body region 36 and the second p-body region 38 , so that the peak electric field strength can be reduced, and thus the breakdown voltage can be increased. On the other hand, under the same breakdown voltage, the doping concentration of the epitaxial layer 14 can be increased to reduce the on-resistance (Ron).

Furthermore, in this embodiment, the isolation field plate PL includes a first portion P1 and a second portion P2. The doped layer/doped region 20b is the first part P1 of the isolated field plate PL; the conductive layer 20a and the conductive layer 20c can be collectively referred to as the second part P2 of the isolated field plate PL. The first portion P1 is sandwiched by the second portion P2, and the doping concentration of the first portion P1 is greater than that of the second portion P2.

Since the first portion P1 of the isolation field plate PL with higher concentration in this embodiment is exposed by the first gate trench 22 and the second gate trench 24, and the first gate trench 22 and the second gate trench The bottom of the groove 24 is higher than the bottom of the first portion P1 (as shown in FIG. 1E ). Therefore, during the subsequent thermal oxidation process for forming the dielectric layer 30 , the first portion P1 with a higher concentration contributes to the formation of a thicker silicon oxide layer, and therefore, more of the first portion P1 is oxidized. Therefore, after the dielectric layer 30 is formed, in the isolation field plate PL between the top and bottom surfaces of the first gate trench 22 and the second gate trench 24, the first portion P1 is the narrowest width. , as shown in Figure 1F and Figure 2.

FIG. 2 shows an enlarged schematic view of the region R in FIG. 1J. Referring to FIG. 2 , the dielectric layer 30 between the epitaxial layer 14 and the first gate 32 is called a first gate dielectric layer 30 a. The dielectric layer 30 between the epitaxial layer 14 and the second gate 34 is called a second gate dielectric layer 30b. The dielectric layer 30 between the isolated field plate PL and the first gate 32 is referred to as a first insulating layer 30c. The dielectric layer 30 between the isolated field plate PL and the second gate 34 is referred to as a second insulating layer 30d.

The first portion P1 (doped layer/doped region 20b ) of the isolation field plate PL is adjacent to and in contact with the first insulating layer 30c and the lower portion 30L of the second insulating layer 30d. In the isolated field plate PL, the second portion P2 (conductor layer 20 c ) above the first portion P1 is adjacent to and in contact with the first insulating layer 30 c and the upper portion 30U of the second insulating layer 30 d.

Since the first part P1 having a higher concentration helps to form a thicker silicon oxide layer, the lower part 30L of the first insulating layer 30c and the second insulating layer 30d is the part of the first insulating layer 30c and the second insulating layer 30d. The maximum thickness T _max1 , T _max2 . In addition, although the first insulating layer 30c and the second insulating layer 30d between the bottom surface of the first gate 32 and the first portion P1 (doped layer/doped region 20b) of the isolated field plate PL have a minimum thickness T _min1 , T _min2 , however, the ratio of the minimum thickness T _min1 to the average thickness of the first insulating layer 30c and the ratio of the minimum thickness T _min2 to the average thickness of the second insulating layer 30d are still greater than 0.8. In one embodiment, the average thickness of the first insulating layer 30c and the second insulating layer 30d is about 900 angstroms, wherein the maximum thicknesses T _max1 and T _max2 of the lower part 30L are about 1600 angstroms, and the minimum thicknesses T _min1 and T of the lower part 30L are about 1600 angstroms. _min2 is about 800 Angstroms.

Since the lower portion 30L of the dielectric layer 30 (the first insulating layer 30c and the second insulating layer 30d) in contact with the first gate 32 and the second gate 34 has a thick and sufficiently thick thickness, the first gate can be reduced. The leakage current between the gate 32 and the isolation field plate PL and between the second gate 34 and the isolation field plate PL increases the breakdown voltage of the device.

3A to 3E are schematic cross-sectional views of a manufacturing method of a power device according to a second embodiment of the present invention.

Referring to FIG. 3A , according to the method described in the above-mentioned first embodiment, after the conductive layer 20 a is formed in the trench 16 , two doped regions 20 b ′ are formed in the conductive layer 20 a. The doped region 20b' is formed in the edge region of the conductor layer 20a, and the doped region 20b' is not formed in the central region of the conductor layer 20a. The doped region 20 b ′ has the same conductivity type dopant as that of the conductor layer 20 a , for example, the first conductivity type dopant. The dopant of the first conductivity type is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the doping region 20b' is higher than that of the conductor layer 20a. In some embodiments, the doping concentration of the doping region 20b′ ranges from 5E18 1/cm ³ to 5E20 1/cm ³ . The method for forming the doped region 20 b ′ is, for example, performing an oblique ion implantation process IMP 2 on the conductor layer 20 a. The included angle θ between the inclined ion implantation process IMP 2 and the normal direction of the surface of the substrate 10 ranges from 30 degrees to 60 degrees, for example.

Thereafter, referring to FIG. 3B , according to the method described in the first embodiment above, a conductive layer 20c is formed on the conductive layer 20a and the doped region 20b'. In this embodiment, the conductive layer 20a, the doped region 20b' and the conductive layer 20c may be collectively referred to as a source polysilicon layer or an isolation field plate PL. The isolation field plate PL may include a first portion P1 and a second portion P2. The first part P1 comprises two separate doped regions 20b' which are not connected. The second portion P2 includes the conductive layer 20a and the conductive layer 20c connected to each other, and separates the two doped regions 20b' from each other. The doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2.

Afterwards, referring to FIG. 3C , according to the method described in the first embodiment above, the insulating filling layer 18 is etched back to leave the insulating filling layer 18a in the trench 16, and an insulating filling layer 18a is formed on the insulating filling layer 18a. The first gate trench 22 and the second gate trench 24 . The heights of the bottom surfaces of the first gate trench 22 and the second gate trench 24 are between the top and bottom surfaces of the two doped regions 20b'.

Thereafter, referring to FIG. 3D , according to the method described in the above-mentioned first embodiment, a dielectric layer is formed on the epitaxial layer 14 and the conductor layer 20c and in the first gate trench 22 and the second gate trench 24 30. Similarly, since the doping concentration of the doped region 20b' is greater than the doping concentration of the conductive layer 20c and greater than the doping concentration of the epitaxial layer 14, compared with the conductive layer 20c and the epitaxial layer 14, the doped region 20b' is easier to oxidize . Therefore, the thickness of the dielectric layer 30 formed on the surface of the doped region 20b' is greater than the thickness of the dielectric layer 30 formed on the surface of the conductive layer 20c, and the dielectric layer 30 formed on the surface of the conductive layer 20c The thickness is greater than the thickness of the dielectric layer 30 formed on the surface of the epitaxial layer 14 .

Afterwards, referring to FIG. 3E , the subsequent processes are performed according to the method described in the above-mentioned first embodiment until the first contact holes 72 and the second contact holes 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate 32 to the second gate 34 .

4A to 4E are schematic cross-sectional views of a manufacturing method of a power device according to a third embodiment of the present invention.

Referring to FIG. 4A , according to the method for forming the conductive layer 20a described in the first embodiment above, the conductive layer 20a ′ is formed in the trench 16 . However, in this embodiment, the conductive layer 20a' is polysilicon doped with relatively high concentration. In one embodiment, the doping concentration of the conductive layer 20 a ′ ranges from 1E19 1/cm ³ to 5E20 1/cm ³ .

After that, a mask layer 19 is formed on the surface of the edge region of the conductor layer 20a'. The mask layer 19 exposes the surface of the central region of the conductor layer 20a'. The mask layer 19 can be a patterned photoresist layer, which covers the surface and sidewalls of the insulating filling layer 19 and the surface of the edge region of the conductive layer 20a'. The mask layer 19 has an opening exposing the surface of the central region of the conductor layer 20a'. The mask layer 19 can also be a spacer, which only covers the sidewall of the insulating filling layer 19 and the surface of the edge region of the conductor layer 20a'. The material of the spacer can be silicon oxide, silicon nitride or a combination thereof. The method for forming the spacer may firstly form a material layer of the spacer, and then perform an anisotropic etching process.

An ion implantation process IMP 3 is performed on the conductor layer 20a' to form a doped region 20d in the conductor layer 20a'. The doped region 20d and the conductive layer 20a' may have dopants of the same or different conductivity types.

In an embodiment where the doping region 20d has the same conductivity type dopant as the conductive layer 20a', the doping concentration of the doping region 20d is lower than that of the conductive layer 20a'. The dopant region 20d can be implanted into the conductor layer 20a' vertically to the surface of the substrate 10 by using the ion implantation process IMP 3 . The ion implantation process IMP 3 is, for example, implanting dopants of the second conductivity type different from the dopants of the first conductivity type in the conductor layer 20a' into the conductor layer 20a', and the dopants compensate each other, so that the formed The doping concentration of the doped region 20d is lower than that of the conductor layer 20a'. The second conductive dopant is a P-type dopant, such as boron or boron trifluoride. The doping concentration of the doped region 20d ranges from 5E18 1/cm ³ to 1E20 1/cm ³ .

In an embodiment where the dopant region 20d and the conductor layer 20a' have dopants of different conductivity types, the dopant can be implanted in the conductor layer 20a in a manner perpendicular to the surface of the substrate 10 by using the ion implantation process IMP 3 'In order to form the doped region 20d. The ion implantation process IMP 3 is, for example, implanting a second conductivity type dopant different from the first conductivity type dopant of the conductor layer 20a' and having a higher doping concentration than the conductor layer 20a' into the conductor layer 20a', by The dopants compensate each other, so that the conductivity type of the dopant in the formed doped region 20d is different from the conductivity type of the dopant in the conductor layer 20a'. The second conductive dopant is a P-type dopant, such as boron or boron trifluoride. The doped region 20 d has a dopant concentration range of conductivity type, for example, 5E19 1/cm ³ to 8E20 1/cm ³ .

Referring to FIG. 4B , the mask layer 19 is removed. The mask layer 19 can be removed by ashing or etching. Afterwards, according to the method described in the above-mentioned first embodiment, the conductive layer 20c is formed on the doped region 20d and the conductive layer 20a'. In this embodiment, the conductive layer 20a', the doped region 20d and the conductive layer 20c may be collectively referred to as a source polysilicon layer or an isolation field plate PL.

The isolation field plate PL may include a first part P1, a second part P2 and a third part P3. The doping concentration of the first portion P1 is greater than that of the second portion P2 and greater than that of the third portion P3. The first part P1 comprises the conductor layer 20a'; the second part P2 comprises the doped region 20d; the third part comprises the conductor layer 20c. The sidewall and the bottom of the second part P2 are surrounded by the first part P1, and the third part P3 covers the top surfaces of the first part P1 and the second part P2.

Afterwards, referring to FIG. 4C , according to the method described in the first embodiment above, the insulating filling layer 18 is etched back to leave the insulating filling layer 18a in the trench 16, and an insulating filling layer 18a is formed on the insulating filling layer 18a. The first gate trench 22 and the second gate trench 24 . The height of the bottom surface of the first gate trench 22 and the second gate trench 24 is lower than the top surface of the conductive layer 20a', so that the sidewalls of the first gate trench 22 and the second gate trench 24 are exposed The conductor layer 20c and part of the conductor layer 20a' are exposed.

Thereafter, referring to FIG. 4D , according to the method described in the above-mentioned first embodiment, a dielectric layer is formed on the epitaxial layer 14 and the conductor layer 20c and in the first gate trench 22 and the second gate trench 24 30. Since the doping concentration of the conductive layer 20a' is greater than that of the conductive layer 20c, the conductive layer 20a' is easier to oxidize than the conductive layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20a' is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20c. The doping of the doped region 20d is less likely to be oxidized than the conductor layer 20a'. Therefore, the isolation field plate PL can maintain a sufficient width to avoid the influence of too high a resistance value caused by excessive oxidation of the conductor layer 20a'. Characteristics of power components. In addition, it can also ensure that the dielectric layers on the left and right sides will not be connected to each other due to excessive oxidation of the conductor layer 20a'. If the dielectric layers (oxidized layers) 30 on the left and right sides are connected, it will cause disconnection of the isolation field plate PL.

Afterwards, referring to FIG. 4E , the subsequent processes are performed according to the method described in the above-mentioned first embodiment until the first contact holes 72 and the second contact holes 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate 32 to the second gate 34 .

5A to 5D are schematic cross-sectional views of a manufacturing method of a power device according to a fourth embodiment of the present invention.

Please refer to FIG. 5A , according to the method for forming the conductive layer 20a described in the above-mentioned first embodiment, the conductive layer 20a' is formed in the trench 16, but in this embodiment, the conductive layer 20a' is doped with a relatively high concentration. of polysilicon. In one embodiment, the doping concentration of the conductive layer 20 a ′ ranges from 5E19 1/cm ³ to 8E20 1/cm ³ .

After that, according to the method described in the first embodiment above, the conductor layer 20c is formed on the conductor layer 20a'. The conductive layer 20c and the conductive layer 20a' have the same conductivity type dopant, for example, the first conductivity type dopant. The doping concentration of the conductor layer 20c is lower than that of the conductor layer 20a'. The formation method of the conductor layer 20c is, for example, to perform a chemical vapor deposition process in situ after forming the conductor layer 20a', but reduce the concentration of the doping gas to form a gas with a concentration lower than that of the conductor layer 20a' on the conductor layer 20a'. conductor layer 20c. The doping concentration of the conductor layer 20c is, for example, 2/3 to 1/2 of the doping concentration of the conductor layer 20a'.

In this embodiment, the conductive layer 20a' and the conductive layer 20c may be collectively referred to as a source polysilicon layer or an isolation field plate PL. The conductor layer 20a' is to isolate the first part P1 of the field plate PL; the conductor layer 20c is to isolate the second part P2 of the field plate PL. The doping concentration of the first portion P1 is greater than the doping concentration of the second portion P2. The second part P2 covers the top surface of the first part P1.

Please refer to FIG. 5B. According to the method described in the first embodiment above, the insulating filling layer 18 is etched back to leave the insulating filling layer 18a in the trench 16, and the first insulating filling layer 18a is formed on the insulating filling layer 18a. The gate trench 22 and the second gate trench 24 . The height of the bottom surface of the first gate trench 22 and the second gate trench 24 is lower than the top surface of the conductive layer 20a', so that the sidewalls of the first gate trench 22 and the second gate trench 24 are exposed The conductor layer 20c and part of the conductor layer 20a' are exposed.

Referring to FIG. 5C , according to the method described in the first embodiment above, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductor layer 20 c and in the first gate trench 22 and the second gate trench 24 . Since the doping concentration of the conductive layer 20a' is greater than that of the conductive layer 20c, the conductive layer 20a' is easier to oxidize than the conductive layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20a' is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20c.

Afterwards, referring to FIG. 5D , the subsequent processes are performed according to the method described in the above-mentioned first embodiment until the first contact holes 72 and the second contact holes 74 are formed. Thereafter, a subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate 32 to the second gate 34 .

The above Figure 1J, Figure 3E, Figure 4E, and Figure 5D respectively depict a unit of the SGT MOSFET. However, the present invention is not limited thereto. In some embodiments, the SGT MOSFET may have two cells, C1 and C1', as shown in FIG. 6 . In FIG. 6 , the unit in FIG. 1J is taken as an example for illustration, but the present invention is not limited thereto. The element symbols of similar or identical components in unit C1' and C1 are represented by the same numbers, and "'" and "'" are added after the numbers. For example, the second doped region 64' is similar to the second doped region 64, both of which are dopants of the second conductivity type.

The cells C1 and C1' are adjacent to each other, and the first base region 36 and the first doped region 62 are shared by the cells C1 and C1'. In addition, the first doped region 62, the second doped region 64 and the second doped region 64' are electrically connected to each other through the first contact window 72 and the second contact windows 74, 74'. The first gate 32 and the second gate 34 of the cell C1 and the first gate 32' and the second gate 34' of the cell C1' may be electrically connected to each other.

In other embodiments, the SGT MOSFET can have more cells, and these cells can be arranged in an array. In other words, an SGT MOSFET can have multiple gates, multiple source doped regions, and multiple drain doped regions. These multiple gates, multiple sources and multiple drains can be arranged in an array respectively, and these multiple gates, multiple source doped regions and multiple drain doped regions can be respectively passed through the inner Wired together to form a gate terminal, a source terminal and a drain terminal

In summary, the present invention exposes the isolation field plate with high doping concentration on the lower sidewall of the gate trench, therefore, a thick oxide layer can be formed at the bottom corner of the gate trench, so that the gate can be reduced. The leakage current between the source and the source increases the breakdown voltage of the component. Under the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (gate charge, QG), and improve the quality factor (figure of merit, FOM), Improve component performance.

Claims (10)

1. A power element, characterized in that, comprising: an epitaxial layer having a trench extending from a first surface of the epitaxial layer to a second surface; a drain doped layer on the second surface of the epitaxial layer; a first body region and a second body region, located in the epitaxial layer on both sides of the trench; A first doped source region and a second doped source region are respectively located in the first body region and the second body region; an isolation field plate located in the trench; an insulating filling layer, located in the trench, surrounding the sidewall and bottom of the lower portion of the isolation field plate; A first gate and a second gate are located in the trench and on the insulating filling layer, wherein the first gate is located between the isolation field plate and the first base region, and the first gate is located between the isolation field plate and the first base region. a second gate is located between the isolation field plate and the second body region; and a dielectric layer surrounding sidewalls of the first gate and the second gate, wherein a lower portion of the dielectric layer has a maximum width of the dielectric layer, and Wherein the isolation field plate includes a first portion and a second portion, the first portion is adjacent to the lower portion of the dielectric layer, and its doping concentration is greater than that of the second portion. 2. The power device according to claim 1, wherein the first portion is a doped layer sandwiched in the second portion. 3. The power device of claim 1, wherein the first portion comprises two disconnected doped regions separated by the second portion. 4. The power device according to claim 1, wherein the isolation field plate further comprises a third portion, the doping concentration of which is lower than that of the first portion and covers the gap between the first portion and the second portion The top surface, and the sidewall and bottom of the second part are surrounded by the first part. 5. The power device according to claim 1, wherein the second portion is located on the first portion and covers a top surface of the first portion. 6. The power device according to claim 1, wherein a bottom surface of the first portion is higher than a bottom surface of the dielectric layer. 7. The power device of claim 1, wherein a top surface of the first portion is higher than a bottom surface of the dielectric layer. 8. The power device according to claim 1, wherein the maximum width of the dielectric layer is greater than an average width of the dielectric layer. 9. The power device of claim 1, wherein the isolation field plate has a minimum width of the dielectric layer at a location corresponding to the lower portion of the dielectric layer. 10. The power device according to claim 9, wherein the ratio of the minimum width of the dielectric layer to the average width of the dielectric layer is greater than 0.8.

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