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CN113809083A - 静态随机存取存储器及其制作方法 - Google Patents

静态随机存取存储器及其制作方法 Download PDF

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CN113809083A
CN113809083A CN202010529866.7A CN202010529866A CN113809083A CN 113809083 A CN113809083 A CN 113809083A CN 202010529866 A CN202010529866 A CN 202010529866A CN 113809083 A CN113809083 A CN 113809083A
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layer
contact plug
barrier layer
metal
forming
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CN113809083B (zh
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洪庆文
林俊贤
陈建宏
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US16/923,117 priority patent/US11538813B2/en
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Priority to US17/991,765 priority patent/US20230090612A1/en
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Abstract

本发明公开一种静态随机存取存储器及其制作方法，其中制作静态随机存取存储器的方法为，首先形成一栅极结构于基底上，然后形成一外延层于栅极结构旁，形成一第一层间介电层环绕栅极结构，将该栅极结构转换为金属栅极，形成一接触洞暴露该外延层，形成一阻障层于接触洞内，形成一金属层于阻障层上，再平坦化金属层及阻障层以形成一接触插塞，其中阻障层底部包含一富钛部分且阻障层顶部包含一富氮部分。

Description

静态随机存取存储器及其制作方法
技术领域
本发明涉及一种静态随机存取存储器(static randomaccess memory,SRAM)，尤其是涉及一种具有梯度(gradient)浓度阻障层的接触插塞的SRAM。
背景技术
在一嵌入式静态随机存取存储器(embedded static random access memory,embedded SRAM)中，包含有逻辑电路(logic circuit)和与逻辑电路连接的静态随机存取存储器。静态随机存取存储器本身属于一种挥发性(volatile)的存储单元(memory cell)，亦即当供给静态随机存取存储器的电力消失之后，所存储的数据会同时抹除。静态随机存取存储器存储数据的方式是利用存储单元内晶体管的导电状态来达成，静态随机存取存储器的设计是采用互耦合晶体管为基础，没有电容器放电的问题，不需要不断充电以保持数据不流失，也就是不需作存储器更新的动作，这与同属挥发性存储器的动态随机存取存储器(Dynamic Random Access Memory,DRAM)利用电容器带电状态存储数据的方式并不相同。静态随机存取存储器的存取速度相当快，因此有在计算机系统中当作快取存储器(cache memory)等的应用。
然而随着制作工艺线宽与曝光间距的缩减，现今SRAM元件的制作难以利用现有的架构曝出所要的图案。因此如何改良现有SRAM元件的架构来提升曝光的品质即为现今一重要课题。
发明内容
本发明一实施例揭露一种制作静态随机存取存储器的方法。首先形成一栅极结构于基底上，然后形成一外延层于栅极结构旁，形成一第一层间介电层环绕栅极结构，将该栅极结构转换为金属栅极，形成一接触洞暴露该外延层，形成一阻障层于接触洞内，形成一金属层于阻障层上，再平坦化金属层及阻障层以形成一接触插塞，其中阻障层底部包含一富钛部分且阻障层顶部包含一富氮部分。
本发明另一实施例揭露一种静态随机存取存储器，其主要包含栅极结构设于基底上、外延层设于栅极结构旁、第一接触插塞设于该外延层上、第二接触插塞设于该栅极结构上、第一层间介电层环绕该第一接触插塞、该第二接触插塞以及该栅极结构、第三接触插塞设于该第一接触插塞上、第四接触插塞设于该第二接触插塞上以及第二层间介电层环绕该第三接触插塞以及该第四接触插塞。
附图说明
图1为本发明优选实施例的一静态随机存取存储器的布局图；
图2为本发明静态随机存取存储器中一组六晶体管静态随机存取存储器(6T-SRAM)存储单元的电路图；
图3至图6为本发明一实施例制作6T-SRAM存储单元的方法示意图。
主要元件符号说明
PL1:第一上拉晶体管
PL2:第二上拉晶体管
PD1:第一下拉晶体管
PD2:第二下拉晶体管
PG1:第一存取晶体管
PG2:第二存取晶体管
WL:字符线
BL:位线
Vcc:电压源
Vss:电压源
10:六晶体管静态随机存取存储器
24:存储节点
26:存储节点
28:串接电路
30:串接电路
52:基底
54:鳍状结构
56:浅沟隔离
58:栅极结构
60:栅极结构
62:栅极介电层
64:栅极材料层
66:硬掩模
68:间隙壁
70:源极/漏极区域
72:外延层
74:接触洞蚀刻停止层
76:层间介电层
78:介质层
80:高介电常数介电层
82:功函数金属层
84:低阻抗金属层
86:金属栅极
88:硬掩模
90:接触插塞
92:第一阻障层
94:第二阻障层
96:金属硅化物
98:金属层
100:第一层
102:第二层
104:停止层
106:层间介电层
108:接触插塞
110:接触插塞
112:金属间介电层
114:金属内连线
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所揭露的范围，在此容先叙明。
请参照图1与图2，图1为本发明优选实施例的一静态随机存取存储器的布局图，图2为本发明静态随机存取存储器中一组六晶体管静态随机存取存储器(six-transistorSRAM,6T-SRAM)存储单元的电路图。如图1与图2所示，本发明的静态随机存取存储器较佳包含至少一组静态随机存取存储器单元，其中每一静态随机存取存储器单元包含一六晶体管静态随机存取存储单元(6T-SRAM)10。
在本实施例中，各6T-SRAM存储单元10较佳由一第一上拉晶体管(Pull-Uptransistor)PL1、一第二上拉晶体管PL2、一第一下拉晶体管(Pull-Down transistor)PD1、一第二下拉晶体管PD2、一第一存取晶体管(Access transistor)PG1和一第二存取晶体管PG2构成正反器(flip-flop)，其中第一上拉晶体管PL1和第二上拉晶体管PL2、第一下拉晶体管PD1和第二下拉晶体管PD2构成栓锁电路(latch)，使数据可以栓锁在存储节点(Storage Node)24或26。另外，第一上拉晶体管PL1和第二上拉晶体管PL2是作为主动负载之用，其也可以一般的电阻来取代作为上拉元件，在此情况下即为四晶体管静态随机存取存储器(four-transistor SRAM,4T-SRAM)。另外在本实施例中，第一上拉晶体管PL1和第二上拉晶体管PL2各自的一源极区域电连接至一电压源Vcc，第一下拉晶体管PD1和第二下拉晶体管PD2各自的一源极区域电连接至一电压源Vss。
一般而言，6T-SRAM存储单元10的第一上拉晶体管PL1、第二上拉晶体管PL2是由P型金属氧化物半导体(P-type metal oxide semiconductor,PMOS)晶体管所组成，而第一下拉晶体管PD1、第二下拉晶体管PD2和第一存取晶体管PG1、第二存取晶体管PG2则是由N型金属氧化物半导体(N-type metal oxide semiconductor,NMOS)晶体管所组成。其中，第一上拉晶体管PL1和第一下拉晶体管PD1一同构成一反向器(inverter)，且这两者所构成的串接电路28其两端点分别耦接于一电压源Vcc与一电压源Vss；同样地，第二上拉晶体管PL2与第二下拉晶体管PD2构成另一反向器，而这两者所构成的串接电路30其两端点也分别耦接于电压源Vcc与电压源Vss。
此外，在存储节点24处，分别电连接有第二下拉晶体管PD2和第二上拉晶体管PL2的栅极、及第一下拉晶体管PD1、第一上拉晶体管PL1和第一存取晶体管PG1的漏极；同样地，在存储节点26上，也分别电连接有第一下拉晶体管PD1和第一上拉晶体管PL1的栅极、及第二下拉晶体管PD2、第二上拉晶体管PL2和第二存取晶体管PG2的漏极。至于第一存取晶体管PG1和第二存取晶体管PG2的栅极则分别耦接至字符线(Word Line)WL，而第一存取晶体管PG1和第二存取晶体管PG2的源极则分别耦接至相对应的位线(Bit Line)BL。
请参照图3至图6，图3至图6为本发明一实施例制作6T-SRAM存储单元10的方法示意图。如图3所示，首先提供一基底52，例如一硅基底或硅覆绝缘(SOI)基板。基底52上具有至少一鳍状结构54及一绝缘层(图未示)，其中鳍状结构54的底部被绝缘层，例如氧化硅所包覆而形成浅沟隔离56。需注意的是，本实施例虽以制作鳍状结构场效晶体管为例，但不局限于此，本发明又可应用至一般平面型场效晶体管，此实施例也属本发明所涵盖的范围。
依据本发明的优选实施例，鳍状结构54较佳通过侧壁图案转移(sidewall imagetransfer,SIT)技术制得，其程序大致包括：提供一布局图案至计算机系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割(fin cut)制作工艺而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构54的形成方式又可包含先形成一图案化掩模(图未示)于基底52上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底52中以形成鳍状结构54。另外，鳍状结构54的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底52上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底52上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构54。这些形成鳍状结构54的实施例均属本发明所涵盖的范围。
接着可于基底52上形成栅极结构58、60或虚置栅极。在本实施例中，形成栅极结构58、60的方式较佳依序形成一栅极介电层62、一栅极材料层64以及一选择性硬掩模66于基底52上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模66、部分栅极材料层64以及部分栅极介电层62，然后剥除图案化光致抗蚀剂，以于鳍状结构54上形成至少一由图案化的栅极介电层62、图案化的栅极材料层64以及图案化的硬掩模66所构成的虚置栅极或栅极结构58、60。在本实施例中，栅极介电层62可包含氧化硅而栅极材料层64可包含多晶硅，但不局限于此。
然后在各栅极结构58、60侧壁形成至少一间隙壁68，并于间隙壁68两侧的鳍状结构54以及/或基底52中形成一源极/漏极区域70以及外延层72。在本实施例中，间隙壁68可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁(图未示)以及一主间隙壁(图未示)，且间隙壁68可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。源极/漏极区域70及外延层72可依据所置备晶体管的导电型式而包含不同掺质或不同材料。例如源极/漏极区域70可包含P型掺质或N型掺质，而外延层72则可包含锗化硅、碳化硅或磷化硅。
然后可选择性形成一由氮化硅所构成的接触洞蚀刻停止层(contact etch stoplayer,CESL)74于基底52上并覆盖栅极结构58、60，再形成一层间介电层76于接触洞蚀刻停止层74上。接着进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanicalpolishing,CMP)去除部分层间介电层76及部分接触洞蚀刻停止层74并暴露出硬掩模66，使硬掩模66上表面与层间介电层76上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构58、60转换为金属栅极。例如图4所示，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构58、60中的硬掩模66、栅极材料层64以及栅极介电层62，以于层间介电层76中形成凹槽(图未示)。
之后依序形成一介质层78、一高介电常数介电层80、一选择性底部金属阻隔层(bottom barrier metal,BBM)、一功函数金属层82以及一低阻抗金属层84于各凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层84、部分功函数金属层82以及部分高介电常数介电层80以形成金属栅极86。
在本实施例中，高介电常数介电层80包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。底部金属阻隔层可选自由氮化钛(TiN)以及氮化钽(TaN)所构成的群组，但不局限于此。
功函数金属层82较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层82可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层82可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层82与低阻抗金属层84之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层84则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
之后可选择性去除部分高介电常数介电层80、部分底部金属阻隔层82以及部分低阻抗金属层84形成凹槽(图未示)，然后再填入一硬掩模88于凹槽内并使硬掩模88与层间介电层76顶部齐平，其中硬掩模88可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
随后可进行一接触插塞制作工艺形成接触插塞90分别电连接源极/漏极区域70以及栅极结构60。在本实施例中，形成接触插塞90的方式可先去除部分栅极结构60两侧的层间介电层76与部分接触洞蚀刻停止层74以及栅极结构60正上方的部分甚至所有硬掩模88形成接触洞(图未示)，其中栅极结构60两侧的接触洞较佳暴露出外延层72而栅极结构60正上方的接触洞则暴露出金属栅极86。
然后依序沉积一第一阻障层92与第二阻障层94于各接触洞中，其中第一阻障层92与第二阻障层94较佳共形地(conformally)形成于基底52表面及接触洞的内侧侧壁。在本实施例中，第一阻障层92较佳选自钛、钴、镍及铂等所构成的群组，且最佳为钛，第二阻障层94则较佳包含氮化钛、氮化钽等金属化合物。
在连续沉积第一阻障层92与第二阻障层94之后，依序进行一第一热处理制作工艺与一第二热处理制作工艺以形成一金属硅化物96于外延层72表面。在本实施例中，第一热处理制作工艺包含一常温退火(soak anneal)制作工艺，其温度较佳介于500℃至600℃，且最佳为550℃，而其处理时间则较佳介于10秒至60秒，且最佳为30秒。第二热处理制作工艺包含一峰值退火(spike anneal)制作工艺，其温度较佳介于600℃至950℃，且最佳为600℃，而其处理较佳时间则较佳介于100毫秒至5秒，且最佳为5秒。
进行两次热处理制作工艺后，形成一金属层98并填满接触洞。在本实施例中，金属层98较佳包含钨，但不局限于此。最后进行一平坦化制作工艺，例如以CMP制作工艺部分去除第三金属层98、部分第二金属层94及部分第一金属层92，甚至可视制作工艺需求接着去除部分层间介电层76，以形成接触插塞90电连接外延层30以及栅极结构60。
值得注意的是，本实施例所形成的第二阻障层94较佳包含氮化钛，且形成第二阻障层94时较佳以交替进行沉积制作工艺以及处理制作工艺的方式来形成具有渐层氮化钛浓度的第二阻障层94。请同时参照图5，图5揭露本发明一实施例形成第二阻障层的方法示意图。如图5所示，形成第二阻障层94的步骤主要先进行第一沉积制作工艺以形成一第一层100于各接触洞内，进行第一处理制作工艺于第一层100上，进行第二沉积制作工艺以形成一第二层102于第一层100上，再进行第二处理制作工艺于第二层102上，其中第一沉积制作工艺以及第二沉积制作工艺均包含氮化钛的沉积，第一处理制作工艺以及第二处理制作工艺均可包含通入氢气以及/或氮气，但第二处理制作工艺通入氮气的时间较佳大于第一处理制作工艺通入氮气的时间。
换句话说，经由延长第二处里制作工艺中通入氮气的时间本发明较佳使第二阻障层94中第一层100的氮浓度低于第二层102的氮浓度且第二层102的钛浓度低于第一层100的钛浓度，或从另一角度来看靠近基底52的第二阻障层94具有较高钛浓度以及较低氮浓度而远离基底52的第二阻障层94则具有较低钛浓度以及较高氮浓度，其中靠近基底52具有较高钛浓度的部分可助长金属硅化物96的形成而远离基底52或靠近金属层98的部分则可用来作为金属阻隔。另外由于靠近基底52具有较高的氮浓度可能使阻障层以及金属层98在接触洞侧壁上附着力不佳造成金属流失并影响元件表现，因此本发明较佳通过上述手段来调整氮原子于第二阻障层94中的浓度以改善此问题。另外本实施例虽以交替进行两次沉积制作工艺以及两次处理制作工艺为例，但沉积制作工艺与处理制作工艺的次数以及所形成构成第二阻障层94的氮化钛层数量均可视制作工艺需求调整而不局限于此。
随后如图6所示，依序形成一停止层104以及另一层间介电层106于层间介电层76上，进行一道或一道以上光刻暨蚀刻制作工艺去除部分层间介电层106、部分停止层104以及栅极结构58正上方的硬掩模88形成接触洞(图未示)。接着填入导电材料于各接触洞内并搭配平坦化制作工艺如CMP以形成金属内连线或接触插塞108、110连接下方的接触插塞90，其中接触插塞108较佳同时连接或直接接触栅极结构58以及栅极结构58、60间的接触插塞90，而接触插塞110则接触下层栅极结构60正上方的接触插塞90。接着再形成一金属间介电层112于层间介电层106上，进行一道或一道以上光刻暨蚀刻制作工艺去除部分金属间介电层112、部分层间介电层106以及部分停止层104形成接触洞，再填入导电材料于接触洞内并搭配平坦化制作工艺如CMP以形成金属内连线114或接触插塞接触栅极结构60旁的接触插塞90。
在本实施例中，停止层104可选自由氮掺杂碳化物层(nitrogen doped carbide,NDC)、氮化硅、以及氮碳化硅(silicon carbon nitride,SiCN)所构成的群组。如同前述所形成的接触插塞90，设于层间介电层106以及金属间介电层112内的各金属内连线114或接触插塞108、110均可依据单镶嵌制作工艺或双镶嵌制作工艺镶嵌于层间介电层106以及/或金属间介电层112内。例如各接触插塞108、110及金属内连线114可更细部包含一阻障层以及一金属层，其中阻障层可选自由钛(Ti)、氮化钛(TiN)、钽(Ta)以及氮化钽(TaN)所构成的群组，而金属层可选自由钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等所构成的群组，但不局限于此。由于单镶嵌或双镶嵌制作工艺是本领域所熟知技术，在此不另加赘述。至此即完成本发明一实施例的半导体元件的制作。
综上所述，本发明主要于SRAM元件的接触插塞制作工艺时以交替进行多次沉积及多次处理的方式来形成具有梯度(gradient)浓度的氮化钛阻障层，其中阻障层底部包含一富钛部分而阻障层顶部则包含一富氮部分，依据前述实施例靠近基底具有较高钛浓度的部分可助长金属硅化物的形成而远离基底或靠近例如金属层98的部分则可用来作为金属阻隔。由于现行制作工艺中靠近基底52具有较高的氮浓度可能使阻障层以及金属层98在接触洞侧壁上附着力不佳造成金属流失并影响元件表现，因此本发明较佳通过上述手段来调整氮原子于第二阻障层94中的浓度以改善此问题。
此外本发明另一实施例较佳将原本贯穿两层层间介电层76、106并连接栅极结构60的接触插塞(或可称M0PY接触插塞)分隔为两部分，其中位于下层层间介电层76内以及栅极结构60正上方的接触插塞90顶部较佳切齐相邻两侧连接源极/漏极区域70以及外延层72的接触插塞90顶部，而位于上层层间介电层106中以及位于栅极结构60正上方的接触插塞110顶部则切齐相邻连接下层接触插塞90以及栅极结构58的接触插塞108。通过将M0PY接触插塞分隔为上下两段本发明可于制作工艺线宽与曝光间距缩减的情况下大幅降低接触插塞之间连结的高度以及元件间发生短路的机会。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种制作静态随机存取存储器的方法，其特征在于，包含：
形成栅极结构于基底上；
形成外延层于该栅极结构旁；
形成第一层间介电层环绕该栅极结构；
将该栅极结构转换为金属栅极；
形成第一接触洞暴露该外延层；以及
形成第一阻障层于该第一接触洞内，其中该第一阻障层底部包含富钛部分且该第一阻障层顶部包含富氮部分。
2.如权利要求1所述的方法，另包含：
形成该第一接触洞暴露该外延层以及第二接触洞暴露该金属栅极；
形成该第一阻障层于该第一接触洞以及该第二接触洞；
形成金属层于该第一阻障层上；
平坦化该金属层以及该第一阻障层以形成第一接触插塞以及第二接触插塞；
形成第二层间介电层于该第一层间介电层上；以及
形成第三接触插塞于该第一接触插塞上以及第四接触插塞于该第二接触插塞上。
3.如权利要求1所述的方法，另包含于形成该金属层后进行退火制作工艺以形成金属硅化物。
4.如权利要求1所述的方法，其中形成该第一阻障层的步骤另包含：
进行第一沉积制作工艺以形成第一层于该第一接触洞内；
进行第一处理制作工艺于该第一层上；
进行第二沉积制作工艺以形成第二层于该第一层上；以及
进行第二处理制作工艺于该第二层上。
5.如权利要求4所述的方法，其中该第一层的氮浓度低于该第二层的氮浓度。
6.如权利要求4所述的方法，其中该第二层的钛浓度低于该第一层的钛浓度。
7.如权利要求4所述的方法，其中该第一处理制作工艺包含氢气以及氮气。
8.如权利要求4所述的方法，其中该第二处理制作工艺包含氢气以及氮气。
9.如权利要求4所述的方法，其中该第二处理制作工艺时间大于该第一处理制作工艺时间。
10.如权利要求1所述的方法，另包含于形成该第一阻障层之前形成第二阻障层于该第一接触洞内。
11.如权利要求10所述的方法，其中该第一阻障层包含氮化钛且该第二阻障层包含钛。
12.一种静态随机存取存储器，其特征在于，包含：
栅极结构，设于基底上；
外延层，设于该栅极结构旁；
第一接触插塞，设于该外延层上；
第二接触插塞，设于该栅极结构上；
第一层间介电层，环绕该第一接触插塞、该第二接触插塞以及该栅极结构；
第三接触插塞，设于该第一接触插塞上；
第四接触插塞，设于该第二接触插塞上；以及
第二层间介电层，环绕该第三接触插塞以及该第四接触插塞。
13.如权利要求12所述的静态随机存取存储器，其中该第一接触插塞顶部切齐该第二接触插塞顶部。
14.如权利要求12所述的静态随机存取存储器，其中该第三接触插塞顶部切齐该第四接触插塞顶部。
15.如权利要求12所述的静态随机存取存储器，另包含金属硅化物，设于该外延层以及该第一接触插塞之间。
16.如权利要求12所述的静态随机存取存储器，其中各该第一接触插塞以及该第二接触插塞包含：
第一阻障层；
第二阻障层，设于该第一阻障层上；以及
金属层，设于该第二阻障层上。
17.如权利要求16所述的静态随机存取存储器，其中该第一阻障层包含钛且该第二阻障层包含氮化钛。
18.如权利要求16所述的静态随机存取存储器，其中该第二阻障层底部包含富钛部分且该第二阻障层顶部包含富氮部分。
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Publication number Priority date Publication date Assignee Title
CN114242688B (zh) * 2020-09-09 2025-03-25 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US20230282750A1 (en) * 2022-03-04 2023-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric Layers for Semiconductor Devices and Methods of Forming the Same

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317187A (en) * 1992-05-05 1994-05-31 Zilog, Inc. Ti/TiN/Ti contact metallization
CN1458679A (zh) * 2002-05-15 2003-11-26 旺宏电子股份有限公司 制造接触插塞的方法
US20070090427A1 (en) * 2005-10-25 2007-04-26 Kazuaki Nakajima Semiconductor device and method of manufacturing same
US20070099414A1 (en) * 2005-10-31 2007-05-03 Kai Frohberg Semiconductor device comprising a contact structure based on copper and tungsten
US20080277736A1 (en) * 2007-05-08 2008-11-13 Kazuaki Nakajima Semiconductor device and method of manufacturing the same
US20120049288A1 (en) * 2010-08-25 2012-03-01 Renesas Electronics Corporation Semiconductor integrated circuit device and manufacturing method thereof
US20150061041A1 (en) * 2013-09-03 2015-03-05 United Microelectronics Corp. Semiconductor structure and method of forming the same
CN106409889A (zh) * 2015-08-03 2017-02-15 联华电子股份有限公司 半导体元件
US9966309B2 (en) * 2014-03-14 2018-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plug without seam hole and methods of forming the same
US20190103311A1 (en) * 2017-04-28 2019-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Gates of Transistors Having Reduced Resistivity
CN109728078A (zh) * 2017-10-30 2019-05-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040069665A (ko) 2003-01-30 2004-08-06 주식회사 하이닉스반도체 에스램 셀 및 그의 제조방법
JP2008311457A (ja) * 2007-06-15 2008-12-25 Renesas Technology Corp 半導体装置の製造方法
US8258572B2 (en) 2009-12-07 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM structure with FinFETs having multiple fins
US10297602B2 (en) * 2017-05-18 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Implantations for forming source/drain regions of different transistors
US10998421B2 (en) * 2018-07-16 2021-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing pattern loading in the etch-back of metal gate

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317187A (en) * 1992-05-05 1994-05-31 Zilog, Inc. Ti/TiN/Ti contact metallization
CN1458679A (zh) * 2002-05-15 2003-11-26 旺宏电子股份有限公司 制造接触插塞的方法
US20070090427A1 (en) * 2005-10-25 2007-04-26 Kazuaki Nakajima Semiconductor device and method of manufacturing same
US20070099414A1 (en) * 2005-10-31 2007-05-03 Kai Frohberg Semiconductor device comprising a contact structure based on copper and tungsten
US20080277736A1 (en) * 2007-05-08 2008-11-13 Kazuaki Nakajima Semiconductor device and method of manufacturing the same
US20120049288A1 (en) * 2010-08-25 2012-03-01 Renesas Electronics Corporation Semiconductor integrated circuit device and manufacturing method thereof
US20150061041A1 (en) * 2013-09-03 2015-03-05 United Microelectronics Corp. Semiconductor structure and method of forming the same
US9966309B2 (en) * 2014-03-14 2018-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plug without seam hole and methods of forming the same
CN106409889A (zh) * 2015-08-03 2017-02-15 联华电子股份有限公司 半导体元件
US20190103311A1 (en) * 2017-04-28 2019-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Gates of Transistors Having Reduced Resistivity
CN109728078A (zh) * 2017-10-30 2019-05-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

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