CN113808516B - Driving circuit - Google Patents

Abstract

The invention discloses a driving circuit, which includes a pixel driving circuit, a gate node driving circuit, a driving capacitor, a control node driving circuit and a multiplexer circuit. The pixel driving circuit includes a driving transistor, the driving transistor is coupled to the light-emitting element, and the control terminal of the driving transistor is coupled to the gate node. The gate node driving circuit is coupled to the gate node and pulls down the voltage of the gate node. The driving capacitor is arranged between the gate node and the control node. The control node driving circuit is coupled to the control node and pulls up the voltage of the control node. The multiplexer circuit includes a data transistor and a data line capacitor. The first terminal of the data transistor is coupled to the control node, and the second terminal of the data transistor is coupled to the data line capacitor.

Description

Drive circuit

Technical field

The present invention relates to a driving circuit, and in particular to a driving circuit that is provided with a gate node driving circuit and a control node driving circuit so that the node charging process will not be affected by the sequence of the multiplexer circuit.

Background technique

Using multiplexers to reduce peripheral circuit space has become a common design trend for various display devices. By controlling differences in signal timing, data voltages can be input to pixels at different time points. Existing multiplexer circuits are among multiplexer circuits in different sequences. Because the gate node is turned on by the multiplexer signal, the voltage of the node is restored by the connection method of the multiplexer circuit. When the multiplexer circuit is turned on, Sequentially, the last one turned on does not have enough time to pull the voltage back to the preset standard, resulting in insufficient compensation of the voltage difference that will cause uneven brightness or color shift in the pixels.

On the other hand, in the reset operating state, the circuit resets the control node to the highest value of the data voltage and resets the gate node to the reference voltage, so that subsequent compensation and data writing functions can be executed normally, but such The operation causes a leakage path from the high voltage source to the reference voltage source, causing the brightness of the screen to be pulled and causing flickering problems.

In summary, the existing driving circuits still have considerable defects in circuit design. Therefore, the present invention solves the problems of the existing technologies by designing a driving circuit to improve the deficiencies of the existing technologies. Promote implementation and utilization in industry.

Contents of the invention

In view of the above-mentioned problems of the prior art, the object of the present invention is to provide a driving circuit to solve the problems of insufficient gate node pull-back time and leakage paths.

According to the above object, embodiments of the present invention provide a driving circuit, which includes a pixel driving circuit, a gate node driving circuit, a driving capacitor, a control node driving circuit and a multiplexer circuit. The pixel driving circuit includes a driving transistor, a first terminal of the driving transistor is coupled to a high voltage source, a second terminal of the driving transistor is coupled to the light-emitting element, and a control terminal of the driving transistor is coupled to the gate node. The gate node driving circuit is coupled to the gate node and pulls down the voltage of the gate node. One end of the driving capacitor is coupled to the gate node, and the other end is coupled to the control node. The control node driving circuit is coupled to the control node and pulls up the voltage of the control node. The multiplexer circuit includes a data transistor and a data line capacitor. The first terminal of the data transistor is coupled to the control node, and the second terminal of the data transistor is coupled to the data line capacitor.

In embodiments of the present invention, the pixel driving circuit may include a light-emitting transistor. A first terminal of the light-emitting transistor is coupled to a second terminal of the driving transistor. A second terminal of the light-emitting transistor is coupled to the light-emitting element. The control terminal of the light-emitting transistor receives Light-emitting signal to control the light-emitting element to emit light. The gate node driving circuit may include a first transistor, a first terminal of the first transistor is coupled to the first reference voltage, and a second terminal of the first transistor is coupled to the gate node. The control node driving circuit may include a second transistor, a first terminal of the second transistor is coupled to the second reference voltage, and a second terminal of the second transistor is coupled to the control node.

In the embodiment of the present invention, the control terminal of the first transistor receives the first signal of the current stage to pull down the voltage of the gate node, and the control terminal of the second transistor receives an external signal to pull the voltage of the control node. The external signal includes the first signal of the current stage. signal and rear pole luminous signal.

In the embodiment of the present invention, the control terminal of the first transistor receives the first signal of the previous stage to pull down the voltage of the gate node, and the control terminal of the second transistor receives an external signal to pull the voltage of the control node. The external signal includes the first signal of the previous stage. signal, the first signal of the current level and the luminous signal.

In an embodiment of the present invention, the control node driving circuit may further include a third transistor. A first terminal of the third transistor is coupled to the second reference voltage and a first terminal of the second transistor. A second terminal of the third transistor is coupled to the second reference voltage. Connected to the control node and the second terminal of the second transistor.

In an embodiment of the present invention, the control terminal of the first transistor receives the first signal of the current stage to pull down the voltage of the gate node, the control terminal of the second transistor receives the first signal of the current stage, and the control terminal of the third transistor receives the light-emitting signal. to pull up the control node voltage.

In an embodiment of the present invention, the control node driving circuit may further include a third transistor. A first terminal of the third transistor is coupled to the second reference voltage and a first terminal of the second transistor. A second terminal of the third transistor is coupled to the second reference voltage. Connected to the control node and the second terminal of the second transistor, the gate node driving circuit may further include a fourth transistor, a first terminal of the fourth transistor is coupled to the first reference voltage, and a second terminal of the fourth transistor is coupled to the first terminal of the first transistor.

In the embodiment of the present invention, the control terminal of the first transistor receives the first signal of the current stage and the control terminal of the fourth transistor receives the first signal of the previous stage to pull down the voltage of the gate node, and the control terminal of the second transistor receives the first signal of the current stage. The control terminals of the first signal and the third transistor receive the lighting signal to pull up the control node voltage.

In an embodiment of the present invention, the control terminal of the data transistor receives the second signal to control the data transistor. When the data transistor is turned off, the multiplexer circuit stores the data voltage in the data line capacitor. When the data transistor is turned on, the multiplexer circuit stores the data voltage in the data line capacitor. The data voltage is coupled to the control node.

As mentioned above, in the driving circuit of the present invention, the gate node driving circuit and the control node driving circuit are configured so that the precharging operation is performed by the above driving circuit instead of the original multiplexer circuit. The precharge operation and the multiplexer data writing operation are separate and independent operation paths and can be performed at the same time to avoid the problem of insufficient time for the precharge operation that affects the node voltage. In addition, the circuit reset state does not need to be performed when the first signal and the second signal turn on the transistor at the same time, thereby avoiding the generation of a leakage path from the high voltage source to the reference voltage source and preventing the screen of the display device from flickering.

Description of the drawings

In order to make the technical features, content and advantages of the present invention and the effects it can achieve more obvious, the present invention is described in detail as follows in conjunction with the accompanying drawings and in the form of embodiments:

Figure 1 is a schematic diagram of a driving circuit according to an embodiment of the present invention.

FIG. 2A is a schematic circuit diagram of a driving circuit according to the first embodiment of the present invention.

FIG. 2B is a schematic waveform diagram of the driving circuit according to the first embodiment of the present invention.

FIG. 3A is a schematic circuit diagram of a driving circuit according to a second embodiment of the present invention.

FIG. 3B is a schematic waveform diagram of the driving circuit according to the second embodiment of the present invention.

FIG. 4A is a schematic circuit diagram of a driving circuit according to a third embodiment of the present invention.

FIG. 4B is a schematic waveform diagram of a driving circuit according to the third embodiment of the present invention.

FIG. 5A is a schematic circuit diagram of a driving circuit according to the fourth embodiment of the present invention.

FIG. 5B is a schematic waveform diagram of a driving circuit according to the fourth embodiment of the present invention.

Among them, the reference symbols are explained as follows:

10, 20, 30, 40, 50: drive circuit

11, 21, 31, 41, 51: Pixel drive circuit

12, 22, 32, 42, 52: Gate node drive circuit

13, 23, 33, 43, 53: drive capacitor

14, 24, 34, 44, 54: Control node drive circuit

15, 25, 35, 45, 55: multiplexer circuit

Cdata: data line capacitance

E: Light emitting element

EM: luminous signal

EM2,n: external signal

MUX,n: multiplexer signal

N: node

OVDD: high voltage source

OVSS: low voltage source

S: signal line

SW: control line

S1,n: the first signal of the current level

S1,n+1: the first signal of the subsequent stage

S1,n-1: the first signal of the previous stage

S2,n: the second signal of the current level

TD: driver transistor

TE: light emitting transistor

TM: multiplexer transistor

Tdata: data transistor

T1, T2: transistor

T21, T31, T41, T51: first transistor

T22, T32, T42, T52: Second transistor

VG: gate node

VT: control node

Vref N: first reference voltage

Vref P: second reference voltage

Detailed ways

In order to facilitate understanding of the technical features, content, advantages and effects achieved by the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and in the form of embodiments. The drawings used are only for their main purpose. They are for illustration and auxiliary description purposes, and may not represent the true proportions and precise configurations after implementation of the present invention. Therefore, the proportions and configuration relationships of the attached drawings should not be interpreted to limit the scope of rights of the present invention in actual implementation. Description.

In the drawings, the thickness or width of substrates, panels, regions, lines, etc. are exaggerated for clarity. Throughout this specification, the same reference numbers refer to the same elements. It will be understood that when an element such as a substrate, panel, region or circuit is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to physical and/or electrical connection. Furthermore, "electrical connection", "coupling" or "coupling" may mean the presence of other components between two components. Additionally, it will be understood that, although the terms "first," "second," and "third" may be used herein to describe various elements, components, regions, layers and/or sections, they are used to refer to an element, One element, region, layer and/or section is distinguished from another element, region, layer and/or section. Accordingly, they are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or sequential relationships thereof.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly so defined herein.

Please refer to FIG. 1 , which is a schematic diagram of a driving circuit according to an embodiment of the present invention. As shown in the figure, the driving circuit 10 includes a pixel driving circuit 11, a gate node driving circuit 12, a driving capacitor 13, a control node driving circuit 14 and a multiplexer circuit 15. The pixel driving circuit 11 includes a driving transistor TD. The first terminal of the driving transistor TD is coupled to the high voltage source OVDD. The second terminal of the driving transistor TD is coupled to the light emitting element E. The light emitting element E is coupled to the low voltage source OVSS. The driving The control terminal of the transistor TD is coupled to the gate node VG. The gate node VG is coupled to one end of the driving capacitor 13, and the other end of the driving capacitor 13 is coupled to the control node VT. The driving capacitor 13 provides a voltage for controlling the driving transistor TD through the voltage difference between the gate node VG and the control node VT. driving voltage. The gate node driving circuit 12 is coupled to the gate node VG, and the voltage of the gate node VG is pulled down through the gate node driving circuit 12 . The control node driving circuit 14 is coupled to the control node VT, and the voltage of the control node VT is pulled up through the control node driving circuit 14 .

The multiplexer circuit 15 includes a data transistor Tdata and a data line capacitor Cdata. The first terminal of the data transistor Tdata is coupled to the control node VT. The second terminal of the data transistor Tdata is coupled to the data line capacitor Cdata. The control terminal of the data transistor Tdata coupled to the signal line S. The data line capacitor Cdata can store the voltage required by the data line. The signal line S controls the data transistor Tdata to turn on to write the stored data voltage to the control node VT. Since each pixel row contains multiple sub-pixels, the data of the data voltage is stored. The capacity of the line capacitor Cdata is larger than the drive capacitor 13. The second terminal of the data transistor Tdata is also coupled to the first terminal of the multiplexer transistor TM. The first terminal of the multiplexer transistor TM is coupled to the node N. The control terminal of the multiplexer transistor TM is coupled to the control line SW. . Among the display pixels of the display, the data signals required to connect the data lines of each sub-pixel can be provided through the multiplexer circuit 15. Different pixel rows can provide data signals from the same node N, and the control line SW controls the multiplexer transistor TM. Turn on to provide the data signals required for each pixel row. The arrangement of the multiplexer circuit 15 can reduce the arrangement of data line transmission nodes, reduce the driving circuit components and the required circuit arrangement space.

In the previous drive structure design, the multiplexer circuits 15 of different pixel rows are controlled by the control line SW, so that the multiplexer transistors TM are turned on sequentially to provide data signals. However, when the data voltage writing time is different, , corresponding to the gate node VG in the final multiplexer circuit, there is not enough time to pull back to the preset maximum voltage during the reset operation, resulting in the generation of insufficient compensation voltage. When the data voltage is written, the coupling voltage This situation causes the current flowing through the control drive transistor to increase when it is turned on, causing the brightness of the light-emitting element E to increase, causing uneven brightness or color shift in the display panel. In addition, the reset operation of resetting the gate node VG to the preset maximum voltage creates a leakage path in the direction of the high voltage source OVDD toward the set voltage source, which also causes the brightness of the display screen to change, affecting the display quality. In the embodiment of the present disclosure, through the settings of the gate node driving circuit 12 and the control node driving circuit 14, the writing of the multiplexer circuit 15 does not directly enter the pixel through the data line, but first writes to the pixel. In the data line, that is, in the data line capacitance Cdata, it enters the driving capacitor 13 at the same time point, so that the corresponding compensation time of each multiplexer circuit 15 is the same, avoiding differences in the time sequence of different multiplexer circuits 15 The voltage difference is caused, and the detailed circuit configuration structure is further explained in the following embodiments.

Please refer to FIG. 2A , which is a schematic circuit diagram of a driving circuit according to the first embodiment of the present invention. Please also refer to FIG. 2B , which is a schematic waveform diagram of the driving circuit according to the first embodiment of the present invention. In FIG. 2A , the driving circuit 20 includes a pixel driving circuit 21 , a gate node driving circuit 22 , a driving capacitor 23 , a control node driving circuit 24 and a multiplexer circuit 25 . The pixel driving circuit 21 includes a driving transistor TD and a light-emitting transistor TE. The first terminal of the driving transistor TD is coupled to the high voltage source OVDD. The second terminal of the driving transistor TD is coupled to the first terminal of the light-emitting transistor TE. The driving transistor TD has a The control terminal is coupled to the gate node VG. The second end of the light-emitting transistor TE is coupled to the light-emitting element E, and the control end of the light-emitting transistor TE is coupled to the signal source of the light-emitting signal EM. The light-emitting signal EM turns on the light-emitting transistor TE so that current flows to the light-emitting element E, controlling the light-emitting element E. glow. One end of the light-emitting element E is coupled to the first end of the transistor T1, and the second end of the transistor T1 and the control end of the transistor T1 are coupled to the signal source of the subsequent first signal S1, n+1 in a diode connection. , the other end of the light-emitting element E is coupled to the low voltage source OVSS.

The gate node VG is coupled to one end of the driving capacitor 23 and the other end of the driving capacitor 23 is coupled to the control node VT. The gate node driving circuit 22 is coupled to the gate node VG. The gate node driving circuit 22 includes a first transistor. At T21, the first terminal of the first transistor T21 is coupled to the first reference voltage Vref N, the second terminal of the first transistor T21 is coupled to the gate node VG, and the control terminal of the first transistor T21 receives the first signal S1 of the current stage. ,n is the voltage that pulls down the gate node VG. The control node driving circuit 24 is coupled to the control node VT. The control node driving circuit 24 includes a second transistor T22, a first terminal of the second transistor T22 is coupled to the second reference voltage Vref P, and a second terminal of the second transistor T22 is coupled to the second reference voltage Vref P. Connected to the control node VT, the T22 control end of the second transistor receives an external signal EM2,n to pull up the voltage of the control node VT. The external signal EM2,n is formed by combining the waveform of the first signal S1,n of the current stage and the light-emitting signal EM. signal of.

The multiplexer circuit 25 includes a data transistor Tdata, a data line capacitor Cdata and a multiplexer transistor TM. The first terminal of the data transistor Tdata is coupled to the control node VT. The second terminal of the data transistor Tdata is coupled to the data line capacitor Cdata. The control terminal of the data transistor Tdata is coupled to the second signal line S2,n of the current stage. The second signal line S2,n of the current stage is also connected to the control terminal of the transistor T2. The first terminal of the transistor T2 is coupled to the gate node VG. , the second terminal of the transistor T2 is coupled to the pixel driving circuit 21 .

Please refer to Figure 2B. In the timing sequence of the first data line, when the first signal S1,n turns on the first transistor T21, the voltage of the gate node VG is pulled down through the first reference voltage Vref N, and at the same time, the external signal EM2,n is connected. The second transistor T22 is turned on to pull up the voltage of the control node VT through the second reference voltage Vref P. In the multiplexer circuit 25 part, the multiplexer signal MUX,n turns on the multiplexer transistor TM and writes the voltage of the data line into the data line capacitor Cdata, because the second signal S2,n of the current stage is not turned on at this time. The data line voltage of the data transistor Tdata is not written to the driving capacitor 23, and because the data transistor Tdata is in the off state, the data writing process of the multiplexer circuit 25 is not the same as the gate node driving circuit 22 and the control node driving circuit 24. The precharging process can be performed independently and simultaneously, and there is no need to wait for the multiplexer signal MUX,n to be turned on before the multiplexer circuit 25 performs the precharging process. Allowing the writing process and the precharging process to be executed simultaneously in separate processes can avoid voltage differences caused by insufficient compensation time caused by multiplexers in different sequences, resulting in an increase in the voltage transmitted to the pixels and affecting the display brightness.

Continuing the aforementioned sequence, when the first signal S1,n of the stage turns to a high potential, the first transistor T21 is turned off, the external signal EM2,n also turns to a high potential, the second transistor T22 is turned off, and when the second signal S2,n of the stage turns on the data transistor Tdata , coupling the data voltage to the control node VT, that is, writing the voltage signal of the data line from the data line capacitor Cdata to the driving capacitor 23 of the pixel. The timing of the first signal S1,n of the current stage and the second signal S2,n of the current stage do not overlap, so the first transistor T21 and the transistor T2 will not be turned on at the same time, preventing the high voltage source OVDD from moving towards the first reference voltage Vref N A leakage path is generated, causing the entire display brightness to be pulled and causing flickering problems.

In addition, when the timing of the second data line proceeds, the second transistor T22 of the control node driving circuit 24 needs to be turned on by the external signal EM2,n, and the gate node VG and the control node VT are pulled back to the second data line. The second reference voltage Vref P, therefore, the external signal EM2,n must include the luminous signal EM of the subsequent stage.

Please refer to FIG. 3A , which is a schematic circuit diagram of a driving circuit according to a second embodiment of the present invention. Please also refer to FIG. 3B , which is a schematic waveform diagram of the driving circuit according to the second embodiment of the present invention. In FIG. 3A , the driving circuit 30 includes a pixel driving circuit 31 , a gate node driving circuit 32 , a driving capacitor 33 , a control node driving circuit 34 and a multiplexer circuit 35 . The pixel driving circuit 31 includes a driving transistor TD and a light-emitting transistor TE. The first terminal of the driving transistor TD is coupled to the high voltage source OVDD. The second terminal of the driving transistor TD is coupled to the first terminal of the light-emitting transistor TE. The driving transistor TD has a The control terminal is coupled to the gate node VG. The second end of the light-emitting transistor TE is coupled to the light-emitting element E, and the control end of the light-emitting transistor TE is coupled to the signal source of the light-emitting signal EM. The light-emitting signal EM turns on the light-emitting transistor TE so that current flows to the light-emitting element E, controlling the light-emitting element E. glow. One end of the light-emitting element E is coupled to the first end of the transistor T1, and the second end of the transistor T1 and the control end of the transistor T1 are coupled to the signal source of the first signal S1, n of the current stage in a diode connection, and emits light. The other end of element E is coupled to the low voltage source OVSS.

The gate node VG is coupled to one end of the driving capacitor 33 and the other end of the driving capacitor 33 is coupled to the control node VT. The gate node driving circuit 32 is coupled to the gate node VG. The gate node driving circuit 32 includes a first transistor. T31, the first terminal of the first transistor T31 is coupled to the first reference voltage Vref N, the second terminal of the first transistor T31 is coupled to the gate node VG, and the control terminal of the first transistor T21 receives the first signal S1 of the previous stage. ,n-1 is the voltage below the pull-down gate node VG. The control node driving circuit 34 is coupled to the control node VT. The control node driving circuit 34 includes a second transistor T32, a first terminal of the second transistor T32 is coupled to the second reference voltage Vref P, and a second terminal of the second transistor T32 is coupled to the second reference voltage Vref P. Connected to the control node VT, the T32 control end of the second transistor receives an external signal EM2,n to pull up the voltage of the control node VT. The external signal EM2,n is combined with the first signal S1,n-1 of the previous stage and the first signal of the current stage. A signal formed by the waveform of S1,n and the luminescence signal EM.

The multiplexer circuit 35 includes a data transistor Tdata, a data line capacitor Cdata and a multiplexer transistor TM. The first terminal of the data transistor Tdata is coupled to the control node VT. The second terminal of the data transistor Tdata is coupled to the data line capacitor Cdata. The control terminal of the data transistor Tdata is coupled to the second signal line S2,n of the current stage. The second signal line S2,n of the current stage is also connected to the control terminal of the transistor T2. The first terminal of the transistor T2 is coupled to the gate node VG. , the second terminal of the transistor T2 is coupled to the pixel driving circuit 31 .

Please refer to Figure 3B. In the timing sequence of the first data line, the first signal S1, n-1 of the previous stage turns on the first transistor T31, pulling down the voltage of the gate node VG through the first reference voltage Vref N, and at the same time, the external signal EM2 is connected. , n turns on the second transistor T32 and pulls up the voltage of the control node VT through the second reference voltage Vref P. In the multiplexer circuit 35 part, the multiplexer signal MUX,n turns on the multiplexer transistor TM and writes the voltage of the data line into the data line capacitor Cdata, because the second signal S2,n of the current stage is not turned on at this time. The data line voltage of the data transistor Tdata is not written to the driving capacitor 33, and because the data transistor Tdata is in the off state, the data writing process of the multiplexer circuit 35 is not the same as the gate node driving circuit 32 and the control node driving circuit 34. The precharging process can be performed independently and simultaneously, and there is no need to wait for the multiplexer signal MUX,n to be turned on before the multiplexer circuit 35 performs the precharging process. Allowing the writing process and the precharging process to be executed simultaneously in separate processes can avoid voltage differences caused by insufficient compensation time caused by multiplexers in different sequences, resulting in an increase in the voltage transmitted to the pixels and affecting the display brightness.

Continuing the aforementioned timing sequence, the first signal S1,n-1 of the previous stage turns off the first transistor T31, and the external signal EM2,n also turns to high potential to turn off the second transistor T32. When the multiplexer signal MUX,n sequentially writes the data voltage After the input is completed, the second signal S2,n of the current stage turns on the data transistor Tdata and couples the data voltage to the control node VT, that is, the voltage signal of the data line is written from the data line capacitor Cdata to the driving capacitor 33 of the pixel. In this embodiment, the first transistor T21 and the transistor T2 are also not turned on at the same time to avoid a leakage path from the high voltage source OVDD to the first reference voltage Vref N, causing the display brightness of the entire surface to be pulled and causing flickering problems. .

Please refer to FIG. 4A , which is a schematic circuit diagram of a driving circuit according to a third embodiment of the present invention. Please also refer to FIG. 4B , which is a schematic waveform diagram of the driving circuit according to the third embodiment of the present invention. In FIG. 4A , the driving circuit 40 includes a pixel driving circuit 41 , a gate node driving circuit 42 , a driving capacitor 43 , a control node driving circuit 44 and a multiplexer circuit 45 . The pixel driving circuit 41 includes a driving transistor TD and a light-emitting transistor TE. The first terminal of the driving transistor TD is coupled to the high voltage source OVDD. The second terminal of the driving transistor TD is coupled to the first terminal of the light-emitting transistor TE. The driving transistor TD has a The control terminal is coupled to the gate node VG. The second end of the light-emitting transistor TE is coupled to the light-emitting element E, and the control end of the light-emitting transistor TE is coupled to the signal source of the light-emitting signal EM. The light-emitting signal EM turns on the light-emitting transistor TE so that current flows to the light-emitting element E, controlling the light-emitting element E. glow. One end of the light-emitting element E is coupled to the first end of the transistor T1, and the second end of the transistor T1 and the control end of the transistor T1 are coupled to the signal source of the subsequent first signal S1, n+1 in a diode connection. , the other end of the light-emitting element E is coupled to the low voltage source OVSS.

The gate node VG is coupled to one end of the driving capacitor 43 and the other end of the driving capacitor 43 is coupled to the control node VT. The gate node driving circuit 42 is coupled to the gate node VG. The gate node driving circuit 42 includes a first transistor. T41, the first terminal of the first transistor T41 is coupled to the first reference voltage Vref N, the second terminal of the first transistor T41 is coupled to the gate node VG, and the control terminal of the first transistor T41 receives the first signal S1 of the current stage. ,n is the voltage that pulls down the gate node VG. The control node driving circuit 44 is coupled to the control node VT. The control node driving circuit 44 includes a second transistor T42 and a third transistor T43. The first end of the second transistor T42 is coupled to the second reference voltage Vref P. The second transistor T42 The second terminal of the third transistor T43 is coupled to the control node VT, the first terminal of the third transistor T43 is coupled to the second reference voltage Vref P, and the second terminal of the third transistor T43 is coupled to the control node VT. The T42 control terminal of the second transistor receives the first signal S1,n of the current stage to pull up the voltage of the control node VT, and the T43 control terminal of the third transistor receives the light-emitting signal EM to pull down the voltage of the control node VT and the gate node VG.

The multiplexer circuit 45 includes a data transistor Tdata, a data line capacitor Cdata and a multiplexer transistor TM. The first terminal of the data transistor Tdata is coupled to the control node VT. The second terminal of the data transistor Tdata is coupled to the data line capacitor Cdata. The control terminal of the data transistor Tdata is coupled to the second signal line S2,n of the current stage. The second signal line S2,n of the current stage is also connected to the control terminal of the transistor T2. The first terminal of the transistor T2 is coupled to the gate node VG. , the second terminal of the transistor T2 is coupled to the pixel driving circuit 41 .

Please refer to Figure 4B. In the timing sequence of the first data line, when the first signal S1, n turns on the first transistor T31 and the second transistor T32 at the same time, the voltage of the gate node VG is pulled down through the first reference voltage Vref N. The voltage of the control node VT is also pulled up by the second reference voltage Vref P. In the multiplexer circuit 35 part, the multiplexer signal MUX,n turns on the multiplexer transistor TM and writes the voltage of the data line into the data line capacitor Cdata, because the second signal S2,n of the current stage is not turned on at this time. The data line voltage of the data transistor Tdata is not written to the driving capacitor 43, and because the data transistor Tdata is in the off state, the data writing process of the multiplexer circuit 45 is not the same as that of the gate node driving circuit 42 and the control node driving circuit 44. The precharging process can be performed independently and simultaneously, and there is no need to wait for the multiplexer signal MUX,n to be turned on before the multiplexer circuit 45 performs the precharging process. Allowing the writing process and the precharging process to be executed simultaneously in separate processes can avoid voltage differences caused by insufficient compensation time caused by multiplexers in different sequences, resulting in an increase in the voltage transmitted to the pixels and affecting the display brightness.

Continuing the aforementioned sequence, when the first signal S1,n of the stage turns to a high potential, the first transistor T31 and the second transistor T32 are turned off. When the multiplexer signal MUX,n completes writing the data voltage in sequence, the second signal of the stage S2,n turns on the data transistor Tdata and couples the data voltage to the control node VT, that is, the voltage signal of the data line is written from the data line capacitor Cdata to the driving capacitor 43 of the pixel. In this embodiment, the first transistor T21 and the transistor T2 are also not turned on at the same time to avoid a leakage path from the high voltage source OVDD to the first reference voltage Vref N, causing the display brightness of the entire surface to be pulled and causing flickering problems. .

When proceeding to the timing sequence of the second data line, the second transistor T43 of the control node driving circuit 44 needs to turn on the third transistor T43 according to the light emitting signal EM, and pull the gate node VG and the control node VT back to the second reference voltage Vref. P, therefore, the light-emitting signal EM must be set in the timing of the latter data line.

Please refer to FIG. 5A , which is a schematic circuit diagram of a driving circuit according to a fourth embodiment of the present invention. Please also refer to FIG. 5B , which is a schematic waveform diagram of the driving circuit according to the fourth embodiment of the present invention. In FIG. 4A , the driving circuit 50 includes a pixel driving circuit 51 , a gate node driving circuit 52 , a driving capacitor 53 , a control node driving circuit 54 and a multiplexer circuit 55 . The pixel driving circuit 51 includes a driving transistor TD and a light-emitting transistor TE. The first terminal of the driving transistor TD is coupled to the high voltage source OVDD. The second terminal of the driving transistor TD is coupled to the first terminal of the light-emitting transistor TE. The driving transistor TD has a The control terminal is coupled to the gate node VG. The second end of the light-emitting transistor TE is coupled to the light-emitting element E, and the control end of the light-emitting transistor TE is coupled to the signal source of the light-emitting signal EM. The light-emitting signal EM turns on the light-emitting transistor TE so that current flows to the light-emitting element E, controlling the light-emitting element E. glow. One end of the light-emitting element E is coupled to the first end of the transistor T1, and the second end of the transistor T1 and the control end of the transistor T1 are coupled to the signal source of the first signal S1, n of the current stage in a diode connection, and emits light. The other end of element E is coupled to the low voltage source OVSS.

The gate node VG is coupled to one end of the driving capacitor 53 and the other end of the driving capacitor 53 is coupled to the control node VT. The gate node driving circuit 52 is coupled to the gate node VG. The gate node driving circuit 52 includes a first transistor. T51 and the fourth transistor T54. The control node driving circuit 54 includes a second transistor T52 and a third transistor T53. The first terminal of the fourth transistor T54 is coupled to the first reference voltage Vref N. The second terminal of the fourth transistor T54 is Coupled to the first terminal of the first transistor T51, the second terminal of the first transistor T51 is coupled to the gate node VG, the control terminal of the first transistor T51 receives the first signal S1,n of the current stage, and the control terminal of the fourth transistor T54 The control terminal receives the first signal S1,n-1 of the previous stage and pulls down the voltage of the gate node VG by simultaneously turning on the first transistor T51 and the fourth transistor T54. The control node driving circuit 54 is coupled to the control node VT, the first terminal of the second transistor T52 is coupled to the second reference voltage Vref P, the second terminal of the second transistor T52 is coupled to the control node VT, and the third transistor T53 The first terminal is coupled to the second reference voltage Vref P, and the second terminal of the third transistor T53 is coupled to the control node VT. The T52 control terminal of the second transistor receives the first signal S1,n of the current stage to pull up the voltage of the control node VT, and the T53 control terminal of the third transistor receives the light-emitting signal EM to pull down the voltage of the control node VT and the gate node VG.

Please refer to Figure 5B. In the timing sequence of the first data line, the first signal S1,n-1 of the previous stage and the first signal S1,n of the current stage turn on the first transistor T51 and the fourth transistor T54 at the same time. The voltage Vref N pulls down the voltage of the gate node VG. When the first signal S1, n turns on the second transistor T52, the voltage of the control node VT is pulled up through the second reference voltage Vref P. In the multiplexer circuit 55 part, the multiplexer signal MUX,n turns on the multiplexer transistor TM and writes the voltage of the data line into the data line capacitor Cdata, because the second signal S2,n of the current stage is not turned on at this time. The data line voltage of the data transistor Tdata is not written to the driving capacitor 53, and because the data transistor Tdata is in the off state, the data writing process of the multiplexer circuit 55 is not the same as that of the gate node driving circuit 52 and the control node driving circuit 54. The precharging process can be performed independently and simultaneously, and there is no need to wait for the multiplexer signal MUX,n to be turned on before the multiplexer circuit 45 performs the precharging process. Allowing the writing process and the precharging process to be executed simultaneously in separate processes can prevent the multiplexers in different sequences from causing insufficient compensation time and causing voltage differences, resulting in an increase in the voltage transmitted to the pixels and affecting the display brightness.

Continuing the aforementioned timing sequence, when the first signal S1,n of the stage turns to a high potential, the first transistor T51 and the second transistor T52 are turned off. When the multiplexer signal MUX,n completes writing the data voltage in sequence, the second signal of the stage S2,n turns on the data transistor Tdata and couples the data voltage to the control node VT, that is, the voltage signal of the data line is written from the data line capacitor Cdata to the driving capacitor 53 of the pixel. In this embodiment, the first transistor T51 and the transistor T2 are also not turned on at the same time to avoid a leakage path from the high voltage source OVDD to the first reference voltage Vref N, causing the display brightness of the entire surface to be pulled and causing flickering problems. .

In the foregoing embodiments, although the first and second embodiments can save the number of transistors, new signal lines must be added to control the transistors, which can be adjusted according to the needs of the display device during actual implementation. Through the settings of the gate node drive circuit and the control node drive circuit, it is possible to avoid the problem that the gate node does not have enough time to pull back to the preset voltage when the multiplexer transmits signals sequentially, causing the display device to display without brightness. For example, if the final multiplexer corresponds to a red sub-pixel, the picture will appear reddish. When implemented with the driving circuit of the present disclosure, the color shift can be effectively reduced.

The above is only illustrative and not restrictive. Any equivalent modifications or changes without departing from the spirit and scope of the invention shall be included in the appended claims.

Claims (9)

1. A drive circuit, comprising:

a pixel driving circuit comprising a driving transistor, a first end of the driving transistor is coupled to a high voltage source, a second end of the driving transistor is coupled to a light emitting element, and a control end of the driving transistor is coupled to a gate node;

a gate node driving circuit coupled to the gate node for pulling down the voltage of the gate node;

one end of the driving capacitor is coupled with the grid node, and the other end of the driving capacitor is coupled with a control node;

a control node driving circuit coupled to the control node for pulling up the voltage of the control node; and

the multiplexer circuit comprises a data transistor, a data line capacitor and a multiplexer transistor, wherein a first end of the data transistor is coupled to the control node, a second end of the data transistor is coupled to the data line capacitor and the first end of the multiplexer transistor, a control end of the multiplexer transistor is coupled to a control line, and the multiplexer transistor is controlled to be turned on in sequence by the control line.

2. The driving circuit of claim 1, wherein the pixel driving circuit comprises a light emitting transistor, a first terminal of the light emitting transistor is coupled to a second terminal of the driving transistor, a second terminal of the light emitting transistor is coupled to the light emitting element, and a control terminal of the light emitting transistor receives a light emitting signal to control the light emitting element to emit light;

the gate node driving circuit comprises a first transistor, wherein a first end of the first transistor is coupled to a first reference voltage, and a second end of the first transistor is coupled to the gate node;

the control node driving circuit comprises a second transistor, wherein a first end of the second transistor is coupled to a second reference voltage, and a second end of the second transistor is coupled to the control node.

3. The driving circuit of claim 2, wherein the control terminal of the first transistor receives a current level first signal to pull down the voltage of the gate node, and the control terminal of the second transistor receives an external signal to pull up the voltage of the control node, the external signal comprising the current level first signal and a back-electrode light-emitting signal.

4. The driving circuit of claim 2, wherein the control terminal of the first transistor receives a pre-first signal to pull down the voltage of the gate node, and the control terminal of the second transistor receives an external signal to pull up the voltage of the control node, the external signal including the pre-first signal, a current-first signal and the light-emitting signal.

5. The driving circuit of claim 2, wherein the control node driving circuit comprises a third transistor, a first terminal of the third transistor is coupled to the second reference voltage and the first terminal of the second transistor, and a second terminal of the third transistor is coupled to the control node and the second terminal of the second transistor.

6. The driving circuit of claim 5, wherein the control terminal of the first transistor receives a current level first signal to pull down the voltage of the gate node, the control terminal of the second transistor receives the current level first signal and the control terminal of the third transistor receives the light-emitting signal to pull up the voltage of the control node.

7. The driving circuit of claim 2, wherein the control node driving circuit comprises a third transistor, a first end of the third transistor is coupled to the second reference voltage and a first end of the second transistor, a second end of the third transistor is coupled to the control node and a second end of the second transistor, the gate node driving circuit comprises a fourth transistor, a first end of the fourth transistor is coupled to the first reference voltage, and a second end of the fourth transistor is coupled to the first end of the first transistor.

8. The driving circuit as claimed in claim 7, wherein the control terminal of the first transistor receives a current level first signal and the control terminal of the fourth transistor receives a previous level first signal to pull down the voltage of the gate node, and the control terminal of the second transistor receives the current level first signal and the control terminal of the third transistor receives the light emitting signal to pull up the voltage of the control node.

9. The driving circuit of any one of claims 3, 4, 6, 8, wherein the control terminal of the data transistor receives a second signal to control the data transistor, the multiplexer circuit stores a data voltage in the data line capacitor when the data transistor is turned off, and the multiplexer circuit couples the data voltage to the control node when the data transistor is turned on.