CN113806148A - PCI express socket detection system - Google Patents
PCI express socket detection system Download PDFInfo
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- CN113806148A CN113806148A CN202010549763.7A CN202010549763A CN113806148A CN 113806148 A CN113806148 A CN 113806148A CN 202010549763 A CN202010549763 A CN 202010549763A CN 113806148 A CN113806148 A CN 113806148A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Tests Of Electronic Circuits (AREA)
Abstract
A fast peripheral component interconnection control chip transmits detection signals from a fast peripheral component interconnection interface to detect the fast peripheral component interconnection slot and generate first detection result information, the first detection result information is transmitted to a detection program through the fast peripheral component interconnection slot, a detection logic control chip transmits the detection signals from the fast peripheral component interconnection interface to carry out detection control and detection logic setting according to the detection signals to detect the fast peripheral component interconnection slot and generate second detection result information, and the second detection result information is transmitted to the detection program through the fast peripheral component interconnection slot, so that the technical effect of individual detection of the pin positions of the fast peripheral component interconnection slot can be achieved.
Description
Technical Field
The present invention relates to a detection system, and more particularly to a detection system for detecting pins of a PCI express socket.
Background
The detection of the current interconnecting slot of the peripheral component express is usually realized by adopting a standard peripheral component express interconnecting network card, the detection of the standard peripheral component express interconnecting network card can only detect basic power supply characteristics and the connection state of the standard peripheral component express interconnecting slot, each corner of the standard peripheral component express interconnecting slot can not be separately detected in detail, the function of auxiliary pin position detection is not provided, and the existing detection coverage rate of the standard peripheral component express interconnecting slot is low.
In summary, it is known that the conventional pin detection for the PCI express socket test has not been able to provide pin detection for the standard PCI express socket test for a long time, and therefore, it is necessary to provide improved technical means for solving the problem.
Disclosure of Invention
In view of the problem of the prior art that the detection of the standard PCI express slot cannot provide the detection of each pin, the present invention discloses a PCI express slot detection system, wherein:
the present invention discloses a PCI express slot detection system according to a first embodiment, comprising: mainboard and detection circuit board, the detection circuit board still contains: the PCI express control chip and the detection logic control chip are interconnected.
The main board is provided with a Central Processing Unit (CPU), a memory and a Peripheral Component Interconnect Express (PCIe) slot, a detection program is stored in the memory, the CPU loads and executes the detection program from the memory to generate a detection signal, and the detection program transmits the detection signal, first detection result information and second detection result information through the PCIe slot.
The detection circuit board is inserted into the quick peripheral component interconnection slot through the quick peripheral component interconnection interface, a quick peripheral component interconnection control chip of the detection circuit board is electrically connected with the quick peripheral component interconnection interface directly through a switch, a detection signal is transmitted from the quick peripheral component interconnection interface to detect the quick peripheral component interconnection slot and generate first detection result information, and the first detection result information is transmitted to a detection program through the quick peripheral component interconnection slot; and the detection logic control chip of the detection circuit board is electrically connected with the fast peripheral component interconnection interface directly through the switch, the detection logic control chip is electrically connected with the fast peripheral component interconnection control chip directly through the switch, the detection signals are transmitted from the fast peripheral component interconnection interface to carry out detection control according to the detection signals and carry out detection logic setting so as to detect the fast peripheral component interconnection slot and generate second detection result information, and the second detection result information is transmitted to the detection program through the fast peripheral component interconnection slot.
The present invention discloses a PCI express slot detection system according to a second embodiment, comprising: mainboard, detection circuitry board and detection device, the detection circuitry board still contains: the peripheral component interconnect express (PCI express) device comprises a PCI express control chip, a detection logic control chip, a first UART-to-RS-232 interface chip, a second UART-to-RS-232 interface chip, a PCI express (PCIe) switch connector and a detection logic connection connector.
The mainboard is provided with a quick peripheral component interconnection slot, the detection circuit board is inserted into the quick peripheral component interconnection slot through a quick peripheral component interconnection interface, a quick peripheral component interconnection control chip of the detection circuit board and the quick peripheral component interconnection interface are directly electrically connected through a switch, and the detection circuit board receives a detection signal to detect the quick peripheral component interconnection slot and generate first detection result information; the detection logic control chip of the detection circuit board is electrically connected with the fast peripheral component interconnection interface directly through the switch, the detection logic control chip is electrically connected with the fast peripheral component interconnection control chip directly through the switch, and the detection logic control chip receives detection signals to perform detection control according to the detection signals and perform detection logic setting to detect the fast peripheral component interconnection slot and generate second detection result information; the fast peripheral component interconnection packet switching connector and the fast peripheral component interconnection control chip of the detection circuit board are directly electrically connected with the RS-232 interface chip through the first UART, the fast peripheral component interconnection packet switching connector transmits a detection signal to the fast peripheral component interconnection control chip, and the fast peripheral component interconnection packet switching connector transmits first detection result information; and the detection logic connection connector of the detection circuit board is electrically connected with the detection logic control chip through a second UART-to-RS-232 interface chip, the detection logic connection connector transmits detection signals to the detection logic control chip, and the detection logic connection connector transmits second detection result information.
The detection device executes a detection program to generate a detection signal, the detection device is electrically connected with the PCI express packet switching connector and the detection logic connection connector respectively, the detection program transmits the detection signal through the PCI express packet switching connector and the detection logic connection connector respectively, the detection program transmits first detection result information through the PCI express packet switching connector, and the detection program transmits second detection result information through the detection logic connection connector.
The system disclosed in the present invention is different from the prior art in that the pci express control chip transmits a detection signal from the pci express interface to detect the pci express slot and generate first detection result information, transmits the first detection result information to the detection program through the pci express slot, transmits a detection signal from the pci express interface to perform detection control according to the detection signal and perform detection logic setting to detect the pci express slot and generate second detection result information, and transmits the second detection result information to the detection program through the pci express slot.
Through the technical means, the invention can achieve the technical effect of individual detection of the pins of the quick peripheral component interconnect slot.
Drawings
FIG. 1 is a block diagram of a PCI express slot inspection system according to a first embodiment of the present invention.
FIG. 2 is a block diagram of a PCI express slot inspection system according to a second embodiment of the present invention.
FIG. 3 is a schematic diagram of power pin detection for PCI express slot detection according to the present invention.
FIG. 4A is a schematic diagram of a system management bus Master mode detection for PCI express slot detection according to the present invention.
FIG. 4B is a schematic diagram illustrating detection of a system management bus Slave mode for PCI express slot detection according to the present invention.
FIG. 5 is a schematic diagram illustrating wake-up detection for PCI express slot detection according to the present invention.
FIG. 6 is a schematic diagram illustrating an IO test model for PCI express socket test according to the present invention.
Description of the symbols
10 main board
11 central processing unit
12 memory
PCI express slot
20, detection circuit board
21 quick peripheral component interconnection control chip
22, detection logic control chip
221 first detection logic control chip
222 second detection logic control chip
23 quick peripheral assembly interconnection interface
24: switch
25 read-only memory
26 EJTAG interface
27 JLINK interface
28 quartz oscillator
29: clock generator
31 first UART to RS-232 interface chip
32: second UART-to-RS-232 interface chip
33 PCI express packet switch connector
34 testing the logical connection connector
Detailed Description
The following detailed description of the embodiments of the present invention will be provided in conjunction with the accompanying drawings and examples, so that how to implement the technical means for solving the technical problems and achieving the technical effects of the present invention can be fully understood and implemented.
Referring to fig. 1, fig. 1 is a block diagram of a pci express slot inspection system according to a first embodiment of the present invention.
The present invention discloses a PCI express slot detection system according to a first embodiment, comprising: mainboard 10 and detection circuit board 20, detection circuit board 20 still contains: the PCI express control chip 21 and the detection logic control chip 22.
The motherboard 10 has a central processing unit 11, a memory 12, and a Peripheral Component Interconnect Express (PCIe) slot 13, wherein a detection program is stored in the memory 12, and the central processing unit 11 loads and executes the detection program from the memory 12 to generate a detection signal.
The detection circuit board 20 is inserted into the pci express slot 13 through the pci express interface 23, the pci express control chip 21 of the detection circuit board 20 and the pci express interface 23 are directly electrically connected to each other through the switch 24, the detection logic control chip 22 of the detection circuit board 20 and the pci express interface 23 are directly electrically connected to each other through the switch 24, and the detection logic control chip 22 and the pci express control chip 21 are directly electrically connected to each other through the switch 24.
In addition, the inspection circuit board 20 further includes: Read-Only Memory (ROM) 25, EJTAG interface 26, JLINK interface 27, and crystal oscillator (crystal) 28.
The ROM 25 is electrically connected to the PCI express control chip 22, the EJTAG interface 26 is electrically connected to the PCI express control chip 22, the JLINK interface 27 is electrically connected to the detection logic control chip 24, the quartz oscillator 28 is electrically connected to the PCI express control chip 22 through a Clock 29, and the quartz oscillator 28 is electrically connected to the detection logic control chip 24.
The detection program can transmit the detection signal to the pci express control chip 21 through the pci express slot 13, the pci express control chip 21 detects the pci express slot 13 according to the detection signal and generates first detection result information, and the pci express control chip 21 transmits the first detection result information to the detection program through the pci express slot 13.
The detection program can transmit the detection signal to the detection logic control chip 22 through the pci express slot 13, the detection logic control chip 22 performs detection control and detection logic setting according to the detection signal to detect the pci express slot 13 and generate second detection result information, and the detection logic control chip 22 transmits the second detection result information to the detection program through the pci express slot 13.
It is noted that the pci express slot 13 performs detection including power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switching detection, System Management Bus (SMBus) detection, WAKE (WAKE) detection, JTAG detection, PWRBRK detection, and CLKREQ detection.
Next, a pci express slot inspection system according to a second embodiment of the present invention is described below with reference to fig. 2, wherein fig. 2 is a system block diagram of the pci express slot inspection system according to the second embodiment of the present invention.
The present invention discloses a PCI express slot detection system according to a second embodiment, comprising: mainboard 10, detection circuit board 20 and detection device 40, detection circuit board 20 still contains: the PCI express control chip 21, the detection logic control chip 22, the first UART to RS-232 interface chip 31, the second UART to RS-232 interface chip 32, the PCI express switch connector 33 and the detection logic connector 34.
The detection circuit board 20 is inserted into the PCI express slot 13 through the PCI express interface 23, the PCI express control chip 21 of the detection circuit board 20 and the PCI express interface 23 are directly electrically connected with the pass switch 24, the detection logic control chip 22 and the PCI express control chip 21 are directly electrically connected with the pass switch 24, the PCI express switch connector 33 of the detection circuit board 20 and the PCI express control chip 21 are directly electrically connected with the RS-232 interface chip 31 through the first UART, the detection logic connector 34 of the detection circuit board 20 is electrically connected to the detection logic control chip 22 via the second UART-to-RS-232 interface chip 32.
In addition, the inspection circuit board 20 further includes: read only memory 25, EJTAG interface 26, JLINK interface 27, and quartz oscillator 28.
The ROM 25 is electrically connected to the PCI express control chip 22, the EJTAG interface 26 is electrically connected to the PCI express control chip 22, the JLINK interface 27 is electrically connected to the detection logic control chip 24, the quartz oscillator 28 is electrically connected to the PCI express control chip 22 through a Clock 29, and the quartz oscillator 28 is electrically connected to the detection logic control chip 24.
The detecting device 30 executes a detecting program to generate a detecting signal, the detecting device 30 is electrically connected to the pci express connector 33 and the detecting logic connector 34, respectively, the detecting program transmits the detecting signal to the pci express control chip 21 through the pci express connector 33 in a UART transmission manner, the pci express control chip 21 detects the pci express slot 13 according to the detecting signal and generates first detecting result information, and the pci express control chip 21 transmits the first detecting result information through the pci express connector 33.
The detection program transmits a detection signal to the detection logic control chip 22 through the detection logic connection connector 34 in a UART transmission manner, the detection logic control chip 22 performs detection control and detection logic setting according to the detection signal to detect the pci express slot 13 and generate second detection result information, and the detection logic control chip 22 transmits the second detection result information to the detection program through the detection logic connection connector 34.
It is noted that the pci express slot 13 performs detection including power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switching detection, System Management Bus (SMBus) detection, WAKE (WAKE) detection, JTAG detection, PWRBRK detection, and CLKREQ detection.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating power pin detection for pci express slot detection according to the present invention.
When the detection signal received by the detection logic control chip 22 is a power pin detection signal, the detection logic control chip 22 will respectively measure the voltage of the power pins of the pci express slot 13 to generate second detection result information, the detection program will determine whether the voltage measured by the power pins in the second detection result information meets the voltage range specified by PCIe, and the detection program can detect whether the power pins of the pci express slot 13 are normally powered.
When the detection signal received by the detection logic control chip 22 is a power pin detection signal, the detection logic control chip 22 will respectively measure the voltage of the power pins of the pci express slot 13 to generate second detection result information, the detection program will determine whether the voltage measured by the power pins in the second detection result information meets the voltage range specified by PCIe, and the detection program can detect whether the power pins of the pci express slot 13 are normally powered.
The PCI express control chip 21 detects and stores the PCIe transmission speed and the PCIe transmission bandwidth in a temporary storage when the detection circuit board 20 is inserted in the PCI express slot 13 through the PCI express interface 21, the detection logic control chip 22 obtains the PCIe transmission speed and the PCIe transmission bandwidth from the temporary storage to generate a second detection result, the PCI express control chip 21 controls the switching of the PCIe transmission speed according to the detection signal and generates a first detection result according to the PCIe connection state after the PCIe transmission speed is switched, and the detection program can detect whether the PCIe transmission speed, the PCIe transmission bandwidth and the PCIe transmission speed switching of the PCI express slot 13 conform to the PCIe specification or not.
Referring to fig. 4A and 4B, fig. 4A is a schematic diagram illustrating a system management bus Master mode detection for pci express slot detection according to the present invention; FIG. 4B is a schematic diagram illustrating detection of a system management bus Slave mode for PCI express slot detection according to the present invention.
In the Master mode detection of the system management bus, the detection logic control chip 22 is set to the I2C Master detection state according to the detection signal, the detection logic control chip 22 obtains the address of the I2C device on the motherboard 10, the detection logic control chip 22 reads or writes the I2C address space, and the detection program determines the availability of the SMBus according to the success or failure of the reading or writing of the I2C address space.
In the Slave mode detection of the system Management bus, the first embodiment is applicable only, and the detection program accesses a Board Management Controller (BMC) of the main board or an SMBus Controller on the ICH, and the SMBus Controller accesses the EEPROM emulated by the detection logic control chip 22, and verifies the availability of the SMBus bus by reading and writing the EEPROM.
Referring to FIG. 5, FIG. 5 is a schematic diagram illustrating wake-up detection for PCI express slot detection according to the present invention.
The wake-up detection includes an IO mode and a Function mode, where the Function mode is adapted to a scenario that the motherboard 10 reads the wake-up state through the BMC, or the motherboard 10 has more than one PCIe slot, and the PCIe slots are wakened together, the first detection logic control chip 221 sends the wake-up signal, the BMC of the motherboard 10 reads the wake-up state, or the second detection logic control chip 222 sends the wake-up signal, and the BMC of the motherboard 10 reads the wake-up state, or the first detection logic control chip 221 reads the wake-up state for detection.
Referring to fig. 6, fig. 6 is a schematic view illustrating an IO detection model for pci express socket detection according to the present invention.
JTAG includes TMS, TDI, TDO, and TCK, and the signals of JTAG, PWRBRK, and CLKREQ all use an IO detection model, which is shown in fig. 6, that is, when an IO of the detection logic control chip 22 is connected to any pin, the detection logic control chip 22 can control two resistors connected to the pin to be set as a pull-up resistor and a pull-down resistor, respectively. The detection logic control chip 22 can determine that the detected pin is in the H/L/NC state by controlling the pull-up state, the pull-down state, and the no pull-up state, and reading the status signal of the IO.
In summary, it can be seen that the difference between the present invention and the prior art is that the pci express control chip transmits a detection signal from the pci express interface to detect the pci express slot and generate first detection result information, transmits the first detection result information to the detection program through the pci express slot, transmits a detection signal from the pci express interface to perform detection control according to the detection signal and perform detection logic setting to detect the pci express slot and generate second detection result information, and transmits the second detection result information to the detection program through the pci express slot.
The technical means can solve the problem that the existing detection for the standard PCI express slot can not provide each pin detection in the prior art, thereby achieving the technical effect of individual detection for the pins of the PCI express slot.
Although the embodiments of the present invention have been described, the description is not intended to limit the scope of the invention. Workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the disclosure. The scope of the present invention is defined by the appended claims.
Claims (10)
1. A pci express socket inspection system, comprising:
the detection system comprises a mainboard, a detection unit and a detection unit, wherein the mainboard is provided with a Central Processing Unit (CPU), a memory and a peripheral component interconnect express (PCIe) slot, a detection program is stored in the memory, the CPU loads and executes the detection program from the memory to generate a detection signal, and the detection program transmits the detection signal, first detection result information and second detection result information through the PCIe slot;
a detection circuit board inserted into the PCI express slots through a PCI express interface, the detection circuit board further comprising:
the PCI express control chip is electrically connected with the PCI express interface directly through a switch, transmits the detection signal from the PCI express interface to detect the PCI express slot and generate the first detection result information, and transmits the first detection result information to the detection program through the PCI express slot; and
the detection logic control chip is electrically connected with the rapid peripheral component interconnection interface directly through a switch, the detection logic control chip is electrically connected with the rapid peripheral component interconnection control chip directly through the switch, the detection signals are transmitted from the rapid peripheral component interconnection interface to carry out detection control according to the detection signals and carry out detection logic setting so as to detect the rapid peripheral component interconnection slot and generate second detection result information, and the second detection result information is transmitted to the detection program through the rapid peripheral component interconnection slot.
2. The PCI express slot detection system of claim 1, wherein detecting the PCI express slot comprises power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switch detection, SMBus detection, wake-up detection, JTAG detection, PWRBRK detection, and CLKRREQ detection.
3. The PCI express slot inspection system of claim 1, wherein the PCI express control chip detects and stores PCIe transmission speed and PCIe transmission bandwidth in a register when the inspection circuit board is inserted into the PCI express slot through the PCI express interface, and the inspection logic control chip obtains the PCIe transmission speed and PCIe transmission bandwidth from the register to generate the second inspection result.
4. The PCI express slot detection system of claim 1, wherein the PCI express control chip controls the switching of the PCIe transmission speed according to the detection signal, and generates the PCIe connection status after the PCIe transmission speed is switched as the first detection result.
5. The PCI express slot detection system of claim 1, wherein the detection logic control chip electrically connects the I/O pins of the detection logic control chip with the pin settings of the PCI express slot to be detected according to the detection signal, and the detection logic control chip sets the two resistors connected to the I/O pins of the detection logic control chip to be pull-up resistors and pull-down resistors, and the detection logic control chip controls the I/O pins of the detection logic control chip to be pull-up state, pull-down state and no pull-up pull-down state to detect the pin settings of the PCI express slot to be detected.
6. An external connection standard socket inspection system, comprising:
a motherboard having a peripheral component interconnect express (PCIe) slot;
a detection circuit board inserted into the PCI express slots through a PCI express interface, the detection circuit board further comprising:
the rapid peripheral component interconnection control chip is electrically connected with the rapid peripheral component interconnection interface directly through a switch, receives a detection signal to detect the rapid peripheral component interconnection slot and generates first detection result information;
the detection logic control chip is electrically connected with the rapid peripheral component interconnection interface directly through a switch, receives the detection signal to carry out detection control according to the detection signal and carries out detection logic setting so as to detect the rapid peripheral component interconnection slot and generate second detection result information;
the PCI express switching connector and the PCI express control chip are directly electrically connected with each other through a first UART-to-RS-232 interface chip, the PCI express switching connector transmits the detection signal to the PCI express control chip, and the PCI express switching connector transmits the first detection result information; and
the detection logic connection connector is electrically connected with the detection logic control chip through a second UART-to-RS-232 interface chip, transmits the detection signal to the detection logic control chip, and transmits the second detection result information; and
the detection device executes a detection program to generate the detection signal, the detection device is electrically connected with the PCI express packet switch connector and the detection logic connection connector respectively, the detection program transmits the detection signal through the PCI express packet switch connector and the detection logic connection connector respectively, the detection program transmits the first detection result information through the PCI express packet switch connector, and the detection program transmits the second detection result information through the detection logic connection connector.
7. The PCI express slot detection system of claim 6, wherein performing detection on the PCI express slot comprises power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switch detection, SMBus detection, wake-up detection, JTAG detection, PWRBRK detection, and CLKRREQ detection.
8. The PCI express slot inspection system of claim 6, wherein the PCI express control chip detects and stores PCIe transmission speed and PCIe transmission bandwidth in a register when the inspection circuit board is inserted into the PCI express slot through the PCI express interface, and the inspection logic control chip obtains the PCIe transmission speed and PCIe transmission bandwidth from the register to generate the second inspection result.
9. The PCI express slot detection system of claim 6, wherein the PCI express control chip controls the PCIe transmission speed to switch according to the detection signal, and generates the PCIe connection status after the PCIe transmission speed is switched as the first detection result.
10. The PCI express slot detection system of claim 6, wherein the detection logic control chip electrically connects the I/O pins of the detection logic control chip with the pin settings of the PCI express slot to be detected according to the detection signal, and the detection logic control chip sets two resistors connected to the I/O pins of the detection logic control chip as a pull-up resistor and a pull-down resistor, and the detection logic control chip controls the I/O pins of the detection logic control chip to be in a pull-up state, a pull-down state and a no pull-up pull-down state to detect the pin settings of the PCI express slot to be detected.
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| CN114218030A (en) * | 2021-12-24 | 2022-03-22 | 苏州浪潮智能科技有限公司 | A central processing unit testing method and device |
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