CN113783553B - A digitally controlled oscillator based on dynamic phase selection and a clock generation method thereof - Google Patents
A digitally controlled oscillator based on dynamic phase selection and a clock generation method thereof Download PDFInfo
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- CN113783553B CN113783553B CN202111084728.3A CN202111084728A CN113783553B CN 113783553 B CN113783553 B CN 113783553B CN 202111084728 A CN202111084728 A CN 202111084728A CN 113783553 B CN113783553 B CN 113783553B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
本发明的目的在于提供一种基于动态相位选择的数字控制振荡器及其时钟产生方法。本发明所提供的数字控制振荡器可以接收非多相的时钟信号，这个时钟信号可以是一个差分时钟信号，通过数字控制字向数字控制振荡器分配时钟调节要求，数字控制振荡器根据数字控制字可以动态地调节接收到的差分时钟信号的相位，以输出目标时钟信号。本发明减少了对芯片面积、功耗以及设计要求，降低了制造成本，具有优异的市场应用前景。
The purpose of the present invention is to provide a digital controlled oscillator based on dynamic phase selection and a clock generation method thereof. The digital controlled oscillator provided by the present invention can receive a non-multi-phase clock signal, which can be a differential clock signal. The clock adjustment requirement is allocated to the digital controlled oscillator through a digital control word. The digital controlled oscillator can dynamically adjust the phase of the received differential clock signal according to the digital control word to output a target clock signal. The present invention reduces the chip area, power consumption and design requirements, reduces the manufacturing cost, and has excellent market application prospects.
Description
Technical Field
The invention relates to the technical field of oscillators, in particular to a digital control oscillator based on dynamic phase selection and a clock generation method thereof.
Background
Digitally controlled oscillators (NCO) are important components of software radio, direct data frequency synthesizer (DDS), fast Fourier Transform (FFT), etc., and are also one of the main factors determining their performance for generating controllable sine or cosine waves. With the improvement of chip integration level, the method is widely applied to the fields of signal processing, digital communication, modulation and demodulation, variable frequency speed regulation, guidance control, power electronics and the like.
Prior art digitally controlled oscillators typically require the generation of a multi-phase clock input to a phase selection means by means of a multi-phase clock generator and a combination of e.g. a delay locked loop, a phase locked loop, an oscillator, or other generating means that can generate a multi-phase clock to generate a target clock signal. Therefore, the load workload of the chip carrying the digital control oscillator is large, the power consumption is large, the required chip area is large, and the design and manufacturing cost is high.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks, an object of the present invention is to provide a digitally controlled oscillator based on dynamic phase selection and a clock generation method thereof. The digital control oscillator provided by the invention can receive a non-multiphase clock signal, the clock signal can be a differential clock signal, the digital control oscillator distributes clock adjustment requirements to the digital control oscillator through the digital control word, and the digital control oscillator can adjust the phase of the received differential clock signal according to the digital control word so as to output a target clock signal. In addition, the digital control oscillator of the invention further comprises a calibration device which can calibrate the clock signal generated by the digital control oscillator in real time and inform the digital control oscillator to adjust the clock signal with errors, and can also generate an error lookup table to be provided to the digital control oscillator.
An aspect of the present invention provides a digitally controlled oscillator, including a first input terminal, a second input terminal, and an output terminal, and further including a phase adjustment module and a dynamic phase calculation and clock edge control module, where the phase adjustment module is connected to the first input terminal and the output terminal, and is configured to receive a first clock input from the first input terminal, and further configured to adjust a phase of the first clock according to a control signal generated by the dynamic phase calculation and clock edge control module to obtain a second clock, and output the second clock through the output terminal; the dynamic phase calculation and clock edge control module is connected with the second input end and the output end, and is used for receiving the digital control word input from the second input end, outputting a second clock from the output end, generating the control signal according to the digital control word and the second clock, and sending the control signal to the phase adjustment module.
In some preferred embodiments, in the digitally controlled oscillator, the dynamic phase calculation and clock edge control module is further configured to read first position information of a last clock edge in the second clock, calculate second position information of a next clock edge according to the first position information and the digital control word, and generate a control signal including the second position information.
In some preferred embodiments, in the digitally controlled oscillator, the dynamic phase calculating and clock edge controlling module is further configured to read rising edge position information of a last clock edge in the second clock, calculate rising edge position information of a next clock edge according to the rising edge position information and the digital control word, and generate a control signal including the rising edge position information, and the phase adjusting module is further configured to adjust a phase of the first clock to generate a rising edge of the second clock at a rising edge position corresponding to the rising edge position information, calculate falling edge position information according to a preset signal delay policy and the rising edge position information, and adjust a phase of the first clock to generate a falling edge of the second clock at a falling edge position corresponding to the falling edge position information.
In some preferred embodiments, when the digitally controlled oscillator is in an initial condition, the phase adjustment module is configured to generate a clock edge of a second clock at a position of a preset first clock edge according to position information of the first clock edge, and output the second clock through the output terminal.
In some preferred embodiments, the digitally controlled oscillator further includes an output stage, where the output stage is connected to the output terminal and is configured to shape the second clock output by the output terminal.
In some preferred embodiments, the phase adjustment module includes a current mode phase adjustment unit or a voltage mode phase adjustment unit in the digitally controlled oscillator.
In some preferred embodiments, the digitally controlled oscillator further includes a clock adjustment module, where the clock adjustment module is connected to the first input terminal, and is configured to receive and adjust a frequency of an original clock, so as to generate the first clock and input the first clock to the phase adjustment module through the first input terminal.
In some preferred embodiments, the clock adjustment module in the digitally controlled oscillator includes a phase locked loop, a clock frequency division module, or a clock multiplication module.
In some preferred embodiments, the digital control oscillator further includes a calibration module, where the calibration module is connected between an output end of the digital control oscillator and the phase adjustment module, and is configured to receive a calibration clock and a second clock, determine whether a phase error exists in the second clock by comparing the calibration clock with the second clock, and generate a phase adjustment policy according to a comparison result, so as to notify the phase adjustment module to adjust the second clock.
In some preferred embodiments, in the digitally controlled oscillator, the calibration module includes a measurement unit and a calibration unit connected to the measurement unit, where the measurement unit is further connected to the output end, and configured to receive the calibration clock and the second clock, and compare the calibration clock and the second clock to determine whether a phase error exists in the second clock, and the calibration unit is further connected to the phase adjustment module, and is configured to generate a phase adjustment policy according to a comparison result of the measurement unit, and send the phase adjustment policy to the phase adjustment module.
In some preferred embodiments, in the digitally controlled oscillator, the phase adjustment strategy is an error lookup table including at least one adjustment strategy corresponding to clock information of a second clock, and the calibration module further includes a lookup table unit configured to generate an error lookup table according to the phase adjustment strategy and the clock information of the second clock corresponding to the phase adjustment strategy, and send the error lookup table to the phase adjustment module; the phase adjustment module comprises a storage unit, a retrieval unit and an adjustment unit, wherein the storage unit is used for storing the error lookup table, the retrieval unit is used for retrieving a corresponding adjustment strategy from the error lookup table according to clock information of the second clock, and the adjustment unit is used for adjusting the second clock according to the adjustment strategy.
In some preferred embodiments, the digitally controlled oscillator is applied to a phase locked loop, the phase locked loop being connected to the output and the second input, the phase locked loop generating the digital control word from the second clock and a reference clock.
In some preferred embodiments, the phase-locked loop is a digital phase-locked loop including a digital phase-frequency detector, a digital filter and a digital frequency divider, wherein the digital frequency divider is connected to the digital phase-frequency detector and the output terminal, and is configured to generate a feedback clock according to a second clock output by the output terminal, the digital phase-frequency detector is further connected to the digital filter, and is configured to receive a reference clock and the feedback clock, calculate a frequency and/or a phase difference between the feedback clock and the reference clock, and send the calculated frequency and/or phase difference to the digital filter, and the digital filter is further connected to the second input terminal, and is configured to generate the digital control word according to the frequency and/or the phase difference, and send the digital control word to the second input terminal.
In some preferred embodiments, the phase-locked loop is a digital-analog hybrid phase-locked loop including a phase-frequency detector, an analog filter, an analog-digital converter, and a frequency divider, where the frequency divider is connected to the phase-frequency detector and the output end, and is configured to generate a feedback clock according to a second clock output by the output end, and the phase-frequency detector is further connected to the analog filter, and is configured to receive a reference clock and the feedback clock, calculate a frequency and/or a phase difference between the feedback clock and the reference clock, and send the frequency and/or the phase difference to the analog filter, and the analog filter is further connected to the analog-digital converter, and is further configured to perform filtering processing on the frequency and/or the phase difference, and the analog-digital converter is further connected to the second input end, and is configured to generate a digital control word according to the frequency and/or the phase difference, and send the digital control word to the second input end.
In another aspect, the present invention also provides a clock generating method based on a digitally controlled oscillator, which includes the steps of: the phase adjusting module receives a first clock from a first input end and adjusts the first clock according to a control signal to obtain a second clock; the dynamic phase calculation and clock edge control module receives a digital control word from a second input end; the dynamic phase calculation and clock edge control module receives the second clock from an output end; the dynamic phase calculation and clock edge control module generates a control signal according to the digital control word and the second clock and sends the control signal to the phase adjustment module; the phase adjusting module adjusts the phase of the first clock according to the control signal to obtain a second clock; and outputting the second clock through the output end.
In some preferred embodiments, in the clock generation method, the step of generating the control signal by the dynamic phase calculation and clock edge control module according to the digital control word and the second clock includes: the dynamic phase calculation and clock edge control module reads the first position information of the last clock edge in the second clock, calculates the second position information of the next clock edge according to the first position information and the digital control word, and generates a control signal containing the second position information.
In some preferred embodiments, in the clock generating method, the dynamic phase calculating and clock edge control module generates a control signal according to the digital control word and the second clock, the phase adjusting module adjusts the phase of the first clock to obtain the second clock according to the control signal, the dynamic phase calculating and clock edge control module reads rising edge position information of a last clock edge in the second clock, calculates rising edge position information of a next clock edge according to the rising edge position information and the digital control word, and generates a control signal including the rising edge position information, and the phase adjusting module adjusts the phase of the first clock to generate a rising edge of the second clock at a rising edge position corresponding to the rising edge position information according to the control signal, and the phase adjusting module further calculates falling edge position information according to a preset signal delay strategy and the rising edge position information and adjusts the phase of the first clock to generate a falling edge of the second clock at a falling edge position corresponding to the falling edge position information.
In some preferred embodiments, in the clock generating method, when the digitally controlled oscillator is in an initial condition, the phase adjusting module generates a clock edge of a second clock at a preset first clock edge position according to position information of the first clock edge position, and outputs the second clock through the output terminal.
In some preferred embodiments, the clock generating method further includes, an output stage receiving a second clock output from the output terminal, and shaping the second clock.
In some preferred embodiments, the clock generating method further includes, the phase adjusting module includes a current mode phase adjusting unit or a voltage mode phase adjusting unit, and the phase of the clock signal is adjusted by current or voltage adjustment.
In some preferred embodiments, the clock generating method further includes a clock adjustment module receiving and adjusting a frequency of an original clock to generate the first clock and inputting the first clock to the phase adjustment module through the first input terminal.
In some preferred embodiments, in the clock generating method, the clock adjusting module includes a phase-locked loop, a clock frequency dividing module, or a clock frequency doubling module.
In some preferred embodiments, the clock generating method further includes a clock calibrating step, in which the calibrating module receives the calibrating clock and the second clock, and determines whether the second clock has a phase error by comparing the calibrating clock with the second clock, and generates a phase adjustment policy according to a comparison result, so as to inform the phase adjusting module to adjust the second clock.
In some preferred embodiments, in the clock generating method, the phase adjustment policy is an error lookup table including at least one adjustment policy corresponding to clock information of a second clock, the error lookup table is stored in the phase adjustment module, the phase adjustment module retrieves the corresponding adjustment policy from the error lookup table according to the clock information of the second clock, and the phase adjustment module adjusts the second clock according to the adjustment policy.
In some preferred embodiments, the clock calibration method in the clock generation method includes the steps of:
s001: the calibration module obtains a second clock and a calibration clock,
S002: acquiring and recording clock information of the second clock, inquiring whether to traverse all the second clocks to be calibrated,
S003: generating an error lookup table when all second clocks to be calibrated have been traversed;
when not all the second clocks to be calibrated have been traversed, step S004 is performed,
S004: comparing the calibration clock with the second clock, judging whether the second clock has phase error,
S005: when the second clock has no phase error, step S001 is performed,
When the second clock has phase error, generating an adjustment strategy and sending the adjustment strategy to the phase adjustment module, recording and correlating the adjustment strategy and the second clock information,
S006: acquiring a second clock regulated by the phase regulating module according to the regulating strategy,
S007: comparing the calibration clock with the adjusted second clock, judging whether the adjusted second clock has a phase error,
S008: storing the recorded data with the second clock when the adjusted second clock has no phase error
The adjustment strategy associated with the information is executed, and step S001 is executed;
When the adjusted second clock has a phase error, the adjustment strategy is updated and sent to the phase adjustment module, the adjustment strategy associated with the second clock information is updated and recorded, and step S006 is executed.
In some preferred embodiments, the clock calibration method determines that the second clock or the adjusted second clock has no phase error when the phase difference is not greater than a threshold value when the phase difference is greater than the threshold value, and determines that the second clock or the adjusted second clock has a phase error when the phase difference is greater than the threshold value.
After the technical scheme is adopted, compared with the prior art, the method has the following beneficial effects:
1. The digital control oscillator and the clock generation method thereof can dynamically adjust the clock phase based on the non-multiphase clock signal, thereby meeting various application requirements;
2. the calibrating device and the clock calibrating method thereof can dynamically calibrate the clock signal, can also generate an error lookup table, and improve the calibrating efficiency;
3. the digital control oscillator and the calibration device thereof reduce the chip area and the design requirement, reduce the manufacturing cost and have excellent market application prospect.
Drawings
FIG. 1 is a schematic diagram of a digitally controlled oscillator according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a current mode phase adjustment circuit according to a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of a voltage mode phase adjustment circuit according to a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of another digitally controlled oscillator according to a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a digitally controlled oscillator including a calibration module according to a preferred embodiment of the present invention;
FIG. 6 is a schematic diagram of a digitally controlled oscillator for use in a phase locked loop according to a preferred embodiment of the present invention;
FIG. 7 is a schematic diagram of another digitally controlled oscillator for use in a phase locked loop according to a preferred embodiment of the present invention;
FIG. 8 is a flow chart of a method for generating a clock of a digitally controlled oscillator according to a preferred embodiment of the present invention;
FIG. 9 is a diagram of a dynamically selected phase generating clock signal in accordance with a preferred embodiment of the present invention;
FIG. 10 is a flow chart of a method for calibrating a clock of a digitally controlled oscillator according to a preferred embodiment of the present invention;
fig. 11 is a flowchart of another clock calibration method of a digitally controlled oscillator according to a preferred embodiment of the present invention.
Detailed Description
Advantages of the invention are further illustrated in the following description, taken in conjunction with the accompanying drawings and detailed description.
It should be understood, however, that this disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather should be provided to provide a more thorough and complete understanding of the disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". Other explicit and implicit definitions are also possible below.
Referring to fig. 1, a schematic diagram of a digitally controlled oscillator according to a preferred embodiment of the present invention is shown. As can be seen from the figure, the digitally controlled oscillator provided in this embodiment mainly includes: the first input end is connected with the phase adjusting module of the first input end, the phase adjusting module is also connected with the output end and the dynamic phase computing and clock edge control module, and the dynamic phase computing and clock edge control module is also connected with the output end and the second input end. Based on the above structural design, a first clock can be input to the digitally controlled oscillator through the first input end, wherein the first clock is a non-multiphase clock, preferably a differential clock, which comprises a pair of clock signals with opposite phases and has excellent external interference resistance; the phase adjustment module may receive the first clock from the first input terminal, and in addition, the phase adjustment module may also receive a control signal from the dynamic phase calculation and clock edge control module, so that the phase adjustment module may adjust the phase of the first clock according to the control signal to obtain a second clock having the target frequency and phase; in this embodiment, a digital control word including target frequency and/or phase information may be input to the digitally controlled oscillator through a second input terminal, and the dynamic phase calculation and clock edge control module connected to the second input terminal may receive the digital control word from the second input terminal, and receive a second clock from the output terminal, and generate the control signal according to the digital control word and the second clock to send to the phase adjustment module for adjusting the first clock. Preferably, when the digitally controlled oscillator is in an initial condition, i.e. is powered on, the phase adjustment module adjusts the phase of the received first clock according to a preset control command to generate the second clock. Wherein, preferably, the first clock and the second clock may have the same or different frequencies.
It should be understood that the term "first clock" as referred to in this embodiment as well as other embodiments of the present invention refers to a clock that is not output from a digitally controlled oscillator, while the term "second clock" refers to a clock that is output from a digitally controlled oscillator. Based on the digitally controlled oscillator provided in this embodiment, the "first clock" may be adjusted cumulatively and multiply, while the "second clock" may be any one of the clocks obtained by adjusting the "first clock" at any one time. In some embodiments of the present invention, there are also cases where "second clock" is used to represent "first clock", and those skilled in the art can fully distinguish from the description of specific embodiments.
Based on the above embodiment, it can be seen that the digitally controlled oscillator provided by the invention can be implemented, and based on the controllable digital control word and the feedback second clock, the non-multiphase clock is controllably phase-adjusted multiple times, so as to obtain the target clock meeting the requirement. Therefore, the calculation workload of the chip carrying the digital control oscillator is reduced, the power consumption of the chip is reduced, the area requirement on the chip is further reduced, and the design and manufacturing cost of the chip is reduced.
In some embodiments, the dynamic phase calculation and clock edge control module in the digitally controlled oscillator is further configured to read the first position information of the last clock edge in the second clock, calculate the second position information of the next clock edge according to the first position information and the digital control word, and generate a control signal including the second position information. The last clock edge here refers to the clock edge of the second clock that was generated prior to the current clock phase adjustment of the digitally controlled oscillator. The clock edge refers to a signal state generated due to level transitions of the digital clock signal, including a rising edge, indicating that the clock signal transitions from a low level to a high level; the falling edge indicates that the clock signal transitions from a high level to a low level, and thus the last clock edge here may be the last rising edge or the last falling edge. The digital control word may be a clock frequency control word of the required clock, and may be defined as an integer or fractional format according to the actual requirements.
In an embodiment consistent with the present invention, the precision control parameter of the digitally controlled oscillator may be set to M, where the precision control parameter M may be set by a person skilled in the art according to an actual application environment, and the minimum period factor of the clock generated by the digitally controlled oscillator is a phase step P, which depends on the precision control parameter M and the frequency of the input first clock, that is, p=1/(m×fin), the period tout=p×dcw of the second clock, if the first position information of the last clock edge is set to edge (n), the second position information of the next clock edge is set to edge (n+1), edge (n+1) =edge (n) +k×p×dcw, where K is a constant, and the working parameter of the digitally controlled oscillator is set according to an actual requirement, and if edge (n) is rising edge position information, edge (n+1) is rising edge position information in the next clock period, and if edge (n+1) is falling edge position information in the next clock period; when K is equal to a fraction, if edge (n) is rising edge position information, edge (n+1) is falling edge position information (edge' (n)) in the same clock cycle, and if edge (n) is falling edge position information, edge (n+1) is rising edge position information in the next clock cycle. Based on the above strategy, the dynamic phase calculation and clock edge control module in the digital control oscillator can calculate the first position information edge (n) of the last clock edge from the second clock received by the output end, and receive the digital control word from the second input end, and calculate the position information edge (n+1) of the next clock edge, thereby obtaining the clock signal with the required frequency and phase.
In order to better understand the implementation manner of the above technical solution of the present invention, some more specific embodiments are provided herein, for example, the accuracy control parameter m=32, the working parameter k=1, the frequency fin=1ghz of the first clock of the digitally controlled oscillator may be set, where the phase step p=1/(m×fin) =0.03125 ns of the clock generated by the digitally controlled oscillator, and when a digital control word dcw=40 is input, the clock period tout=1.25 ns of the second clock generated by the digitally controlled oscillator, and the clock frequency fout=1/tout=800 Mhz may be used in any scenario requiring the clock frequency 800 Mhz. It should be understood that, according to actual requirements, the skilled person can set the accuracy control parameter M and the digital control word to any value satisfying the actual requirements, for example, m=1000, 1000, 80, 40, 32, 30, 20, 10, 1, 0.8, 0.4, 0.2, 0.01, 0.001, etc., dcw=100, 80, 40, 20.5, 9, 3, 1, 0.5, 0.01, etc.
In some embodiments, the dynamic phase calculation and clock edge control module in the digitally controlled oscillator is further configured to read rising edge position information of a last clock edge in the second clock, calculate rising edge position information of a next clock edge according to the rising edge position information and the digital control word, and generate a control signal including the rising edge position information; the phase adjusting module is further used for adjusting the phase of the first clock to generate a rising edge of the second clock at a rising edge position corresponding to the rising edge position information, calculating falling edge position information according to a preset signal delay strategy and the rising edge position information, and adjusting the phase of the first clock to generate a falling edge of the second clock at a falling edge position corresponding to the falling edge position information.
For example, referring to fig. 9, the position information of the rising edge of the last clock edge is edge (n), and the received digital control word is DCW, then the position information of the rising edge of the next clock edge may be edge (n+1) =edge (n) +kdcw×p, where k=1, and edge (n+1) is always the position information of the rising edge in the next clock cycle, that is, the position information of the falling edge is not calculated any more in this embodiment. In this embodiment, the position information of the falling edge does not need to be calculated, but can be calculated according to a signal delay strategy, so that the workload of the dynamic phase calculation and clock edge control module is reduced, and the design and manufacturing cost is reduced.
In some embodiments, when the digitally controlled oscillator is in the initial condition, the phase adjustment module is configured to generate a clock edge of the second clock at the first clock edge position according to the position information of the preset first clock edge position, and output the second clock through the output terminal. The digitally controlled oscillator may thus be started to dynamically and cyclically phase adjust to obtain a clock signal meeting frequency and/or phase requirements.
In some embodiments, the digitally controlled oscillator further includes an output stage, where the output stage is connected to the output end, and the output stage may perform shaping processing on the second clock output by the output end to obtain a clock signal with a waveform meeting an application requirement, so as to improve an application field and an application range of the generated clock signal. Preferably, the output stage in the present embodiment may be any output stage circuit capable of realizing the above-described functions.
In some embodiments, the phase adjustment module of the digitally controlled oscillator may include a current mode phase adjustment unit or a voltage mode phase adjustment unit, and preferably referring to fig. 2 and 3, the current mode phase adjustment unit or the voltage mode phase adjustment unit may be a current mode phase adjustment circuit or a voltage mode phase adjustment circuit, based on which the present embodiment may implement adjustment of the phase of the clock signal through current or voltage adjustment.
Referring to fig. 4, in some embodiments, the digitally controlled oscillator further includes a clock adjustment module, preferably, the clock adjustment module includes a phase locked loop, a clock frequency division module, or a clock frequency multiplication module, and the clock adjustment module is connected to the first input terminal, so that the original clock generated by the clock generating device is first input to the clock adjustment module before being input to the first input terminal, and the clock adjustment module obtains a first clock with a required frequency by adjusting the frequency of the original clock, and the first clock is input to the phase adjustment module through the first input terminal for being used by subsequent phase adjustment.
Referring to fig. 5, in some embodiments, the digitally controlled oscillator further includes a calibration module, where the calibration module is connected between an output end of the digitally controlled oscillator and the phase adjustment module, and is capable of receiving a calibration clock and a second clock generated by the digitally controlled oscillator, determining whether a phase error exists in the second clock generated by the digitally controlled oscillator by comparing the calibration clock with the second clock, and generating a phase adjustment strategy according to a comparison result, so as to inform the phase adjustment module to adjust the second clock. It may be preferable that when the comparison result shows that there is a phase difference between the second clock and the calibration clock, and the phase difference is not greater than a threshold value, the phase difference is negligible, and the second clock is considered to have no phase error; when the phase difference between the second clock and the calibration clock is greater than the threshold, the second clock is considered to have a phase error, in which case the calibration module generates a phase adjustment strategy based on the phase difference between the second clock and the calibration clock, which may enable the phase adjustment module to adjust the first clock according to the phase adjustment strategy to obtain a second clock with the phase error removed.
In some embodiments, the calibration module includes a measurement unit and a calibration unit connected to the measurement unit, where the measurement unit is further connected to an output end of the digitally controlled oscillator, so that the measurement unit may receive the second clock generated by the digitally controlled oscillator and a calibration clock, and the measurement unit may determine whether a phase error exists in the second clock by comparing the calibration clock with the second clock; the calibration unit is further connected to a phase adjustment module of the digitally controlled oscillator, and the calibration unit can generate a phase adjustment strategy according to the comparison result of the measurement unit, where the phase adjustment strategy can enable the phase adjustment module to adjust the first clock according to the phase adjustment strategy, so as to obtain the second clock with the phase error eliminated.
In some embodiments, the phase adjustment strategy is an error lookup table including at least one adjustment strategy corresponding to clock information of the second clock, in which case the calibration module further includes a lookup table unit, and the lookup table unit may generate an error lookup table according to the phase adjustment strategy generated by the phase calibration unit and the clock information of the second clock corresponding to the phase adjustment strategy, and may send the error lookup table to the phase adjustment module. When the phase adjustment module adjusts the first clock to obtain the second clock, the phase adjustment module searches the error lookup table according to the clock information of the second clock to determine whether the second clock has a phase error, and can adjust the first clock again according to the corresponding adjustment strategy searched from the error lookup table to obtain the second clock with the phase error eliminated. Preferably, the phase adjustment module in the numerically controlled oscillator further comprises a storage unit, a search unit and an adjustment unit, wherein the storage unit can store the error lookup table, the search unit can search a corresponding adjustment strategy from the error lookup table according to clock information of the second clock, and the adjustment unit can adjust the second clock according to the adjustment strategy searched by the search unit to obtain the second clock with the phase error eliminated.
In some embodiments, the digitally controlled oscillator of the embodiments described above may be applied to a phase locked loop, where the phase locked loop is connected to the output terminal of the digitally controlled oscillator and the second input terminal, and the phase locked loop may be configured to generate a corresponding digital control word according to the second clock generated by the digitally controlled oscillator and the received reference clock, for example, generated by a clock source with a fixed frequency and phase, where the digital control word reflects the required clock frequency and/or phase, and input the digital control word to the digitally controlled oscillator, and may be configured to control the digitally controlled oscillator to generate the second clock signal according to the frequency and/or phase requirements according to the method of the embodiments described above. Therefore, the digital control oscillator provided by the invention can dynamically generate specific clock signals according to specific applications in application, and has flexible application and controllable cost.
Referring to fig. 6, in some embodiments, the phase-locked loop may be a digital phase-locked loop including a digital phase-frequency detector, a digital filter, and a digital frequency divider, where the digital frequency divider is connected to the output terminals of the digital phase-frequency detector and the digitally controlled oscillator, and the digital frequency divider generates the feedback clock according to the second clock output from the output terminal; the digital phase frequency detector is also connected with the digital filter, receives the reference clock and the feedback clock, calculates the frequency and/or the phase difference between the feedback clock and the reference clock, and sends the calculated frequency and/or phase difference to the digital filter, and the digital filter is also connected with the second input end of the digital control oscillator, so that a digital control word can be generated according to the received frequency and/or phase difference and sent to the second input end, and the digital control oscillator is controlled to generate a second clock signal meeting the frequency and/or phase requirements.
Referring to fig. 7, in some embodiments, the phase-locked loop may be a digital-analog hybrid phase-locked loop including a phase frequency detector, an analog filter, a digital-analog-digital converter, and a frequency divider, where the frequency divider is connected to the output ends of the phase frequency detector and the digitally controlled oscillator, and may generate the feedback clock according to the second clock output from the output end; the phase frequency detector is also connected with an analog filter, can receive a reference clock and a feedback clock, calculates and obtains the frequency and/or the phase difference of the feedback clock and the reference clock, so as to send the frequency and/or the phase difference to the analog filter, the analog filter is also connected with an analog-digital converter, can carry out filtering processing on the frequency and/or the phase difference, and the analog-digital converter is also connected with a second input end of a digital control oscillator, and can generate a digital control word according to the frequency and/or the phase difference after the filtering processing so as to send the digital control word to the second input end, thereby realizing the control of the digital control oscillator to generate a second clock signal meeting the frequency and/or the phase requirement.
In another aspect of the present invention, there is also provided a clock generation method based on a digitally controlled oscillator, which can be applied to the digitally controlled oscillator described in the above embodiments. Referring to fig. 8, which is a flow chart of a clock generating method according to a preferred embodiment of the invention, it can be seen that the clock generating method of the present embodiment includes the following steps:
-a phase adjustment module receives a first clock from a first input, adjusts the first clock according to a control signal to obtain a second clock;
-the dynamic phase computation and clock edge control module receives a digital control word from a second input;
-said dynamic phase computation and clock edge control module receiving said second clock from an output;
-said dynamic phase calculation and clock edge control module generating control signals from said digital control word and said second clock and sending to said phase adjustment module;
-the phase adjustment module adjusts the phase of the first clock to obtain a second clock in dependence on the control signal;
-outputting said second clock via said output.
The first clock is a non-multiphase clock, and may preferably be a differential clock.
In some implementations, the step of the dynamic phase computation and clock edge control module generating control signals from the digital control word and the second clock includes:
-the dynamic phase computation and clock edge control module reads first location information of a last clock edge in the second clock;
-said dynamic phase calculation and clock edge control module calculating a second position information of a next clock edge from said first position information and said digital control word and generating a control signal comprising said second position information.
The last clock edge here refers to the clock edge of the second clock that was generated prior to the current clock phase adjustment of the digitally controlled oscillator. The clock edge refers to a signal state generated due to level transitions of the digital clock signal, including a rising edge, indicating that the clock signal transitions from a low level to a high level; the falling edge indicates that the clock signal transitions from a high level to a low level, and thus the last clock edge here may be the last rising edge or the last falling edge. The digital control word is a clock frequency control word of the required clock, and can be defined as an integer or decimal format according to actual requirements. For examples of specific working principles and specific implementations of the dynamic phase calculation and clock edge control module in this embodiment, reference may be made to the detailed description of the digitally controlled oscillator portion, which is not repeated here.
In some embodiments, the dynamic phase calculation and clock edge control module generates a control signal according to the digital control word and the second clock, and the phase adjustment module adjusts the phase of the first clock to obtain the second clock according to the control signal, including:
-the dynamic phase calculation and clock edge control module reads rising edge position information of a last clock edge in the second clock and calculates rising edge position information of a next clock edge from the rising edge position information and the digital control word and generates a control signal comprising the rising edge position information;
-the phase adjustment module adjusts the phase of the first clock to generate a rising edge of a second clock at a rising edge position corresponding to the rising edge position information according to the control signal;
the phase adjustment module calculates falling edge position information according to a preset signal delay strategy and the rising edge position information, and adjusts the phase of the first clock to generate a falling edge of a second clock at a falling edge position corresponding to the falling edge position information.
For examples of specific working principles and specific implementations of the dynamic phase calculation and clock edge control module in this embodiment, reference may be made to the detailed description of the digitally controlled oscillator portion, which is not repeated here.
In some embodiments, when the digitally controlled oscillator is in an initial condition, the phase adjustment module generates a clock edge of a second clock at a preset first clock edge position according to position information of the first clock edge position, and outputs the second clock through the output terminal. The digitally controlled oscillator may thus be started to dynamically and cyclically phase adjust to obtain a clock signal meeting frequency and/or phase requirements.
In some embodiments, the clock generating method further includes the steps of receiving the second clock output from the output terminal by using the output stage, and shaping the second clock to obtain a clock signal with a waveform meeting the application requirement, so that the application field and the application range of the generated clock signal can be improved.
In some embodiments, the phase adjustment module in the applied digitally controlled oscillator comprises a current mode phase adjustment unit or a voltage mode phase adjustment unit, and the adjustment of the phase of the clock signal can be achieved by current or voltage adjustment.
In some embodiments, the clock generating method further includes a step of receiving and adjusting a frequency of an original clock using a clock adjusting module to generate the first clock satisfying application requirements and inputting the first clock to the phase adjusting module through the first input terminal. Preferably, the clock adjustment module may comprise a phase locked loop, a clock frequency division module or a clock multiplication module.
Referring to fig. 10, in some embodiments, the clock generating method further includes a step of receiving a calibration clock and a second clock by using a calibration module, comparing the calibration clock and the second clock to determine whether a phase error exists in the second clock, and generating a phase adjustment policy according to a comparison result to inform the phase adjustment module to adjust the second clock. It may be preferable that when the comparison result shows that there is a phase difference between the second clock and the calibration clock, and the phase difference is not greater than a threshold value, the phase difference is negligible, and the second clock is considered to have no phase error; when the phase difference between the second clock and the calibration clock is greater than the threshold, the second clock is considered to have a phase error, in which case the calibration module generates a phase adjustment strategy based on the phase difference between the second clock and the calibration clock, which may enable the phase adjustment module to adjust the first clock according to the phase adjustment strategy to obtain a second clock with the phase error removed.
In some embodiments, the phase adjustment policy is an error lookup table including at least one adjustment policy corresponding to clock information of a second clock, based on which, if the error lookup table is stored in the phase adjustment module, the phase adjustment module may retrieve the corresponding adjustment policy from the error lookup table according to the clock information of the second clock, and readjust the second clock according to the adjustment policy to obtain a second clock that eliminates the phase error.
Referring to fig. 11, which is a schematic flow chart of a clock calibration method according to a preferred embodiment of the present invention, it can be seen that in some embodiments, the clock calibration method may further include the following steps:
S001: the calibration module acquires a second clock and a calibration clock;
S002: acquiring and recording clock information of the second clocks, and inquiring whether to traverse all the second clocks to be calibrated;
s003: generating an error lookup table when traversing all second clocks to be calibrated;
When all the second clocks to be calibrated are not traversed, executing step S004;
S004: comparing the calibration clock with the second clock, and judging whether the second clock has a phase error or not;
S005: when the second clock has no phase error, performing step S001;
When the second clock has phase error, generating an adjustment strategy and sending the adjustment strategy to the phase adjustment module, recording and correlating the adjustment strategy and the second clock information,
S006: acquiring a second clock regulated by the phase regulating module according to the regulating strategy,
S007: comparing the calibration clock with the adjusted second clock, judging whether the adjusted second clock has a phase error,
S008: storing the recorded adjustment policy associated with the second clock information when the adjusted second clock has no phase error, and executing step S001;
When the adjusted second clock has a phase error, the adjustment strategy is updated and sent to the phase adjustment module, the adjustment strategy associated with the second clock information is updated and recorded, and step S006 is executed.
Based on the above embodiment, it can be seen that the calibration method provided by the present embodiment may further implement pre-calibration of all clock signals generated by the digitally controlled oscillator, and generate an error lookup table so as to be stored in the phase adjustment module of the digitally controlled oscillator, so that, in operation, the phase adjustment module may calibrate and adjust the generated second clock in real time, so that the second clock of the digitally controlled oscillator has no phase error, thereby meeting practical application requirements.
In some embodiments, when the second clock or the adjusted second clock has a phase difference compared with the calibration clock, it is determined that the second clock or the adjusted second clock has no phase error when the phase difference is not greater than a threshold value, and it is determined that the second clock or the adjusted second clock has a phase error when the phase difference is greater than a threshold value. The threshold value can be adjusted according to the actual application requirement so as to meet different requirements on clock precision in different applications.
It should be noted that the embodiments of the present invention are preferred and not limited in any way, and any person skilled in the art may make use of the above-disclosed technical content to change or modify the same into equivalent effective embodiments without departing from the technical scope of the present invention, and any modification or equivalent change and modification of the above-described embodiments according to the technical substance of the present invention still falls within the scope of the technical scope of the present invention.
Claims (24)
1. A digital controlled oscillator comprising a first input terminal, a second input terminal and an output terminal, and further comprising a phase adjustment module and a dynamic phase calculation and clock edge control module, wherein
The phase adjusting module is connected with the first input end and the output end and is used for receiving a first clock input from the first input end and is also used for
Adjusting the phase and/or frequency of the first clock according to the control signal generated by the dynamic phase calculation and clock edge control module to obtain a second clock, outputting the second clock through the output end,
The dynamic phase calculation and clock edge control module is connected with the second input end and the output end, and is used for receiving a digital control word input from the second input end, a second clock output from the output end, and generating the control signal according to the digital control word and the second clock and sending the control signal to the phase adjustment module; the dynamic phase calculation and clock edge control module is further used for reading the first position information of the last clock edge in the second clock, calculating the second position information of the next clock edge according to the first position information and the digital control word, and generating a control signal containing the second position information.
2. The numerically controlled oscillator according to claim 1, wherein,
The dynamic phase calculation and clock edge control module is also used for reading rising edge position information of the last clock edge in the second clock, calculating rising edge position information of the next clock edge according to the rising edge position information and the digital control word, generating a control signal containing the rising edge position information,
The phase adjusting module is further configured to adjust a phase of the first clock to generate a rising edge of the second clock at a rising edge position corresponding to the rising edge position information, calculate falling edge position information according to a preset signal delay strategy and the rising edge position information, and adjust a phase of the first clock to generate a falling edge of the second clock at a falling edge position corresponding to the falling edge position information.
3. The numerically controlled oscillator according to claim 1, wherein,
When the digitally controlled oscillator is in an initial condition,
The phase adjusting module is used for generating a clock edge of a second clock at the first clock edge position according to the position information of the preset first clock edge position and outputting the second clock through the output end.
4. The numerically controlled oscillator according to claim 1, further comprising
And the output stage is connected with the output end and is used for shaping the second clock output by the output end.
5. The numerically controlled oscillator according to claim 1, wherein,
The phase adjustment module comprises a current mode phase adjustment unit or a voltage mode phase adjustment unit.
6. The numerically controlled oscillator according to claim 1, further comprising
And the clock adjusting module is connected to the first input end and is used for receiving and adjusting the frequency of the original clock so as to generate the first clock and input the first clock into the phase adjusting module through the first input end.
7. The numerically controlled oscillator according to claim 6, wherein,
The clock regulating module comprises a phase-locked loop, a clock frequency dividing module or a clock frequency doubling module.
8. The numerically controlled oscillator according to claim 1, further comprising
The calibration module is used for calibrating the calibration module,
The calibration module is connected between the output end of the numerically controlled oscillator and the phase adjustment module, and is used for receiving the calibration clock and the second clock, judging whether the second clock has a phase error by comparing the calibration clock with the second clock, and generating a phase adjustment strategy according to a comparison result so as to inform the phase adjustment module to adjust the second clock.
9. The numerically controlled oscillator according to claim 8, wherein,
The calibration module comprises a measurement unit and a calibration unit connected to the measurement unit, wherein
The measuring unit is further connected to the output end, and is configured to receive the calibration clock and the second clock, and determine whether a phase error exists in the second clock by comparing the calibration clock with the second clock, and the calibrating unit is further connected to the phase adjusting module, and is configured to generate a phase adjustment strategy according to a comparison result of the measuring unit, and send the phase adjustment strategy to the phase adjusting module.
10. The numerically controlled oscillator according to claim 8, wherein,
The phase adjustment strategy is an error look-up table comprising at least one adjustment strategy corresponding to clock information of the second clock,
The calibration module further comprises a lookup table unit for generating an error lookup table according to the phase adjustment strategy and the clock information of the second clock corresponding to the phase adjustment strategy, and sending the error lookup table to a phase adjustment module, wherein the phase adjustment module comprises a storage unit, a retrieval unit and an adjustment unit,
The memory unit is configured to store the error look-up table,
The retrieving unit is configured to retrieve a corresponding adjustment strategy from the error lookup table according to clock information of the second clock,
The adjusting unit is used for adjusting the second clock according to the adjusting strategy.
11. The numerically controlled oscillator according to any one of claims 1 to 10, wherein said numerically controlled oscillator is applied to a phase locked loop,
The phase-locked loop is connected to the output end and the second input end, and the phase-locked loop generates the digital control word according to the second clock and the reference clock.
12. The numerically controlled oscillator according to claim 11, wherein,
The phase-locked loop is a digital phase-locked loop comprising a digital phase-frequency detector, a digital filter and a digital frequency divider, wherein the digital frequency divider is connected with the digital phase-frequency detector and the output end and is used for generating a feedback clock according to a second clock output by the output end,
The digital phase frequency detector is further connected to the digital filter, and is configured to receive a reference clock and the feedback clock, calculate a frequency and/or a phase difference between the feedback clock and the reference clock, and send the calculated frequency and/or the phase difference to the digital filter, and the digital filter is further connected to the second input end, and is configured to generate the digital control word according to the frequency and/or the phase difference, and send the generated digital control word to the second input end.
13. The numerically controlled oscillator according to claim 11, wherein,
The phase-locked loop is a digital-analog hybrid phase-locked loop comprising a phase frequency detector, an analog filter, an analog-digital converter and a frequency divider, wherein
The frequency divider is connected with the phase frequency detector and the output end and is used for generating a feedback clock according to a second clock output by the output end,
The phase frequency detector is also connected with the analog filter and is used for receiving a reference clock and the feedback clock, calculating the frequency and/or the phase difference between the feedback clock and the reference clock and sending the frequency and/or the phase difference to the analog filter, the analog filter is also connected with the analog-digital converter and is used for filtering the frequency and/or the phase difference,
The analog-to-digital converter is further connected to the second input terminal for generating a digital control word according to the frequency and/or the phase difference for transmission to the second input terminal.
14. A clock generation method based on a digitally controlled oscillator, comprising the steps of:
the phase adjusting module receives a first clock from a first input end and adjusts the first clock according to a control signal to obtain a second clock;
The dynamic phase calculation and clock edge control module receives a digital control word from a second input end;
the dynamic phase calculation and clock edge control module receives the second clock from an output end;
The dynamic phase calculation and clock edge control module generates a control signal according to the digital control word and the second clock and sends the control signal to the phase adjustment module;
The phase adjusting module adjusts the phase and/or frequency of the first clock according to the control signal to obtain a second clock;
Outputting the second clock through the output terminal;
the step of the dynamic phase calculation and clock edge control module generating a control signal according to the digital control word and the second clock comprises the following steps:
The dynamic phase calculation and clock edge control module reads the first position information of the last clock edge in the second clock, calculates the second position information of the next clock edge according to the first position information and the digital control word, and generates a control signal containing the second position information.
15. The method of generating a clock as recited in claim 14, wherein,
The dynamic phase calculation and clock edge control module generates a control signal according to the digital control word and the second clock, the phase adjustment module adjusts the phase of the first clock to obtain the second clock according to the control signal,
The dynamic phase calculation and clock edge control module reads rising edge position information of the last clock edge in the second clock, calculates rising edge position information of the next clock edge according to the rising edge position information and the digital control word, generates a control signal containing the rising edge position information,
The phase adjusting module adjusts the phase of the first clock to generate a rising edge of the second clock at the rising edge position corresponding to the rising edge position information according to the control signal,
The phase adjusting module also calculates falling edge position information according to a preset signal delay strategy and the rising edge position information, and adjusts the phase of the first clock to generate a falling edge of the second clock at the falling edge position corresponding to the falling edge position information.
16. The method of generating a clock as recited in claim 14, wherein,
When the digitally controlled oscillator is in an initial condition,
And the phase adjusting module generates a clock edge of a second clock at the first clock edge position according to the position information of the preset first clock edge position, and outputs the second clock through the output end.
17. The clock generation method of claim 14, further comprising
And the output stage receives the second clock output from the output end and performs shaping processing on the second clock.
18. The clock generation method of claim 14, further comprising
The phase adjustment module comprises a current mode phase adjustment unit or a voltage mode phase adjustment unit, and the adjustment of the phase of the clock signal is realized through current or voltage adjustment.
19. The clock generation method of claim 14, further comprising
The clock adjustment module receives and adjusts the frequency of the original clock to generate the first clock and input the first clock to the phase adjustment module through the first input terminal.
20. The method of generating a clock as recited in claim 19, wherein,
The clock regulating module comprises a phase-locked loop, a clock frequency dividing module or a clock frequency doubling module.
21. The clock generation method of claim 14, further comprising the step of clock calibration of:
The calibration module receives the calibration clock and the second clock, compares the calibration clock with the second clock to judge whether the second clock has a phase error, and generates a phase adjustment strategy according to a comparison result to inform the phase adjustment module to adjust the second clock.
22. The method of generating a clock as recited in claim 21, wherein,
The phase adjustment strategy is an error look-up table comprising at least one adjustment strategy corresponding to clock information of the second clock,
The phase adjustment module stores the error look-up table,
The phase adjustment module retrieves a corresponding adjustment strategy from the error lookup table based on clock information of the second clock,
The phase adjustment module also adjusts the second clock according to the adjustment policy.
23. The clock generation method of claim 21, wherein the clock calibration comprises the steps of:
s001: the calibration module obtains a second clock and a calibration clock,
S002: acquiring and recording clock information of the second clock, inquiring whether to traverse all the second clocks to be calibrated,
S003: generating an error lookup table when all second clocks to be calibrated have been traversed;
when not all the second clocks to be calibrated have been traversed, step S004 is performed,
S004: comparing the calibration clock with the second clock, judging whether the second clock has phase error,
S005: when the second clock has no phase error, step S001 is performed,
When the second clock has phase error, generating an adjustment strategy and sending the adjustment strategy to the phase adjustment module, recording and correlating the adjustment strategy and the second clock information,
S006: acquiring a second clock regulated by the phase regulating module according to the regulating strategy,
S007: comparing the calibration clock with the adjusted second clock, judging whether the adjusted second clock has a phase error,
S008: storing the recorded adjustment policy associated with the second clock information when the adjusted second clock has no phase error, and executing step S001;
When the phase error exists in the adjusted second clock, the adjustment strategy is updated and sent to the phase adjustment module, the adjustment strategy associated with the second clock information is updated and recorded, and the steps are executed
S006。
24. The method of generating a clock as recited in claim 21, wherein,
When the second clock or the adjusted second clock has phase difference compared with the calibration clock, then
When the phase difference is not greater than a threshold value, judging that the second clock or the adjusted second clock has no phase error,
And when the phase difference is larger than a threshold value, judging that the second clock or the adjusted second clock has a phase error.
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| US9762252B2 (en) * | 2013-09-16 | 2017-09-12 | Entropic Communications, Llc | Digitally controlled oscillator |
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| CN108270437A (en) * | 2017-01-04 | 2018-07-10 | 京东方科技集团股份有限公司 | Digital controlled oscillator and digital frequency locking ring and phaselocked loop based on digital controlled oscillator |
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