CN113782603B - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising: a gate structure on the substrate of the device region; the source region is positioned in the substrate of the device region at one side of the grid structure; the drain region is positioned in the substrate of the device region at the other side of the grid structure; the bottom dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source region and the drain region; the top dielectric layer is positioned on the bottom dielectric layer and covers the gate structure; the heat dissipation structure is positioned in the top dielectric layer of the isolation region; the heat dissipation structure is positioned on one side of the source region, which is away from the gate structure, or on one side of the drain region, which is away from the gate structure, or on one side of the source region, which is away from the gate structure, and one side of the drain region, which is away from the gate structure; the heat dissipation structure comprises one or more heat conducting layers connected with each other. When the device works, heat generated by the device can be conducted out through the heat dissipation structure, so that the heat dissipation efficiency of the device is improved, the self-heating effect of the device is correspondingly improved, and further the performance of the semiconductor structure is improved.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor , MOSFET) channel length has been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The channel becomes more and more difficult, making subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to reduce the impact of the short channel effect, the semiconductor process gradually begins to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with the planar MOSFET, the gate structure has a stronger ability to control the channel and can well suppress the short channel effect; Moreover, compared with other devices, FinFET has better compatibility with existing integrated circuit manufacturing.

Contents of the invention

The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the self-heating effect of the device, thereby improving the performance of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate including discrete device regions and isolation regions between the device regions; a gate structure located on the substrate of the device regions; a source region, The drain region is located in the substrate of the device region on one side of the gate structure; the drain region is located in the substrate of the device region on the other side of the gate structure; the bottom dielectric layer is located on the substrate at the side of the gate structure and Covering the source region and the drain region; the top dielectric layer is located on the bottom dielectric layer and covers the gate structure; the heat dissipation structure is located in the top dielectric layer of the isolation region; the heat dissipation structure is located on the back of the source region On the side of the gate structure, or on the side of the drain region facing away from the gate structure, or on the side of the source region facing away from the gate structure and the side of the drain region facing away from the gate structure ; The heat dissipation structure includes one or more connected heat conduction layers.

Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, including a plurality of discrete device regions and isolation regions between the device regions, and gates are formed on the substrate of the device regions structure, an active region is formed in the substrate of the device region on one side of the gate structure, a drain region is formed in the substrate of the device region on the other side of the gate structure, and a drain region is formed on the substrate at the side of the gate structure There is a bottom dielectric layer covering the source region and the drain region; a top dielectric layer covering the gate structure and a heat dissipation structure in the top dielectric layer of the isolation region are formed on the bottom dielectric layer; The heat dissipation structure is located on the side of the source region facing away from the gate structure, or on the side of the drain region facing away from the gate structure, or on the side of the source region facing away from the gate structure, and the The side of the drain region facing away from the gate structure; the heat dissipation structure includes one or more connected heat conduction layers.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the semiconductor structure of the embodiment of the present invention, a heat dissipation structure located in the top dielectric layer of the isolation region is also provided; the heat dissipation structure is located on the side of the source region facing away from the gate structure, or located on the side of the drain region facing away from the gate structure, or located on the side of the source region facing away from the gate structure and the drain region facing away from the gate structure; the heat dissipation structure includes one or more layers of connected heat conduction layer; by setting the heat dissipation structure, when the device is working, the heat generated by the device can be conducted out through the heat dissipation structure, thereby improving the heat dissipation efficiency of the device and correspondingly improving the self-heating effect (Self-Heating Effect, SHE) of the device , which in turn is beneficial to improve the performance of the semiconductor structure.

Description of drawings

1 to 10 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Detailed ways

It can be seen from the background art that the current semiconductor technology gradually begins to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides.

However, the fins of the FinFET device have a small width, and the heat generated during the operation of the device is difficult to dissipate through the fins, which easily leads to poor heat dissipation performance of the device, and further leads to poor performance of the device.

In order to solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate including discrete device regions and an isolation region between the device regions; a gate structure located on the substrate of the device region; a source Region, located in the substrate of the device region on one side of the gate structure; drain region, located in the substrate of the device region on the other side of the gate structure; bottom dielectric layer, located in the substrate of the side of the gate structure on and covers the source region and the drain region; a top dielectric layer, located on the bottom dielectric layer and covering the gate structure; a heat dissipation structure, located in the top dielectric layer of the isolation region; the heat dissipation structure is located in the source region facing away from the gate structure, or located on the side of the drain region facing away from the gate structure, or located on the side of the source region facing away from the gate structure and the drain region facing away from the gate structure One side; the heat dissipation structure includes one or more connected heat conduction layers.

In the semiconductor structure of the embodiment of the present invention, a heat dissipation structure is also formed in the top dielectric layer of the isolation region; the heat dissipation structure is located on the side of the source region facing away from the gate structure, or is located on the drain region facing away from the gate structure, or located on the side of the source region facing away from the gate structure and the drain region facing away from the gate structure; the heat dissipation structure includes one or more layers of connected heat conduction layer; by setting the heat dissipation structure, when the device is working, the heat generated by the device can be conducted out through the heat dissipation structure, thereby improving the heat dissipation efficiency of the device and correspondingly improving the self-heating effect (Self-Heating Effect, SHE) of the device , which in turn is beneficial to improve the performance of the semiconductor structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 9 and FIG. 10 together, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown. Wherein, FIG. 9 is a top view, and FIG. 10 is a cross-sectional view at position B-B1 of FIG. 9 .

The semiconductor structure includes: a substrate, including a discrete device region I and an isolation region II between the device regions I; a gate structure 120 (as shown in FIG. 6 ), located on the substrate of the device region I; a source region 130 (as shown in FIG. 6 ), located in the substrate of the device region 1 on one side of the gate structure 120; drain region 140 (as shown in FIG. 6 ), located in the device region on the other side of the gate structure 120 In the base of I; Bottom dielectric layer 150 (as shown in Figure 6), is positioned on the substrate of described gate structure 120 side and covers source region 130 and drain region 140; Top dielectric layer 185, is positioned at described bottom dielectric layer 150 and covering the gate structure 120; the heat dissipation structure 180 is located in the top dielectric layer 185 of the isolation region II; the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120, or , located on the side of the drain region 140 facing away from the gate structure 120, or located on the side of the source region 130 facing away from the gate structure 120 and the side of the drain region 140 facing away from the gate structure 120; the The heat dissipation structure 180 includes one or more layers of connected heat conducting layers 80 .

In the semiconductor structure provided by the embodiment of the present invention, a heat dissipation structure 180 located in the top dielectric layer 185 of the isolation region II is also provided; the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120 , or on the side of the drain region 140 facing away from the gate structure 120, or on the side of the source region 130 facing away from the gate structure 120, and on the side of the drain region 140 facing away from the gate structure 120 One side; the heat dissipation structure 180 includes one or more layers of connected heat conduction layers 80; by setting the heat dissipation structure 80, when the device is working, the heat generated by the device can be conducted out through the heat dissipation structure 180, thereby facilitating The heat dissipation efficiency of the device is improved, and the self-heating effect (Self-Heating Effect, SHE) of the device is correspondingly improved, thereby helping to improve the performance of the semiconductor structure.

The substrate is used to provide a platform for process steps. In this embodiment, the base is a three-dimensional base. Specifically, in this embodiment, the substrate is used to form a Fin Field Effect Transistor (FinFET), and the substrate includes a substrate 100 and fins 110 separated on the device region I substrate 100 . In other embodiments, the substrate can also be a planar substrate.

In particular, in this embodiment, the base includes a substrate 100 (as shown in FIG. 6 ) and a fin 110 (as shown in FIG. 6 ) located on the substrate 100 . The width of the fin 110 is generally small, and by forming a heat dissipation The structure 180 is beneficial to improve the heat dissipation capability of the FinFET device, thereby significantly improving the self-heating effect of the device.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Bottom and other types of substrates.

The fins 110 are used to provide a conductive channel during device operation.

In this embodiment, the material of the fin portion 110 is the same as that of the substrate 100 , and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, etc., which are suitable for forming the semiconductor material of the fin, and the material of the fin can also be the same as the material of the substrate. different.

In this embodiment, the semiconductor structure further includes: an isolation structure 111 (as shown in FIG. 6 ), located on the substrate 100 and covering part of the sidewall of the fin 110 . The isolation structure 111 is used to isolate adjacent fins 110 , and the isolation structure 111 is also used to isolate the substrate 100 and the gate structure 120 .

The material of the isolation structure 111 is an insulating material, and the thermal conductivity of the insulating material is lower than that of silicon, that is, the thermal conductivity of the isolation structure 111 is lower than that of the substrate 100 and the fins 110, and the fins 110 has a small width and a small volume, and the isolation structure 111 has a large volume, so it is difficult for the heat generated by the device to dissipate through the isolation structure 111 . Therefore, by arranging the heat dissipation structure 180 in the semiconductor structure, the heat generated by the device can be conducted away, which is beneficial to significantly improve the heat dissipation capability of the FinFET device, and further improve the heat dissipation effect of the device.

In this embodiment, the material of the isolation structure 111 is insulating material such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

When the device is working, the gate structure 120 is used to control the opening or closing of the conduction channel.

The gate structure 120 is located on the isolation structure 111 , the gate structure 120 spans the plurality of fins 110 , and covers part of the top and part of the sidewall of the fins 110 .

In this embodiment, the gate structure 120 is a metal gate structure. The gate structure 120 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer. ).

The high-k gate dielectric layer is used to electrically isolate the fin portion 110 from the gate structure 120 . The high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide, such as HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ .

When forming an NMOS transistor, the material of the work function layer is an N-type work function material, including one or more of TiAl, TaAlN, TiAlN, MoN, TaCN and AlN; when forming a PMOS transistor, the material of the work function layer is corresponding It is a P-type work function material, including one or more of Ta, TiN, TaN, TaSiN and TiSiN.

The gate electrode layer is used as an electrode, so that the gate structure 120 is electrically connected with other interconnection structures or external circuits. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti and the like.

The source region 130 and the drain region 140 are used to provide stress to the channel, thereby increasing the mobility of carriers.

In this embodiment, the source region 130 is located in the fin portion 110 on one side of the gate structure 120 , and the drain region 140 is located in the fin portion 110 on the other side of the gate structure 120 .

When an NMOS transistor is formed, the source region 130 or the drain region 140 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC, and the stress layer provides a pull for the channel region of the NMOS transistor. Stress, which is conducive to improving the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions; when forming a PMOS transistor, the source region 130 or the drain region 140 includes doped A stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides a compressive stress effect for the channel region of the PMOS transistor, thereby helping to improve the carrier mobility of the PMOS transistor, wherein , the P-type ions are B ions, Ga ions or In ions.

The bottom dielectric layer 150 is used to isolate adjacent devices, and the bottom dielectric layer 150 is also used to realize electrical isolation between the gate structure 120 and subsequent source and drain contact layers.

The bottom dielectric layer 150 is an interlayer dielectric layer (ILD). The material of the bottom dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the bottom dielectric layer 150 is a single-layer structure, and the material of the bottom dielectric layer 150 is silicon oxide.

In this embodiment, the semiconductor structure further includes: a source region contact layer 135 (as shown in FIG. 6 ), which penetrates through the bottom dielectric layer 150 above the source region 130 and is in contact with the source region 130; a drain region contact layer 145 (as shown in FIG. 6 shown), through the bottom dielectric layer 150 above the drain region 140 and in contact with the drain region 140

The source region contact layer 135 is used to realize electrical connection between the source region 130 and external circuits or other interconnection structures. The drain region contact layer 145 is used to realize the electrical connection between the drain region 140 and external circuits or other interconnection structures. The material of the source contact layer 135 and the drain contact layer 145 is a conductive material. Materials of the source contact layer 135 and the drain contact layer 145 include one or more of cobalt, tungsten, copper, nickel and aluminum.

In this embodiment, the source region contact layer 135 and the drain region contact layer 145 are made of the same material.

In this embodiment, the semiconductor structure further includes: a third dielectric layer 155 located between the top dielectric layer 185 and the bottom dielectric layer 150 . Correspondingly, the source contact layer 135 penetrates the bottom dielectric layer 150 and the third dielectric layer 155 above the source region 130 , and the drain contact layer 145 penetrates the bottom dielectric layer 150 and the third dielectric layer 155 above the drain region 140 .

The third dielectric layer 155 is used to realize electrical isolation between the source contact layer 135 and the drain contact layer 145 .

In this embodiment, the third dielectric layer 155 is an inter metal dielectric (IMD) layer. In this embodiment, the material of the third dielectric layer 155 is silicon oxide.

In this embodiment, the semiconductor structure further includes: a gate contact layer 125 (as shown in FIG. 5 ), which penetrates through the third dielectric layer 155 above the gate structure 120 and is in contact with the top of the gate structure 120 .

The gate contact layer 125 is used to realize the electrical connection between the gate structure 120 and external circuits or other interconnection structures. The material of the gate contact layer 125 is the same as that of the source region contact layer 135 and the drain region contact layer 145 , which will not be repeated here.

In this embodiment, the semiconductor structure further includes: a second dielectric layer 160 located between the top dielectric layer 185 and the bottom dielectric layer 150; a source interconnection structure 136 located in the second dielectric layer of the device region 1 The drain interconnection structure 146 is located in the second dielectric layer 160 of the device region II and contacts the top surface of the drain contact layer 145 .

The second dielectric layer 160 is used to realize the electrical connection between the source interconnection structure 136 and the drain interconnection structure 146 . Specifically, the second dielectric layer 160 is located between the third dielectric layer 155 and the top dielectric layer 185 .

In this embodiment, the second dielectric layer 160 is an inter-metal dielectric (IMD). Regarding the related description of the second dielectric layer 160 , reference may be made to the aforementioned related description of the third dielectric layer 155 , which will not be repeated here.

The source interconnection structure 136 is electrically connected to the source region 130 through the source region contact layer 135 , so as to realize electrical connection between the source region 130 and external circuits or other interconnection structures.

The drain interconnection structure 146 is electrically connected to the drain region 140 through the drain contact layer 145 , so as to realize an electrical connection between the drain region 140 and external circuits or other interconnection structures.

In this embodiment, both the source interconnection structure 136 and the drain interconnection structure 146 include the conductive plug 161 and the interconnection line 162 on the conductive plug 161 .

In this embodiment, the semiconductor structure further includes: a gate interconnection structure 126 (as shown in FIG. 5 ), penetrating through the second dielectric layer 160 above the gate contact layer 125 .

The gate interconnection structure 126 is electrically connected to the gate structure 120 through the gate contact layer 125 , so as to realize the electrical connection between the gate structure 125 and external circuits or other interconnection structures.

The material and structure of the gate interconnection structure 126 are the same as those of the source interconnection structure 136 or the drain interconnection structure 146 , and details will not be repeated here.

When the device is working, the heat generated by the device can be conducted out through the heat dissipation structure 180 , thereby improving the heat dissipation efficiency of the device, correspondingly improving the Self-Heating Effect (SHE) of the device, and further improving the performance of the semiconductor structure. In particular, in this embodiment, the base includes a substrate 100 and a fin 110 located on the substrate 100. The width of the fin 110 is small. By setting the heat dissipation structure 180, it is beneficial to significantly improve the heat dissipation capability of the FinFET device and improve the performance of the device. self-heating effect.

For this reason, the thermal conductivity of the material of the heat conduction layer 80 should not be too low, which is beneficial to improve the heat dissipation capability of the heat dissipation structure 180 , and further helps to improve the effect of the heat dissipation structure 180 for improving the self-heating effect of the device. Therefore, in this embodiment, the thermal conductivity of the material of the heat conducting layer 80 is at least 150 W/mK. As an example, the thermal conductivity of the material of the thermal conduction layer 80 is 150 W/mK to 1500 W/mK.

In this embodiment, the material of the heat conducting layer 80 is a metal material. The metal material has a high thermal conductivity, which is beneficial to ensure that the heat dissipation structure 180 has a high thermal conductivity, thereby improving the effect of the heat dissipation structure 180 on improving the self-heating effect of the device; moreover, the metal material is a conductive material that can The metal material is selected so that the heat dissipation structure 180 can be formed during the process of forming the back-end interconnection structure. The material of the heat dissipation structure 180 is the same as that of the back-end interconnection structure, which is beneficial to combine the formation process of the heat dissipation structure 180 with that of the back-end interconnection structure. The back-end interconnection process is compatible, which is conducive to improving process compatibility and process integration. Specifically, the metal material includes one or more of cobalt, tungsten, copper, nickel and aluminum.

When the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120 , the distance between the heat dissipation structure 180 and the source region 130 cannot be too small due to design rules. However, the distance between the heat dissipation structure 180 and the source region 130 should not be too large, otherwise it is easy to reduce the efficiency of the heat dissipated by the device from being transferred to the heat dissipation structure 180, and then it is easy to reduce the improvement effect of the heat dissipation structure 180 on the self-heating effect of the device. Moreover, It is also easy to cause the semiconductor structure to occupy an excessively large area, which is not conducive to the miniaturization of the device. Therefore, in this embodiment, when the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120 , the distance between the heat dissipation structure 180 and the source region 130 is 2 nm to 8 nm.

Similarly, when the heat dissipation structure 180 is located on the side of the drain region 140 facing away from the gate structure 120 , the distance between the heat dissipation structure 180 and the drain region 140 is 2 nm to 8 nm.

As an example, the top dielectric layer 185 includes a multi-layer stacked first dielectric layer 85; the heat dissipation structure 180 includes a multi-layer heat conduction layer 80, and the heat conduction layer 80 is located in the first dielectric layer 85; Layer 80 is a bottom thermally conductive layer 80a, and each thermally conductive layer 80 above bottom thermally conductive layer 80a is a top thermally conductive layer 80b.

By arranging the multi-layer heat conduction layer 80 , it is beneficial to further improve the heat dissipation efficiency of the heat dissipation structure 180 .

In this embodiment, two layers of the first dielectric layer 85 and the heat conduction layer 80 are taken as an example. In other embodiments, the number of layers of the first dielectric layer and the heat conduction layer may also be other numbers.

Correspondingly, in this embodiment, the heat dissipation structure 180 further includes: a first plug structure 81, located in the first dielectric layer 85 below each top heat conduction layer 80b and connected to the top heat conduction layer 81b; the first plug structure 81 It is in contact with the top of a thermally conductive layer 80 located below it.

The first plug structure 81 is used to connect the lower heat conduction layer 80 with the upper heat conduction layer 80 , so as to improve the heat dissipation efficiency of the heat dissipation structure 180 .

The material of the first plug structure 81 is also a metal material, which not only helps to improve the thermal conductivity of the first plug structure 81 , but also helps to make the process of forming the first plug structure 81 compatible with the subsequent interconnection process. The material of the first plug structure 81 includes one or more of cobalt, tungsten, nickel, copper and aluminum. In this embodiment, the material of the first plug structure 81 is the same as that of the heat conduction layer 80,

Correspondingly, the first dielectric layer 85 is used to realize electrical isolation between the thermal conduction layer 80 and the back-end interconnection structure. In this embodiment, the first dielectric layer 85 is an inter-metal dielectric layer. Therefore, the material of the first dielectric layer 85 is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the first dielectric layer 85 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between the subsequent interconnection structures, thereby reducing the subsequent RC delay. Specifically, the ultra-low-k dielectric material may be SiOCH.

In other embodiments, the top dielectric layer includes a first dielectric layer; the heat dissipation structure includes a thermal conduction layer, and the thermal conduction layer is located in the first dielectric layer.

In this embodiment, the heat dissipation structure 180 includes a plurality of heat conduction layers 80 stacked in sequence, and the heat conduction layer 80 closest to the base serves as the bottom heat conduction layer 80a. In other embodiments, when the heat dissipation structure includes a one-layer heat conduction layer, the heat conduction layer serves as the bottom heat conduction layer.

As an example, the heat dissipation structure 180 is only located on the side of the source region 130 facing away from the gate structure 120 . In other embodiments, the heat dissipation structure may only be located on the side of the drain region facing away from the gate structure. In some other embodiments, the heat dissipation structure may also be located on a side of the drain region facing away from the gate structure and a side of the source region facing away from the gate structure.

In this embodiment, the semiconductor structure further includes: a source connection layer 170 located in the second dielectric layer 160 on the side of the source interconnection structure 136 facing away from the gate structure 120 , the sidewall of the source connection layer 170 is connected to the source The interconnection structure 135 is in contact with each other, and the source connection layer 170 also extends into the second dielectric layer 160 below the bottom heat conduction layer 80a; the heat dissipation structure 180 further includes: a second plug structure 82 located between the source connection layer 170 and the bottom heat conduction layer The bottom of the second plug structure 82 is in contact with the top surface of the source connection layer 170 in the first dielectric layer 85 between the layers 80 a and is connected to the bottom thermal conduction layer 80 a.

By setting the source connection layer 170, the heat dissipation structure 180 is connected to the source interconnection structure 170 through the source connection layer 170; compared with conducting the heat dissipated from the device to the heat dissipation structure through the dielectric material, in this embodiment By forming the source connection layer 170, the material of the source connection layer 170 is the same as that of the source interconnection structure 136, and the thermal conductivity of the material of the source connection layer 170 is greater than that of the dielectric material, which is beneficial to make the device work The heat dissipated during the time is conducted to the heat dissipation structure 180 faster, and then can dissipate heat through the heat dissipation structure 180, which is beneficial to further improve the heat dissipation capability of the device.

Moreover, when the device is in operation, the source region 130 is usually connected to zero potential, and by connecting the heat dissipation structure 180 with the source interconnection structure 136 through the source connection layer 170, it is beneficial to reduce the influence of the heat dissipation structure 180 on the electrical connection performance of the device. .

The material of the source connection layer 170 is the same as that of the source interconnection structure 136 and the drain interconnection structure 146 , and will not be repeated here.

By setting the second plug structure 82 in the heat dissipation structure 180, the bottom heat conduction layer 80a is connected to the source connection layer 170 through the second plug structure 82, and the heat dissipation structure 180 is connected to the source region contact layer 135 accordingly. The heat generated when the device is in operation can be conducted to the heat dissipation structure 180 through the source connection layer 170, which is conducive to improving the heat dissipation efficiency and heat dissipation capacity of the heat dissipation structure 180, and further helps to improve the effect of the heat dissipation structure 180 for improving the self-heating effect of the device.

The material of the second plug structure 82 is a metal material, which not only helps to improve the thermal conductivity of the second plug structure 82, but also helps to make the process of forming the second plug structure 82 compatible with the subsequent interconnection process, Thus, it is beneficial to improve the degree of process integration.

In this embodiment, the material of the second plug structure 82 is the same as that of the source interconnection structure 136 or the drain interconnection structure 146, including one or the other of cobalt, tungsten, copper, nickel and aluminum. Various.

It should be noted that, in this embodiment, the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 110, and the source connection layer 170 for connecting the source region contact layer 135 and the heat dissipation structure 180 is provided as an example. . In other embodiments, when the heat dissipation structure is located on the side of the source region facing away from the gate structure, the heat dissipation structure and the contact layer of the source region may not be provided with a source connection layer. Correspondingly, when the device is in operation, the heat generated by the device It can conduct to the heat dissipation structure through the top dielectric layer, and then dissipate heat through the heat dissipation structure.

In some other embodiments, when the heat dissipation structure is located on the side of the drain region facing away from the gate, when the heat dissipation structure is located on the side of the drain region facing away from the gate, the semiconductor structure further includes: a drain connection layer located on the drain In the second dielectric layer on the side of the electrode interconnection structure facing away from the gate structure, the sidewall of the drain connection layer is in contact with the drain interconnection structure, and the drain connection layer also extends to the second dielectric layer below the bottom heat conducting layer The heat dissipation structure further includes: a third plug structure, located in the first dielectric layer between the drain connection layer and the bottom heat conduction layer and connected to the bottom heat conduction layer, the bottom of the third plug structure is connected to the bottom of the drain connection layer The top surfaces are in contact.

The drain connection layer is used to connect the drain interconnection structure and the heat dissipation structure, so that the heat of the device during operation can be conducted to the heat dissipation structure through the drain connection layer, which is beneficial to further improve the heat dissipation capability of the device.

Similarly, the heat dissipation structure is connected to the drain connection layer through the third plug structure, which is beneficial to improve the heat dissipation effect of the heat dissipation structure. For the detailed description of the material of the third plug structure, reference may be made to the related description of the second plug structure, which will not be repeated here.

In some other embodiments, when the heat dissipation structure is located on the side of the drain region facing away from the gate structure, no drain connection layer may be provided between the heat dissipation structure and the drain region connection layer. When the device is working, the heat generated by the device can be conducted to the heat dissipation structure through the top dielectric layer, and then dissipated through the heat dissipation structure.

Correspondingly, the present invention also provides a method for forming a semiconductor structure. 1 to 10 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to FIGS. 1 and 2, FIG. 1 is a top view, and FIG. 2 is a cross-sectional view at the AA1 position of FIG. 1, providing a substrate, including a plurality of discrete device regions I and isolation regions II between the device regions I, the A gate structure 120 is formed on the base of the device region 1, an active region 130 is formed in the base of the device region on one side of the gate structure 120, and an active region 130 is formed in the base of the device region on the other side of the gate structure 120. In the drain region 140 , a bottom dielectric layer 150 covering the source region 130 and the drain region 140 is formed on the substrate at the side of the gate structure 120 .

The substrate is used to provide a platform for process steps. In this embodiment, in the step of providing the base, the base is a three-dimensional base. Specifically, in this embodiment, the base is used to form a Fin Field Effect Transistor (FinFET), and the base includes a substrate 100 and fins 110 separated on the device region I substrate 100 . In other embodiments, the substrate can also be a planar substrate.

In this embodiment, the substrate 100 is a silicon substrate.

The fins 110 are used to provide a conductive channel when the device is in operation. In this embodiment, the material of the fin portion 110 is the same as that of the substrate 100 , and the material of the fin portion 110 is silicon.

In this embodiment, an isolation structure 111 covering part of the sidewall of the fin 110 is further formed on the substrate 100 .

The isolation structure 111 is used to isolate adjacent fins 110 , and the isolation structure 111 is also used to isolate the substrate 100 and the gate structure 120 . In this embodiment, the material of the isolation structure 111 is silicon oxide.

When the device is working, the gate structure 120 is used to control the opening or closing of the conduction channel.

The gate structure 120 is located on the isolation structure 111 , the gate structure 120 spans the plurality of fins 110 , and covers part of the top and part of the sidewall of the fins 110 .

In this embodiment, the gate structure 120 is a metal gate structure, including a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a work function layer located on the high-k gate dielectric layer. The upper gate electrode layer (not shown).

The source region 130 and the drain region 140 are used to provide stress to the channel, thereby increasing the mobility of carriers.

In this embodiment, the source region 130 is located in the fin portion 110 on one side of the gate structure 120 , and the drain region 140 is located in the fin portion 110 on the other side of the gate structure 120 .

When forming an NMOS transistor, the source region 130 or the drain region 140 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source region 130 or the drain region The region 140 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

The bottom dielectric layer 150 is used to isolate adjacent devices, and the bottom dielectric layer 150 is also used to realize electrical isolation between the gate structure 120 and subsequent source and drain contact layers.

The bottom dielectric layer 150 is an interlayer dielectric layer. The material of the bottom dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

Referring to FIG. 3 and FIG. 4 in conjunction, FIG. 3 is a top view, and FIG. 4 is a cross-sectional view at position AA of FIG. : forming a source contact layer 135 penetrating through the bottom dielectric layer 150 above the source region 130 and in contact with the source region 130 , and forming a bottom dielectric layer 150 penetrating above the drain region 140 and in contact with the drain region 140 Drain contact layer 145 .

The source region contact layer 135 is used to realize electrical connection between the source region 130 and external circuits or other interconnection structures. The drain region contact layer 145 is used to realize the electrical connection between the drain region 140 and external circuits or other interconnection structures. The material of the source contact layer 135 and the drain contact layer 145 is a conductive material, including one or more of cobalt, tungsten, copper, nickel and aluminum.

In this embodiment, the source region contact layer 135 and the drain region contact layer 145 are made of the same material.

In this embodiment, before forming the source contact layer 135 and the drain contact layer 145 , a third dielectric layer 155 is formed on the bottom dielectric layer 150 to cover the gate structure 120 .

The third dielectric layer 155 is used to realize electrical isolation between the source contact layer 135 and the drain contact layer 145 .

In this embodiment, the third dielectric layer 155 is an inter-metal dielectric layer. In this embodiment, the material of the third dielectric layer 155 is silicon oxide.

In this embodiment, it is taken as an example that the third dielectric layer 155 has a single-layer structure. In other embodiments, the third dielectric layer may also be a multi-layer structure.

Correspondingly, the step of forming the source region contact layer 135 and the drain region contact layer 145 includes: forming a source contact hole (not shown) penetrating through the bottom dielectric layer 150 and the third dielectric layer 155 above the source region 130 , forming a drain contact hole (not shown) that runs through the bottom dielectric layer 150 and the third dielectric layer 155 above the drain region 140; forming a source contact layer 135 filling the source contact hole, and filling the The drain contact layer 145 of the drain contact hole.

It should be noted that, in this embodiment, in the step of forming the source region contact layer 135 and the drain region contact layer 145, a third dielectric layer 155 penetrating above the gate structure 120 and connecting with the gate structure 120 is also formed. The top of structure 120 is in contact with gate contact layer 125 .

The gate contact layer 125 is used to realize the electrical connection between the gate structure 120 and external circuits or other interconnection structures. The material of the gate contact layer 125 is the same as that of the source region contact layer 135 and the drain region contact layer 145 , which will not be repeated here.

In this embodiment, the source contact layer 135 , the drain contact layer 145 , and the gate contact layer 125 are formed in the same step as an example. In other embodiments, the source contact layer and the drain contact layer, and the gate contact layer can also be formed in different steps.

Referring to FIG. 5 and FIG. 6 together, FIG. 5 is a top view, and FIG. 6 is a cross-sectional view of FIG. The second dielectric layer 160 of the layer 145; the source interconnection structure 136 in contact with the top surface of the source region contact layer 135 and the top surface of the drain region contact layer 145 are formed in the second dielectric layer 160 of the device region 1 The drain interconnect structure 146 is in face-to-face contact.

The second dielectric layer 160 is used to realize the electrical connection between the source interconnection structure 136 and the drain interconnection structure 146 . In this embodiment, the second dielectric layer 160 is an inter-metal dielectric layer. For the relevant description of the material of the second dielectric layer 160 , reference may be made to the above-mentioned relevant description of the third dielectric layer 155 , which will not be repeated here.

The source interconnection structure 136 is electrically connected to the source region 130 through the source region contact layer 135 , so as to realize electrical connection between the source region 130 and external circuits or other interconnection structures.

The drain interconnection structure 146 is electrically connected to the drain region 140 through the drain contact layer 145 , so as to realize an electrical connection between the drain region 140 and external circuits or other interconnection structures.

In this embodiment, after the second dielectric layer 160 is formed, the source interconnection structure 136 and the drain interconnection structure 146 are formed in the second dielectric layer 160 .

In this embodiment, the step of forming the source interconnection structure 136 and the drain interconnection structure 146 includes: forming a first conductive groove penetrating through the second dielectric layer 160 above the source region contact layer 135 (Fig. not shown), and a second conductive groove (not shown) penetrating through the second dielectric layer 160 above the drain region contact layer 145, the first conductive groove and the second conductive groove both include the second conductive groove located in a partial thickness. The interconnection groove (not shown) in the dielectric layer 160, and the conductive via hole (not shown) that runs through the second dielectric layer 160 below the interconnection groove; in the first conductive groove and the second conductive The grooves are filled with conductive material to form the source interconnection structure 136 in the first conductive groove and the drain interconnection structure 146 in the second conductive groove. The source interconnection structure 136 Both drain and drain interconnection structures 146 include a conductive plug 161 in the conductive via and an interconnection line 162 on the conductive plug 161 .

The material of the conductive plug 161 and the interconnection line 162 is a metal material, including one or more of cobalt, tungsten, copper, nickel and aluminum.

It should be noted that, in this embodiment, in the step of forming the first conductive groove and the second conductive groove, a third conductive groove ( not shown in the figure), the third conductive slot also includes interconnection trenches and conductive vias.

Correspondingly, in the step of filling the first conductive groove and the second conductive groove with the conductive material, the third conductive groove is also filled with the conductive material to form the gate interconnection structure 126 located in the third conductive groove. The pole interconnection structure 126 also includes a conductive plug 161 and an interconnection line 162 on the conductive plug 161 .

The gate interconnection structure 126 is electrically connected to the gate structure 120 through the gate contact layer 125 , so as to realize the electrical connection between the gate structure 125 and external circuits or other interconnection structures.

As an example, the subsequently formed heat dissipation structure is located in the top dielectric layer of the isolation region II, and the heat dissipation structure is located on the side of the source region 130 facing away from the gate structure 120 .

It should also be noted that, referring to FIG. 5 , in this embodiment, in the step of forming the source interconnection structure 136 , the method for forming the semiconductor structure further includes: A source connection layer 170 is formed in the second dielectric layer 160 on one side of the electrode structure 120. The source connection layer 170 is located on the sidewall of the device region I and contacts the source interconnection structure 136. The source connection The layer 170 also extends to the isolation region II on the side of the source region 130 facing away from the gate structure 120 .

By forming the source connection layer 170, the subsequently formed heat dissipation structure is connected to the source interconnection structure 170 through the source connection layer 170; compared with conducting the heat dissipated from the semiconductor structure to the heat dissipation structure through the dielectric material , in this embodiment, by forming the source connection layer 170, the material of the source connection layer 170 is the same as that of the source interconnection structure 136, the source connection layer 170 is a metal material, and the thermal conductivity of the metal material is greater than that of the medium The thermal conductivity of the material, therefore, is conducive to enabling the heat dissipated by the device to be conducted to the heat dissipation structure faster, and then dissipated through the heat dissipation structure, which is conducive to further improving the heat dissipation capability of the device.

Moreover, when the device is in operation, the source region 145 is usually connected to zero potential, and by connecting the subsequent heat dissipation structure with the source interconnection structure 136 through the source connection layer 170, it is beneficial to reduce the influence of the heat dissipation structure on the electrical connection performance of the device. .

In this embodiment, during the process of forming the source interconnection structure 136 and the drain interconnection structure 146 , the source connection layer 170 is formed. Specifically, in the process of forming the interconnect trench, the second dielectric layer 160 on the side of the source interconnect structure 136 facing away from the gate structure 120 is also etched to form a connection trench (not shown in the figure). ); during the process of filling the first conductive groove and the second conductive groove with a conductive material, the connection trench is also filled with a conductive material, and the source connection layer 170 is formed in the connection trench.

By forming the source connection layer 170 during the process of forming the source interconnection structure 136 and the drain interconnection structure 146 , it is beneficial to improve process compatibility and process integration.

It should be noted that, in this embodiment, the formation of the source connection layer 170 is taken as an example. In other embodiments, no source connection layer can be formed. Correspondingly, the heat generated when the device is in operation is conducted to the heat dissipation structure through the top dielectric layer.

In some other embodiments, when the subsequently formed heat dissipation structure is located on the side of the drain region facing away from the gate, in the step of forming the drain interconnection structure, the method for forming the semiconductor structure further includes: A drain connection layer is formed in the second dielectric layer on the side of the drain interconnection structure facing away from the gate structure, the drain connection layer is located on the sidewall of the device region and contacts the drain interconnection structure, the The drain connection layer also extends to the isolation region on the side of the drain region facing away from the gate.

The drain connection layer is used to connect the drain interconnection structure and the heat dissipation structure, so that the heat of the device during operation can be conducted to the heat dissipation structure through the drain connection layer, which is beneficial to further improve the heat dissipation capability of the device.

7 to 10, a top dielectric layer 185 covering the gate structure 120 and a heat dissipation structure 180 located in the top dielectric layer 185 of the isolation region II are formed on the bottom dielectric layer 150; The structure 180 is located on the side of the source region 130 facing away from the gate structure 120, or on the side of the drain region 140 facing away from the gate structure 120, or on the side of the source region 130 facing away from the gate structure 120 One side of the drain region 140 and one side of the drain region 140 facing away from the gate structure 120 ;

In the method for forming the semiconductor structure provided by the embodiment of the present invention, the heat dissipation structure 180 located in the top dielectric layer 185 of the isolation region II is also formed; the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120, or, The drain region 140 is located on the side facing away from the gate structure 120, or is located on the side of the source region 130 facing away from the gate structure 120, and the side of the drain region 140 facing away from the gate structure 120; the heat dissipation structure 180 includes a layer or Multi-layer connected heat conduction layer 80; by forming a heat dissipation structure 180, when the device is working, the heat generated by the device can be conducted out through the heat dissipation structure 180, thereby helping to improve the heat dissipation efficiency of the device and correspondingly improving the self-heating effect (Self-Heating) of the device Effect, SHE), which is conducive to improving the performance of semiconductor structures.

In particular, in this embodiment, the base includes a substrate 100 and a fin 110 located on the substrate 100. The width of the fin 110 is generally small. By forming the heat dissipation structure 180, it is beneficial to improve the heat dissipation capability of the FinFET device, thereby enabling Significantly improve the self-heating effect of the device.

For this reason, the thermal conductivity of the material of the heat conduction layer 80 should not be too low, which is beneficial to improve the heat dissipation capability of the heat dissipation structure 180 , and further helps to improve the effect of the heat dissipation structure 180 for improving the self-heating effect of the device. Therefore, in this embodiment, the thermal conductivity of the material of the heat conducting layer 80 is at least 150 W/mK. As an example, the thermal conductivity of the material of the heat conducting layer 80 is 150W/mK to 1500W/mK

In this embodiment, the material of the heat conducting layer 80 is a metal material. The metal material has a higher thermal conductivity, which is beneficial to ensure that the heat dissipation structure 180 has a higher heat conductivity, thereby improving the effect of the heat dissipation structure 180 on improving the self-heating effect of the device; moreover, the metal material is a conductive material, and by selecting a metal The material can form the heat dissipation structure 180 in the process of forming the back-end interconnection structure. The material of the heat dissipation structure 180 is the same as that of the back-end interconnection structure, so that the process of forming the heat dissipation structure 180 is integrated with the back-end interconnection process. It is beneficial to improve process compatibility and process integration.

Specifically, the metal material includes one or more of cobalt, tungsten, copper, nickel and aluminum.

In this embodiment, the heat dissipation structure 180 is only located on the side of the source region 130 facing away from the gate structure 120 as an example. In other embodiments, the heat dissipation structure may only be located on the side of the drain region facing away from the gate structure. In some other embodiments, the heat dissipation structure may also be located on a side of the drain region facing away from the gate structure and a side of the source region facing away from the gate structure.

When the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120 , limited by design rules, the distance between the heat dissipation structure 180 and the source region 130 cannot be too small. However, the distance between the heat dissipation structure 180 and the source region 130 should not be too large, otherwise it is easy to reduce the efficiency of the heat dissipated by the device from being transferred to the heat dissipation structure 180, and then it is easy to reduce the improvement effect of the heat dissipation structure 180 on the self-heating effect of the device. Moreover, It is also easy to cause the semiconductor structure to occupy an excessively large area. Therefore, in this embodiment, when the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120 , the distance between the heat dissipation structure 180 and the source region 130 is 2 nm to 8 nm.

Similarly, when the heat dissipation structure 180 is located on the side of the drain region 140 facing away from the gate structure 120 , the distance between the heat dissipation structure 180 and the drain region 140 is 2 nm to 8 nm.

As an example, the step of forming the top dielectric layer 185 includes sequentially forming a multilayer stack of first dielectric layers 85; the step of forming the heat dissipation structure 180 includes forming a heat conduction layer 80 in each first dielectric layer 85, and the heat dissipation structure includes multiple layers. The thermally conductive layers 80 of the layers; the one thermally conductive layer 80 closest to the substrate is the bottom thermally conductive layer 80a, and each thermally conductive layer 80 above the bottom thermally conductive layer 80a is the top thermally conductive layer 80b.

By forming the multi-layer heat conduction layer 80 , it is beneficial to improve the heat dissipation efficiency of the heat dissipation structure 180 .

Correspondingly, the first dielectric layer 85 is used to realize the electrical isolation between the thermal conduction layer and the back-end interconnection structure. In this embodiment, the first dielectric layer 85 is an inter-metal dielectric layer. The material of the first dielectric layer 85 is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride.

In this embodiment, the step of forming the heat dissipation structure 180 further includes: in the step of forming the top heat conduction layer 80 b , forming a first plug structure 81 in the first dielectric layer 85 and a top heat conduction layer on the first plug structure 81 . Layer 80b; wherein, the first plug structure 81 is in contact with the top of a thermally conductive layer 80 located below it.

The first plug structure 81 is used to connect the lower heat conduction layer 80 with the upper heat conduction layer 80 , so as to improve the heat dissipation efficiency of the heat dissipation structure 180 .

The material of the first plug structure 81 is also a metal material, which not only helps to improve the thermal conductivity of the first plug structure 81 , but also helps to make the process of forming the first plug structure 81 compatible with the subsequent interconnection process. In this embodiment, the material of the first plug structure 81 is the same as that of the heat conducting layer 80 .

In other embodiments, the step of forming the top dielectric layer includes forming a first dielectric layer; the step of forming the heat dissipation structure includes forming a heat conduction layer in the first dielectric layer, and the heat dissipation structure includes a heat conduction layer.

In this embodiment, the heat dissipation structure 180 includes multiple layers of heat conduction layers 80, and the heat conduction layer 80 closest to the base serves as the bottom heat conduction layer 80a. In other embodiments, the heat dissipation structure includes a thermally conductive layer, and the thermally conductive layer serves as the bottom thermally conductive layer.

In this embodiment, the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120. In this embodiment, the source interconnection structure 136 is further formed in the second dielectric layer 160 on the side of the Pole connection layer 170.

Therefore, the step of forming the heat dissipation structure 180 further includes: in the step of forming the bottom heat conduction layer 80a, forming a second plug structure 82 and the bottom heat conduction layer 80a on the second plug structure 82, the second plug structure 82 The source connection layer 170 is in contact with the top of the isolation region II.

By forming the second plug structure 82, the bottom thermal conduction layer 80a is connected to the source connection layer 170, and correspondingly, the heat dissipation structure 180 is connected to the source contact layer 135, and the heat generated during device operation can pass through the source connection layer. 170 conducts to the heat dissipation structure 180, which is beneficial to improve the heat dissipation efficiency and heat dissipation capacity of the heat dissipation structure 180, and further helps to improve the effect of the heat dissipation structure 190 for improving the self-heating effect of the device.

The material of the second plug structure 82 is a metal material, which not only helps to improve the thermal conductivity of the second plug structure 82, but also helps to make the process of forming the second plug structure 82 compatible with the subsequent interconnection process, so that It is beneficial to improve process integration and process compatibility. In this embodiment, the material of the second plug structure 82 is the same as that of the source interconnection structure 136 or the drain interconnection structure 146 , including one or more of cobalt, tungsten, copper, nickel and aluminum.

In this embodiment, two layers of the first dielectric layer 85 and the heat conduction layer 80 are taken as an example. In other embodiments, the number of layers of the first dielectric layer and the heat conduction layer may also be other numbers.

Correspondingly, in this embodiment, the step of forming the top dielectric layer 185 and the heat dissipation structure 180 includes: as shown in FIG. 7 and FIG. 8, FIG. 7 is a top view, and FIG. A first dielectric layer 85a is formed on the second dielectric layer 160; a second plug structure 82 and a bottom thermal conduction layer 80a located on the second plug structure 82 are formed in the first dielectric layer 85a; as shown in FIGS. 9 and 10 , FIG. 9 is a top view, and FIG. 10 is a schematic partial cross-sectional view at the position of BB1 in FIG. 9, a first dielectric layer 85b is formed on the first dielectric layer 85a; The top thermally conductive layer 80b on the first plug structure 81 .

It should be noted that, in this embodiment, the heat dissipation structure 180 is located on the side of the source region 130 facing away from the gate structure 120, and the source connection layer 170 for connecting the source region contact layer 135 and the heat dissipation structure 180 is formed as a kind of example. In other embodiments, when the heat dissipation structure is located on the side of the source region facing away from the gate structure, the heat dissipation structure and the contact layer of the source region may not have a source connection layer. Correspondingly, when the device is in operation, the Heat can be conducted to the heat dissipation structure through the top dielectric layer, and then dissipated through the heat dissipation structure.

In some other embodiments, when the heat dissipation structure is located on the side of the drain region facing away from the gate structure, the step of forming the heat dissipation structure further includes: in the step of forming the bottom heat conduction layer, forming a third plug structure and The bottom thermal conduction layer is on the plug structure, and the third plug structure is in contact with the drain connection layer at the top of the isolation region. Similarly, the heat dissipation structure is connected to the drain connection layer through the third plug structure, which is beneficial to improve the heat dissipation effect of the heat dissipation structure. For the detailed description of the material of the third plug structure, reference may be made to the related description of the second plug structure, which will not be repeated here.

Alternatively, when the heat dissipation structure is located on the side of the drain region facing away from the gate structure, no drain connection layer may be formed between the heat dissipation structure and the drain region connection layer. Correspondingly, when the device is working, the heat generated by the device can be conducted to the heat dissipation structure through the top dielectric layer, and then dissipated through the heat dissipation structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A semiconductor structure, characterized in that, comprising: a substrate including discrete device regions and isolation regions between the device regions; a gate structure located on the substrate of the device region; a source region located in the base of the device region on one side of the gate structure; a drain region located in the base of the device region on the other side of the gate structure; a bottom dielectric layer, located on the substrate at the side of the gate structure and covering the source region and the drain region; a top dielectric layer located on the bottom dielectric layer and covering the gate structure; The heat dissipation structure is located in the top dielectric layer of the isolation region; the heat dissipation structure is located on the side of the source region facing away from the gate structure, or on the side of the drain region facing away from the gate structure, or, It is located on the side of the source region facing away from the gate structure and the side of the drain region facing away from the gate structure; the heat dissipation structure includes one or more connected heat conducting layers. 2. The semiconductor structure according to claim 1, wherein the base comprises a substrate and a plurality of fins separated on the device region substrate; The gate structure spans a plurality of fins, and covers part of the top and part of the sidewall of the fin; the source region is located in the fin on one side of the gate structure, and the drain region is located in In the fin portion on the other side of the gate structure. 3. The semiconductor structure according to claim 1, wherein the top dielectric layer comprises a first dielectric layer; the heat dissipation structure comprises a thermal conduction layer, and the thermal conduction layer is located on the first dielectric layer layer; Alternatively, the top dielectric layer includes a multi-layer stacked first dielectric layer; the heat dissipation structure includes a multi-layer heat conduction layer, and the heat conduction layer is located in the first dielectric layer; wherein, a heat conduction layer closest to the base is a bottom heat conduction layer, and each heat conduction layer above the bottom heat conduction layer is a top heat conduction layer; The heat dissipation structure further includes: a first plug structure located in the first dielectric layer below each of the top heat conduction layers and connected to the top heat conduction layer; The tops of the thermally conductive layers are in contact. 4. The semiconductor structure according to claim 1, further comprising: a source contact layer, penetrating through the bottom dielectric layer above the source region and in contact with the source region; a drain region contact layer, penetrating through the bottom dielectric layer above the drain region and in contact with the drain region; a second dielectric layer located between the top dielectric layer and the bottom dielectric layer; a source interconnection structure located in the second dielectric layer of the device region and in contact with the top surface of the source region contact layer; The drain interconnection structure is located in the second dielectric layer of the device region and is in contact with the top surface of the drain region contact layer. 5. The semiconductor structure according to claim 1, wherein when the heat dissipation structure is located on the side of the source region facing away from the gate structure, the distance between the heat dissipation structure and the source region is 2nm to 8nm; When the heat dissipation structure is located on the side of the drain region facing away from the gate structure, the distance between the heat dissipation structure and the drain region is 2nm to 8nm. 6. The semiconductor structure according to claim 4, wherein the heat dissipation structure comprises a one-layer heat conduction layer, and the heat conduction layer is used as a bottom heat conduction layer; or, the heat dissipation structure comprises a multilayer heat conduction layer, and the most A heat conduction layer close to the base acts as the bottom heat conduction layer; When the heat dissipation structure is located on the side of the source region facing away from the gate structure, the semiconductor structure further includes: a source connection layer, a second dielectric layer located on the side of the source interconnection structure facing away from the gate structure wherein, the sidewall of the source connection layer is in contact with the source interconnection structure, and the source connection layer also extends into the second dielectric layer below the bottom heat conducting layer; The heat dissipation structure further includes: a second plug structure located in the first dielectric layer between the source connection layer and the bottom heat conduction layer and connected to the bottom heat conduction layer, the second plug structure The bottom is in contact with the top surface of the source connection layer. 7. The semiconductor structure according to claim 4, wherein the heat dissipation structure comprises a layer of heat conduction layer, and the heat conduction layer is used as a bottom heat conduction layer; or, the heat dissipation structure comprises a multi-layer heat conduction layer, and the most A heat conduction layer close to the base acts as the bottom heat conduction layer; When the heat dissipation structure is located on the side of the drain region facing away from the gate, the semiconductor structure further includes: a drain connection layer located in the second dielectric layer on the side of the drain interconnection structure facing away from the gate structure , the sidewall of the drain connection layer is in contact with the drain interconnection structure, and the drain connection layer also extends into the second dielectric layer below the bottom heat conducting layer; The heat dissipation structure further includes: a third plug structure, located in the first dielectric layer between the drain connection layer and the bottom heat conduction layer and connected to the bottom heat conduction layer, the third plug structure The bottom is in contact with the top surface of the drain connection layer. 8. The semiconductor structure of claim 1, wherein a material of the thermally conductive layer has a thermal conductivity of at least 150 W/mK. 9. The semiconductor structure according to claim 3, wherein the material of the first plug structure is a metal material. 10. The semiconductor structure according to claim 6, wherein the material of the second plug structure is a metal material. 11. The semiconductor structure according to claim 7, wherein the material of the third plug structure is a metal material. 12. The semiconductor structure according to claim 1, wherein the material of the heat conducting layer is a metal material. 13. The semiconductor structure according to any one of claims 9 to 12, wherein the metal material comprises one or more of cobalt, tungsten, copper, aluminum and nickel. 14. A method for forming a semiconductor structure, comprising: A substrate is provided, including a plurality of discrete device regions and isolation regions between the device regions, a gate structure is formed on the substrate of the device region, and an active region is formed in the substrate of the device region on one side of the gate structure A drain region is formed in the substrate of the device region on the other side of the gate structure, and a bottom dielectric layer covering the source region and the drain region is formed on the substrate at the side of the gate structure; A top dielectric layer covering the gate structure and a heat dissipation structure located in the top dielectric layer of the isolation region are formed on the bottom dielectric layer; the heat dissipation structure is located on a side of the source region facing away from the gate structure. side, or on the side of the drain region facing away from the gate structure, or on the side of the source region facing away from the gate structure, and on the side of the drain region facing away from the gate structure; The heat dissipation structure includes one or more connected heat conduction layers. 15. The method for forming a semiconductor structure according to claim 14, wherein in the step of providing a base, the base includes a substrate and fins separated on the device region substrate; The gate structure spans a plurality of fins, and covers part of the top and part of the sidewall of the fin; the source region is located in the fin on one side of the gate structure, and the drain region is located in In the fin portion on the other side of the gate structure. 16. The method for forming a semiconductor structure according to claim 14, wherein the step of forming the top dielectric layer includes forming a first dielectric layer; the step of forming the heat dissipation structure includes The heat conduction layer is formed in the dielectric layer, and the heat dissipation structure includes a layer of heat conduction layer; or, The step of forming the top dielectric layer includes sequentially forming a multilayer stack of first dielectric layers; the step of forming the heat dissipation structure includes forming the heat conduction layer in each of the first dielectric layers, and the heat dissipation structure includes multiple The heat conduction layer of the layer; the heat conduction layer closest to the base is the bottom heat conduction layer, and each heat conduction layer above the bottom heat conduction layer is the top heat conduction layer; The step of forming the heat dissipation structure further includes: in the step of forming the top heat conduction layer, forming a first plug structure in the first dielectric layer and the top heat conduction layer on the first plug structure layer; wherein the first plug structure is in contact with the top of an underlying thermally conductive layer. 17. The method for forming a semiconductor structure according to any one of claims 14 to 16, wherein after providing the substrate, before forming the top dielectric layer and the heat dissipation structure, the method for forming the semiconductor structure further comprises: forming a source contact layer penetrating through the bottom dielectric layer above the source region and in contact with the source region, and forming a drain contact layer penetrating through the bottom dielectric layer above the drain region and in contact with the drain region; forming a second dielectric layer covering the gate structure, the source contact layer and the drain contact layer on the bottom dielectric layer; A source interconnection structure in contact with the top surface of the source region contact layer and a drain interconnection structure in contact with the top surface of the drain region contact layer are formed in the second dielectric layer of the device region. 18. The method for forming a semiconductor structure according to claim 17, wherein in the step of forming the source interconnection structure, the method for forming the semiconductor structure further comprises: A source connection layer is formed in the second dielectric layer on one side of the gate structure, the source connection layer is located on the sidewall of the device region and contacts the source interconnection structure, and the source connection layer also extends to the source On the isolation region on the side facing away from the gate; The heat dissipation structure includes a layer of heat conduction layer, and the heat conduction layer is used as the bottom heat conduction layer; or, the heat dissipation structure includes multiple layers of heat conduction layers, and the heat conduction layer closest to the base is used as the bottom heat conduction layer; The step of forming the heat dissipation structure further includes: in the step of forming the bottom heat conduction layer, forming a second plug structure and the bottom heat conduction layer on the second plug structure, the second plug structure is in contact with the source connection layer on top of the isolation region. 19. The method for forming a semiconductor structure according to claim 17, wherein in the step of forming the drain interconnection structure, the method for forming the semiconductor structure further comprises: A drain connection layer is formed in the second dielectric layer on one side of the gate structure, the drain connection layer is located on the sidewall of the device region and contacts the drain interconnection structure, and the drain connection layer also extends to the drain On the isolation region on the side facing away from the gate; The heat dissipation structure includes a layer of heat conduction layer, and the heat conduction layer is used as the bottom heat conduction layer; or, the heat dissipation structure includes multiple layers of heat conduction layers, and the heat conduction layer closest to the base is used as the bottom heat conduction layer; The step of forming the heat dissipation structure further includes: in the step of forming the bottom heat conduction layer, forming a third plug structure and the bottom heat conduction layer on the third plug structure, the third plug The structure is in contact with the drain connection layer on top of the isolation region. 20. The method for forming a semiconductor structure according to claim 14, wherein the material of the heat conducting layer is a metal material.