CN113778734B - Chip, chip bus detection system, chip bus detection method and storage medium - Google Patents
Chip, chip bus detection system, chip bus detection method and storage medium Download PDFInfo
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- CN113778734B CN113778734B CN202111028333.1A CN202111028333A CN113778734B CN 113778734 B CN113778734 B CN 113778734B CN 202111028333 A CN202111028333 A CN 202111028333A CN 113778734 B CN113778734 B CN 113778734B
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
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Abstract
The invention provides a chip, a detection system, a detection method and a storage medium of a chip bus, wherein the system comprises: the system comprises a debugging interface, a debugging bus, at least one bus detection unit and a controller, wherein the first end of each bus detection unit is connected with each bus unit, the second end of each bus detection unit is connected with a bus node corresponding to each bus unit, the third end of each bus detection unit is connected with the first end of the debugging interface through the debugging bus, and the second end of the debugging interface is connected with the controller; the controller is used for accessing each bus detection unit through the debugging interface and the debugging bus under the condition that the chip bus is abnormal, so as to acquire the information of each bus detection unit, and positioning the address of the chip bus abnormal according to the information of each bus detection unit. Therefore, when the bus of the chip is abnormal, the system can accelerate the speed of locating the abnormal bus address of the chip, and improves the efficiency and the effectiveness of debugging the chip.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a chip, a chip bus detection system, a chip bus detection method, and a storage medium.
Background
A SoC (System-on-a-Chip) Chip is a System-on-Chip, also called Chip-on-Chip, which is an integrated circuit with a dedicated target, and the general composition of its hardware is: core, storage, peripheral interfaces (high-speed peripherals and low-speed peripherals), bus, interrupt unit, clock unit, etc. When an abnormality occurs in the bus of the SoC chip, a situation that the processor cannot access the bus generally occurs, and it is not known which bus units have the abnormality continuously.
Therefore, how to know which buses of the bus units are abnormal when the buses of the SoC chip are abnormal is a problem to be solved.
Disclosure of Invention
The object of the present invention is to solve at least to some extent one of the technical problems in the art described above.
Therefore, a first object of the present invention is to provide a system for detecting a chip bus, which can increase the speed of locating an abnormal chip bus address when an abnormality occurs in the chip bus, and improve the efficiency and effectiveness of debugging the chip.
A second object of the invention is to propose a chip.
A third object of the present invention is to provide a method for detecting a chip bus.
A fourth object of the present invention is to propose a non-transitory computer readable storage medium storing computer instructions.
To achieve the above object, an embodiment of a first aspect of the present invention provides a system for detecting a chip bus, including: the device comprises a debugging interface, a debugging bus, at least one bus detection unit and a controller, wherein the first end of each bus detection unit is connected with each bus unit, the second end of each bus detection unit is connected with a bus node corresponding to each bus unit, the third end of each bus detection unit is connected with the first end of the debugging interface through the debugging bus, and the second end of the debugging interface is connected with the controller; the controller is used for accessing each bus detection unit through the debugging interface and the debugging bus under the condition that the chip bus is abnormal, so as to acquire the information of each bus detection unit, and positioning the address of the chip bus abnormal according to the information of each bus detection unit.
According to the detection system of the chip bus, provided by the embodiment of the invention, the bus detection units are additionally arranged between each bus unit and the corresponding bus node, all the bus detection units are connected with the controller through the debugging bus and the debugging interface, so that the controller accesses each bus detection unit through the debugging interface and the debugging bus under the condition that the chip bus is abnormal, the information of each bus detection unit is obtained, and the address of the chip bus abnormal is positioned according to the information of each bus detection unit. Therefore, when the bus of the chip is abnormal, the system can accelerate the speed of locating the abnormal bus address of the chip, and improves the efficiency and the effectiveness of debugging the chip.
In addition, the detection system of the chip bus according to the embodiment of the present invention may further have the following additional technical features:
According to one embodiment of the invention, the controller is further configured to: and correspondingly processing the chip bus with the abnormal address so as to ensure that the chip runs safely and reliably.
According to one embodiment of the present invention, when the controller accesses each of the bus detection units, it includes: each of the bus detection units is accessed in an addressed manner.
According to one embodiment of the invention, the debug interface is a joint test workgroup JTAG interface.
In order to achieve the above object, a second aspect of the present invention provides a chip including the above-mentioned detection system for a chip bus.
According to the chip provided by the embodiment of the invention, through the detection system of the chip bus, when the bus of the chip is abnormal, the speed of locating the abnormal chip bus address can be increased, and the efficiency and the effectiveness of debugging the chip are improved.
To achieve the above object, an embodiment of the present invention provides a method for detecting a chip bus, where a detecting device for a chip bus includes a debug interface, a debug bus, at least one bus detecting unit, and a controller, a first end of each of the bus detecting units is connected to each of the bus units, a second end of each of the bus detecting units is connected to a bus node corresponding to each of the bus units, a third end of each of the bus detecting units is connected to the first end of the debug interface through the debug bus, and a second end of the debug interface is connected to the controller, where the detecting method includes the following steps: under the condition that the chip bus is abnormal, accessing each bus detection unit through the debugging interface and the debugging bus to acquire the information of each bus detection unit; and positioning the address of the chip bus abnormal according to the information of each bus detection unit.
According to the detection method of the chip bus, provided by the embodiment of the invention, one bus detection unit is additionally arranged between each bus unit and the corresponding bus node, all the bus detection units are connected with the controller through the debugging bus and the debugging interface, and the controller accesses each bus detection unit through the debugging interface and the debugging bus under the condition that the chip bus is abnormal, so as to acquire the information of each bus detection unit, and positions the address of the chip bus abnormal according to the information of each bus detection unit. Therefore, when the bus of the chip is abnormal, the method can accelerate the speed of locating the abnormal bus address of the chip, and improves the efficiency and the effectiveness of debugging the chip.
In addition, the method for detecting a chip bus according to the above embodiment of the present invention may further have the following additional technical features:
According to an embodiment of the invention, said accessing each of said bus detection units comprises: each of the bus detection units is accessed in an addressed manner.
According to an embodiment of the present invention, the method for detecting a chip bus further includes: and correspondingly processing the chip bus with the abnormal address so as to ensure that the chip runs safely and reliably.
According to one embodiment of the invention, the debug interface is a joint test workgroup JTAG interface.
To achieve the above object, a fourth aspect of the present invention provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the above-described method for detecting a chip bus.
According to the non-transitory computer readable storage medium storing the computer instructions, through executing the method for detecting the chip bus, when the chip bus is abnormal, the speed of locating the abnormal chip bus address can be increased, and the efficiency and the effectiveness of debugging the chip are improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block schematic diagram of a detection system for a chip bus according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a detection system of a chip bus according to an embodiment of the present invention;
Fig. 3 is a flowchart of a method for detecting a chip bus according to an embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
A chip bus detection system, a chip bus detection method, and a non-transitory computer-readable storage medium storing computer instructions according to embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a block schematic diagram of a detection system of a chip bus according to an embodiment of the present invention.
As shown in fig. 1, a detection system 100 for a chip bus according to an embodiment of the present invention includes: a debug interface 110, a debug bus 120, at least one bus detection unit 130, and a controller 140.
Wherein, a first end of each bus detection unit 130 is connected to each bus unit, a second end of each bus detection unit 130 is connected to a bus node corresponding to each bus unit, a third end of each bus detection unit 130 is connected to a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected to the controller 140. The controller 140 is configured to access each bus detection unit 130 through the debug interface 110 and the debug bus 120 in case of an abnormality of the chip bus, to obtain information of each bus detection unit 130, and to locate an address of the abnormality of the chip bus according to the information of each bus detection unit 130.
For example, referring to fig. 2, at least one bus detection unit 130 includes a bus detection unit 1-bus detection unit 10, the bus units include a bus unit M0-bus unit M4, a bus unit IP 1-bus unit IP5, and the bus nodes include a bus node M0-bus node M4, a bus node IP 1-bus node IP5. Wherein, the first end of the bus detection unit 1 is connected with the bus unit M0, the second end of the bus detection unit 1 is connected with the bus node M0, the third end of the bus detection unit 1 is connected with the first end of the debug interface 110 through the debug bus 120, and the second end of the debug interface 110 is connected with the controller 140; A first end of the bus detection unit 2 is connected with the bus unit M1, a second end of the bus detection unit 2 is connected with the bus node M1, a third end of the bus detection unit 2 is connected with a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected with the controller 140; a first end of the bus detection unit 3 is connected with the bus unit M2, a second end of the bus detection unit 3 is connected with the bus node M2, a third end of the bus detection unit 3 is connected with a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected with the controller 140; a first end of the bus detection unit 4 is connected with the bus unit M3, a second end of the bus detection unit 4 is connected with the bus node M3, a third end of the bus detection unit 4 is connected with a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected with the controller 140; A first end of the bus detection unit 5 is connected with the bus unit M4, a second end of the bus detection unit 5 is connected with the bus node M4, a third end of the bus detection unit 5 is connected with a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected with the controller 140; a first end of the bus detection unit 6 is connected with the bus unit IP1, a second end of the bus detection unit 6 is connected with the bus node IP1, a third end of the bus detection unit 6 is connected with a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected with the controller 140; a first end of the bus detection unit 7 is connected with the bus unit IP2, a second end of the bus detection unit 7 is connected with the bus node IP2, a third end of the bus detection unit 7 is connected with a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected with the controller 140; A first end of the bus detection unit 8 is connected with the bus unit IP3, a second end of the bus detection unit 8 is connected with the bus node IP3, a third end of the bus detection unit 8 is connected with a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected with the controller 140; a first end of the bus detection unit 9 is connected with the bus unit IP4, a second end of the bus detection unit 9 is connected with the bus node IP4, a third end of the bus detection unit 9 is connected with a first end of the debug interface 110 through the debug bus 120, and a second end of the debug interface 110 is connected with the controller 140; the first end of the bus detection unit 10 is connected to the bus unit IP5, the second end of the bus detection unit 10 is connected to the bus node IP5, the third end of the bus detection unit 10 is connected to the first end of the debug interface 110 through the debug bus 120, and the second end of the debug interface 110 is connected to the controller 140. That is, for each bus unit in the chip, a corresponding bus detection unit 130 is added.
In this embodiment, each bus detection unit 130 has a function of detecting a transfer behavior of a bus, a bus transfer capability, a transfer address (read and write), and the like. The bus detection unit 130 for different physical locations has a unique corresponding address and is accessed directly using a different address whenever there is any configuration or access required.
At any time, when detecting that a bus abnormality occurs in the chip, including but not limited to bus hang-up, memory trampling, etc., through the debug interface 110 (such as a joint test group JTAG interface or a custom hardware interface) and the debug bus 120 (such as a custom internal debug bus for accessing each bus detection unit 130), a specific site is grabbed, each bus detection unit 130 is accessed to derive information of each bus detection unit 130, and further analysis is performed according to the information of each bus detection unit 130, so as to gradually exclude whether the bus of the bus unit of each address is abnormal, and thus, the address where the abnormality occurs in the chip bus can be located.
Therefore, the invention uses the debugging interface and the debugging bus, and even if the bus is abnormal and can not be accessed, the bus detection unit captures all the bus sites of the corresponding bus units, thereby accelerating the speed of locating the abnormal address of the bus and improving the debugging efficiency and effectiveness.
In order to make the chip safely and reliably operate, the controller 140 is further configured to perform corresponding processing on the chip bus with the address abnormal, for example, a standby chip bus may be set for each bus unit, so that after the chip bus is abnormal and the address of the chip bus with the abnormal address is obtained, the chip bus with the abnormal address is switched to the standby chip bus with the corresponding address, so that the chip can be ensured to safely and reliably operate.
To further improve the efficiency and effectiveness of the debug, the controller 140 accesses each bus detection unit in an addressed manner based on the addresses of the different location bus detection units when accessing each bus detection unit.
In summary, according to the detection system for a chip bus in the embodiment of the present invention, a bus detection unit is added between each bus unit and a corresponding bus node, and all the bus detection units are connected to the controller through the debug bus and the debug interface, so that the controller accesses each bus detection unit through the debug interface and the debug bus when the chip bus is abnormal, so as to obtain information of each bus detection unit, and locates an address where the chip bus is abnormal according to the information of each bus detection unit. Therefore, when the bus of the chip is abnormal, the system can accelerate the speed of locating the abnormal bus address of the chip, and improves the efficiency and the effectiveness of debugging the chip.
Based on the above embodiments, the present invention proposes a chip including the above detection system for a chip bus.
According to the chip provided by the embodiment of the invention, through the detection system of the chip bus, when the bus of the chip is abnormal, the speed of locating the abnormal chip bus address can be increased, and the efficiency and the effectiveness of debugging the chip are improved.
Based on the above embodiment, the invention further provides a method for detecting the chip bus.
Fig. 3 is a flowchart of a method of detecting a chip bus according to an embodiment of the present invention.
It should be noted that, referring to fig. 1, the detection device of the chip bus includes a debug interface, a debug bus, at least one bus detection unit and a controller, a first end of each bus detection unit is connected to each bus unit, a second end of each bus detection unit is connected to a bus node corresponding to each bus unit, a third end of each bus detection unit is connected to the first end of the debug interface through the debug bus, and a second end of the debug interface is connected to the controller. The execution subject of the detection method of the chip bus of the embodiment of the invention is a controller.
As shown in fig. 3, the method for detecting a chip bus according to the embodiment of the invention includes the following steps:
S1, under the condition that the chip bus is abnormal, accessing each bus detection unit through the debugging interface and the debugging bus to acquire information of each bus detection unit.
S2, positioning the address of the chip bus abnormal according to the information of each bus detection unit.
According to an embodiment of the invention, said accessing each of said bus detection units comprises: each of the bus detection units is accessed in an addressed manner.
According to an embodiment of the present invention, the method for detecting a chip bus further includes: and correspondingly processing the chip bus with the abnormal address so as to ensure that the chip runs safely and reliably.
According to one embodiment of the invention, the debug interface is a joint test workgroup JTAG interface.
It should be noted that, for details not disclosed in the method for detecting a chip bus according to the embodiment of the present invention, please refer to details not disclosed in the system for detecting a chip bus according to the embodiment of the present invention, and detailed descriptions thereof will not be provided herein.
According to the detection method of the chip bus, provided by the embodiment of the invention, one bus detection unit is additionally arranged between each bus unit and the corresponding bus node, all the bus detection units are connected with the controller through the debugging bus and the debugging interface, and the controller accesses each bus detection unit through the debugging interface and the debugging bus under the condition that the chip bus is abnormal, so as to acquire the information of each bus detection unit, and positions the address of the chip bus abnormal according to the information of each bus detection unit. Therefore, when the bus of the chip is abnormal, the method can accelerate the speed of locating the abnormal bus address of the chip, and improves the efficiency and the effectiveness of debugging the chip.
Based on the above embodiments, the present invention proposes a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the above-described method of detecting a chip bus.
The non-transitory computer readable storage medium storing computer instructions according to the embodiment of the invention can accelerate the speed of locating the abnormal chip bus address when the chip bus is abnormal by executing the method for detecting the chip bus, thereby improving the efficiency and the effectiveness of debugging the chip
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As with the other embodiments, if implemented in hardware, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like. While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (8)
1. A system for detecting a chip bus, comprising:
The system comprises a debugging interface, a debugging bus, at least one bus detection unit and a controller, wherein each bus detection unit has the functions of detecting the transmission behavior, the bus transmission capacity and the transmission address of the bus, and has a unique corresponding address aiming at the bus detection units in different physical positions, when configuration or access is needed, the bus detection units are directly accessed by using different addresses, wherein,
The first end of each bus detection unit is connected with each bus unit, the second end of each bus detection unit is connected with a bus node corresponding to each bus unit, the third end of each bus detection unit is connected with the first end of the debug interface through the debug bus, and the second end of the debug interface is connected with the controller;
the controller is used for accessing each bus detection unit through the debugging interface and the debugging bus under the condition that the chip bus is abnormal, so as to acquire information of each bus detection unit, and locating an address of the chip bus abnormal according to the information of each bus detection unit, wherein the abnormality comprises bus suspension and memory trampling, and when the controller accesses each bus detection unit, each bus detection unit is accessed according to an addressing mode.
2. The system for detecting a chip bus according to claim 1, wherein the controller is further configured to:
And correspondingly processing the chip bus with the abnormal address so as to ensure that the chip runs safely and reliably.
3. The system of claim 1, wherein the debug interface is a joint test workgroup JTAG interface.
4. A chip, comprising: a detection system for a chip bus as claimed in any one of claims 1 to 3.
5. The detection method of the chip bus is characterized in that a detection device of the chip bus comprises a debugging interface, a debugging bus, at least one bus detection unit and a controller, wherein a first end of each bus detection unit is connected with each bus unit, a second end of each bus detection unit is connected with a bus node corresponding to each bus unit, a third end of each bus detection unit is connected with the first end of the debugging interface through the debugging bus, a second end of the debugging interface is connected with the controller, each bus detection unit has the functions of detecting the transmission behavior, the bus transmission capacity and the transmission address of the bus, and the bus detection units in different physical positions have unique corresponding addresses, and when configuration or access is needed, different addresses are directly used for access, and the detection method comprises the following steps:
Accessing each bus detection unit through the debug interface and the debug bus under the condition that the chip bus is abnormal, so as to acquire the information of each bus detection unit, wherein the abnormality comprises bus death and memory trampling, and when the controller accesses each bus detection unit, each bus detection unit is accessed according to an addressing mode;
and positioning the address of the chip bus abnormal according to the information of each bus detection unit.
6. The method for detecting a chip bus according to claim 5, further comprising:
And correspondingly processing the chip bus with the abnormal address so as to ensure that the chip runs safely and reliably.
7. The method of claim 5, wherein the debug interface is a joint test workgroup JTAG interface.
8. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of detecting a chip bus of any one of claims 5-7.
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| TWI854647B (en) * | 2023-05-10 | 2024-09-01 | 大陸商北京有竹居網路技術有限公司 | Bus anomaly detection and processing method, apparatus, system, device and media |
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| CN109918303B (en) * | 2019-03-05 | 2022-12-16 | 上海嘉楠捷思信息技术有限公司 | Chip, chip debugging method and device, equipment and medium |
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