CN113764339B - Semiconductor structure and method of forming the same - Google Patents

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a semiconductor substrate including a first region and a fourth region; a gate structure on the semiconductor substrate in the first region and the fourth region; the barrier layer is positioned on the grid structure of the first area and comprises a plurality of grooves penetrating through the barrier layer; and the dielectric layer is positioned on the semiconductor substrate and the gate structure and fills the groove, and the upper surface of the dielectric layer is flush with the upper surface of the barrier layer. The blocking layer and the dielectric layer in the groove are divided into a plurality of parts, and the size of each part is reduced, so that the dielectric layer is not easy to sink when flattened by adopting a chemical mechanical polishing process, and the performance of the device can be improved.

Description

Semiconductor structure and method of forming the same

Technical Field

The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same.

Background Art

At present, semiconductor technology has penetrated into various fields of life. For example, aerospace, medical devices, and mobile communications are inseparable from chips made by semiconductor technology. Semiconductor integrated circuits usually contain a variety of semiconductor devices, such as high-voltage semiconductor devices, medium-voltage semiconductor devices, and low-voltage semiconductor devices. The advantages of high-voltage semiconductor devices are cost-effectiveness and compatibility with other processes. They have been widely used in display driver IC components, power supplies, power management, communications, automotive electronics, or industrial control.

However, since high-voltage semiconductor devices have a large channel length and width, the gate size located above the channel is also large. When the dielectric layer on the gate surface is ground using a chemical mechanical polishing process, it is easy for a dent to appear on the gate, and even excessive polishing may cause a portion of the gate to be removed, affecting device performance. Therefore, a more effective or reliable technical solution needs to be provided.

Summary of the invention

The present application provides a semiconductor structure and a method for forming the same, which can reduce the generation of recesses when a dielectric layer on a gate surface is polished using a chemical mechanical polishing process, thereby improving device performance.

One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a fourth region; forming a gate structure on the semiconductor substrate in the first region and the fourth region, respectively, wherein a dimension of the gate structure in the first region along a channel length direction is greater than a dimension of the gate structure in the fourth region along the channel length direction; and forming a blocking layer on the gate structure in the first region, the blocking layer comprising a plurality of grooves penetrating the blocking layer.

In some embodiments of the present application, the gate structure includes a gate dielectric layer and a dummy gate layer, and the method further includes: removing the dummy gate layer in the first region and the fourth region, and forming a metal gate on the surface of the gate dielectric layer.

In some embodiments of the present application, a method for forming a blocking layer on a gate structure in the first region, wherein the blocking layer includes a plurality of grooves penetrating the blocking layer, comprises: forming a blocking material layer on the sidewalls and top surfaces of a semiconductor substrate and a gate structure in the first region and a fourth region; etching the blocking material layer to retain only a portion of the blocking material layer located on the top surface of the gate structure in the first region, and forming grooves penetrating the blocking material layer in the blocking material layer to form the blocking layer.

In some embodiments of the present application, the fourth region includes at least one of the second region and the third region.

In some embodiments of the present application, the first region is a high voltage device region, the second region is a medium voltage device region, and the third region is a low voltage device region.

In some embodiments of the present application, the thickness of the barrier layer is 100 angstroms to 250 angstroms.

In some embodiments of the present application, the plurality of grooves include a plurality of first grooves distributed along a channel length direction and a plurality of second grooves distributed along a channel width direction.

In some embodiments of the present application, the method for forming the semiconductor structure also includes: forming a dielectric layer covering the semiconductor substrate, the gate structure and the barrier layer in the first and fourth regions, wherein the dielectric layer fills the plurality of grooves; and removing the dielectric layer above the top surface of the gate structure in the fourth region.

Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate including a first region and a fourth region; a gate structure, located on the semiconductor substrate in the first region and the fourth region, the size of the gate structure in the first region along the channel length direction is greater than the size of the gate structure in the fourth region along the channel length direction; a barrier layer, located on the gate structure in the first region, the barrier layer including a plurality of grooves penetrating the barrier layer; a dielectric layer, located on the semiconductor substrate and the gate structure and filling the grooves, the upper surface of the dielectric layer is flush with the upper surface of the barrier layer. In some embodiments of the present application, the plurality of grooves include a plurality of first grooves distributed along the channel length direction and a plurality of second grooves distributed along the channel width direction.

The semiconductor structure and the method for forming the same described in the present application are such that the barrier layer and the dielectric layer in the groove are divided into several parts, each of which is smaller in size. Therefore, when the dielectric layer is flattened by a chemical mechanical polishing process, it is not easy to be concave, thereby improving device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

1 to 9 are schematic structural diagrams of various steps in a method for forming a semiconductor structure according to an embodiment of the present application.

DETAILED DESCRIPTION

The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

1 to 9 are schematic structural diagrams of various steps in a method for forming a semiconductor structure according to an embodiment of the present application.

An embodiment of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate 100, wherein the semiconductor substrate 100 includes a first region 101 and a fourth region 104; forming gate structures on the semiconductor substrate 100 in the first region 101 and the fourth region 104, respectively, wherein a size of the gate structure in the first region 101 along the channel length direction is greater than a size of the gate structure in the fourth region 104 along the channel length direction; and forming a blocking layer 150 on the gate structure in the first region 101, wherein the blocking layer 150 includes a plurality of grooves penetrating the blocking layer 150.

The method for forming the semiconductor structure described in the present application is described in detail below with reference to the accompanying drawings.

1 , a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a first region 101 and a fourth region 104, the first region 101 and the fourth region 104 in the figure are not drawn strictly according to scale, but are only schematically represented. The semiconductor substrate 100 also includes an isolation structure 110, the isolation structure 110 separates the first region 101 and the fourth region 104.

In some embodiments of the present application, the material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon on insulator (SOI) or germanium on insulator (GOI), etc. The semiconductor substrate 100 may also be a structure with an epitaxial layer grown thereon.

The fourth region 104 includes at least one of the second region and the third region. For example, the semiconductor substrate 100 may include the first region 101 and the second region; the semiconductor substrate 100 may include the first region 101 and the third region; the semiconductor substrate 100 may include the first region 101 and the second region and the third region.

In some embodiments of the present application, the first region 101 is defined as a high-voltage device region; the second region is defined as a medium-voltage device region, and the third region is defined as a low-voltage device region. If the channel size in the first region 101 is larger than the channel size in the second region, the electron migration path in the first region 101 is longer than the electron migration path in the second region, and the voltage of the first region 101 when working is higher than the voltage of the second region when working. Similarly, the voltage of the second region 102 when working is higher than the voltage of the third region when working, thereby defining the high-voltage device region, the medium-voltage device region, and the low-voltage device region.

In some embodiments of the present application, the isolation structure 110 may be composed of silicon oxide or a composite layer of silicon oxide and silicon nitride or silicon oxynitride. The isolation structure 110 may be used to separate the first region 101 and the fourth region 104 in the semiconductor substrate 100.

2 , the semiconductor substrate 100 in the first region 101 is etched so that the surface of the semiconductor substrate in the first region 101 is lower than the surface of the semiconductor substrate in the fourth region 104. The thickness of the gate dielectric layer in the fourth region 104 is greater than the thickness of the gate dielectric layer in the first region 101, so a portion of the semiconductor substrate 100 in the fourth region 104 may be etched to accommodate the gate dielectric layer in the fourth region 104.

In some embodiments of the present application, the semiconductor substrate 100 of the first region 101 can be etched by a dry or wet etching process. Depending on the etching process and the etching gas or etching solution used in the etching process, the isolation structure 110 located in the first region will also be etched to varying degrees. In Figure 2, the surface of the isolation structure 110 in the first region is schematically shown to be flush with the surface of the semiconductor substrate 100 in the first region 101 after being etched.

3 to 5 , gate structures are formed on the semiconductor substrate 100 in the first region 101 and the fourth region 104 , respectively. The size of the gate structure in the first region 101 along the channel length direction is greater than the size of the gate structure in the fourth region 104 along the channel length direction.

Referring to FIG. 3 , gate dielectric material layers are formed on the surface of the semiconductor substrate 100 in the first region 101 and the fourth region 104, respectively. The top surface of the gate dielectric material layer in the first region is lower than the top surface of the gate dielectric material layer in the fourth region, and the thickness of the gate dielectric material layer in the first region is greater than the thickness of the gate dielectric material layer in the fourth region. For example, a gate dielectric material layer 120a of designed thickness is formed on the surface of the semiconductor substrate 100 in the first region 101, and a gate dielectric material layer 120b of designed thickness is formed on the surface of the semiconductor substrate 100 in the fourth region 104. In an embodiment of the present application, the top surface of the gate dielectric material layer 120a is lower than the top surface of the gate dielectric material layer 120b, and the existence of the height difference between the gate dielectric material layer 120a and the gate dielectric material layer 120b facilitates the subsequent formation of a blocking layer on the surface of the gate dielectric material layer 120b to protect the pseudo gate material layer. In the embodiment of the present application, the gate dielectric material layer 120a of the first region is generally formed first, and then the gate dielectric material layer 120b of the fourth region is formed.

In some embodiments of the present application, a method of forming the gate dielectric material layer 120 a and the gate dielectric material layer 120 b includes a thermal oxidation process, an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, or the like.

Referring to FIG4 , a dummy gate material layer 130a is formed on the surface of the gate dielectric material layer 120a, and a dummy gate material layer 130b is formed on the surface of the gate dielectric material layer 120b. The dummy gate material layer 130a and the dummy gate material layer 130b can be formed simultaneously or separately. In the embodiment of the present application, the dummy gate material layer 130a and the dummy gate material layer 130b are formed simultaneously, and the thickness of the dummy gate material layer 130a and the dummy gate material layer 130b are the same.

The material of the dummy gate material layer 130 a and the dummy gate material layer 130 b is, for example, polysilicon, which can be formed by a chemical vapor deposition process or a physical vapor deposition process.

Referring to Figure 5, the pseudo gate material layer 130a and the gate dielectric material layer 120a in the first region are etched to expose the semiconductor substrate to form a pseudo gate 131a and a gate dielectric layer 121a, and the pseudo gate material layer 130b and the gate dielectric material layer 120b in the fourth region are etched to expose the semiconductor substrate to form a pseudo gate 131b and a gate dielectric layer 121b, forming stacked pseudo gate structures in the active areas of the first region and the fourth region, respectively.

In some embodiments of the present application, a method of etching the gate dielectric material layer and the dummy gate material layer includes dry etching or wet etching.

The gate dielectric layer 121 a and the gate dielectric layer 121 b include a high dielectric constant material, for example, may include at least one of silicon oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide and aluminum oxide.

In some embodiments of the present application, the length of the dummy gate 131 a on the first region 101 ranges from 1 micrometer to 12 micrometers.

In some embodiments of the present application, the length of the dummy gate 131 b on the fourth region 104 is in a range of 0.03 micrometers to 3 micrometers.

Embodiments of the present application also include forming sidewalls (not shown) on the sidewalls of the pseudo gate structure in the first region and the fourth region and performing ion implantation in the semiconductor substrate on both sides of the pseudo gate structure to form a source doping layer and a drain doping layer (not shown).

Referring to Figure 6, a blocking material layer (not shown) is formed on the sidewalls and top surfaces of the semiconductor substrate and the gate structure in the first region 101 and the fourth region 104; the blocking material layer is etched to retain only a portion of the blocking material layer located on the top surface of the gate structure in the first region 101, and a groove 160 is formed in the blocking material layer that penetrates the blocking material layer to form the blocking layer 150.

In some embodiments of the present application, the material of the barrier layer 150 includes silicon nitride.

In some embodiments of the present application, the method of forming the barrier layer 150 includes a chemical vapor deposition process and a physical vapor deposition process.

In some embodiments of the present application, the barrier layer 150 has a thickness of 100 angstroms to 250 angstroms. The barrier layer 150 is relatively thin relative to the semiconductor structure, and even if the barrier layer 150 remains on the gate structure, it will not affect the performance of the semiconductor device.

Since the first region 101 is a high-voltage device region, the channel size of the high-voltage device region is relatively large, and the size of the pseudo gate 131a on the first region 101 is also relatively large. It is easy to produce a depression on the pseudo gate 131a during the subsequent chemical mechanical polishing. Therefore, the plurality of grooves 160 are formed in the barrier layer 150 on the first region 101. The barrier layer 150 is divided into several parts by the grooves 160, and the size of each part becomes smaller. Therefore, it is not easy to produce a depression during the subsequent chemical mechanical polishing process, which can improve the device performance.

In some embodiments of the present application, the method for etching the blocking material layer to retain only a portion of the blocking material layer located on the top surface of the gate structure in the first region 101 and forming grooves 160 in the blocking material layer that penetrate the blocking material layer includes: forming a patterned photoresist on the semiconductor substrate 100; the patterned photoresist defines the positions of the plurality of grooves 160 and exposes the blocking layer 150 on the fourth region 104; etching the blocking layer using the patterned photoresist as a mask to form a plurality of grooves 160 that penetrate the blocking layer 150 on the first region 101 and remove the blocking layer 150 on the fourth region 104.

In order to more completely and clearly illustrate the trench 160 , the embodiment of the present application also provides a top view of the semiconductor substrate 100 .

Referring to Fig. 7, Fig. 7 is a top view of the semiconductor structure according to an embodiment of the present application. In order to briefly illustrate the structure and distribution of the plurality of trenches 160, a part of the structure, such as the isolation structure and the sidewall, is omitted in the figure.

Referring to FIG7 , direction A is defined as the channel length direction, and direction B is defined as the channel width direction. The semiconductor substrate 100 includes a first region 101 and a fourth region 104. A barrier layer 150 and a plurality of trenches 160 penetrating the barrier layer 150 are formed on the gate structure of the first region 101; the barrier layer 150 on the gate structure of the fourth region 104 is removed to expose the dummy gate 131b.

In some embodiments of the present application, the plurality of grooves 160 include a plurality of first grooves 161 distributed along the channel length direction A and a plurality of second grooves 162 distributed along the channel width direction B. It should be noted that the second groove 162 at the bottom in FIG. 7 is relatively wide. The second groove 162 at the bottom is to facilitate the etching and removal of the pseudo gate there and replace it with a metal gate in the subsequent process. Since the height of the pseudo gate under the second groove 162 at the bottom is slightly higher than the height of the pseudo gate of the remaining part, it will not affect the formation of the metal gate. The groove 160 divides the barrier layer 150 into several parts, and the size of each part becomes smaller. Therefore, it is not easy to produce a depression on the pseudo gate during the chemical mechanical polishing process, which can improve the device performance.

In some other embodiments of the present application, the plurality of grooves 160 are distributed along the channel length direction. In some other embodiments of the present application, the plurality of grooves 160 are distributed along the channel width direction. Specifically, the structure and distribution of the plurality of grooves 160 can be designed according to the situation of the recess generated on the pseudo gate in the actual process.

In some embodiments of the present application, the method for forming the semiconductor structure also includes: forming a dielectric layer covering the semiconductor substrate, the gate structure and the blocking layer of the first region 101 and the fourth region 104, wherein the dielectric layer fills the plurality of grooves; and removing the dielectric layer 170 that is higher than the top surface of the gate structure of the fourth region 104.

8 , a dielectric layer 170 is formed on the semiconductor substrate 100 , the gate structure and the barrier layer 150 .

In some embodiments of the present application, the material of the dielectric layer 170 includes silicon oxide.

In some embodiments of the present application, the method of forming the dielectric layer 170 includes a chemical vapor deposition process and a physical vapor deposition process.

9 , a chemical mechanical polishing process is used to remove the dielectric layer 170 above the top surface of the gate structure in the fourth region 104 .

In conventional processes, since there is no barrier layer 150, and the first region 101 is a high-voltage device region, the channel size of the high-voltage device region is relatively large, and the size of the pseudo gate on the first region 101 is also relatively large, and it is easy to generate a depression on the pseudo gate during chemical mechanical polishing. In the semiconductor structure forming method described in the embodiment of the present application, the barrier layer 150 having a plurality of grooves 160 is formed on the first region 101, and the barrier layer 150 and the dielectric layer 170 located in the grooves 160 are divided into a plurality of parts, and the size of each part becomes smaller. Therefore, when the dielectric layer 170 is flattened by a chemical mechanical polishing process, no depression will be generated on the pseudo gate 131a, which can improve the device performance.

In some embodiments of the present application, the method for forming the semiconductor structure further includes: removing part of the dummy gate layer 131a in the first region 101 and the dummy gate layer 131b in the fourth region 104, and forming a metal gate on the surface of the gate dielectric layer 121a and the gate dielectric layer 121b.

The method for forming a semiconductor structure described in the present application forms a barrier layer and a plurality of grooves penetrating the barrier layer on the gate structure of the first region, and the barrier layer and the dielectric layer located in the grooves are divided into a plurality of parts, each of which is smaller in size. Therefore, when the dielectric layer is flattened by a chemical mechanical polishing process, it is not easy to be concave, thereby improving device performance.

An embodiment of the present application also provides a semiconductor structure. Referring to Figure 9, the semiconductor structure includes: a semiconductor substrate 100, the semiconductor substrate 100 includes a first region 101 and a fourth region 104, and the semiconductor substrate 100 includes an isolation structure 110, the isolation structure 110 separates the first region 101 and the fourth region 104; a gate structure, located on the semiconductor substrate in the first region 101 and the fourth region 104; a blocking layer 150, located on the gate structure in the first region 101, the blocking layer 150 includes a plurality of grooves penetrating the blocking layer 150; a dielectric layer 170, located on the semiconductor substrate 100 and the gate structure and filling the grooves, the upper surface of the dielectric layer 170 is flush with the upper surface of the blocking layer 150.

9 , the material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon on insulator (SOI) or germanium on insulator (GOI), etc. The semiconductor substrate 100 may also be a structure with an epitaxial layer grown thereon.

The semiconductor substrate surface of the first region 101 is lower than the semiconductor substrate surface of the fourth region 104. The fourth region 104 includes at least one of the second region and the third region, for example, the semiconductor substrate 100 may include the first region 101 and the second region; the semiconductor substrate 100 may include the first region 101 and the third region; the semiconductor substrate 100 may include the first region 101, the second region and the third region.

In some embodiments of the present application, the first region 101 is defined as a high-voltage device region; the second region is defined as a medium-voltage device region, and the third region is defined as a low-voltage device region. If the channel size in the first region 101 is larger than the channel size in the second region, the electron migration path in the first region 101 is longer than the electron migration path in the second region, and the voltage of the first region 101 when working is higher than the voltage of the second region when working. Similarly, the voltage of the second region 102 when working is higher than the voltage of the third region when working, thereby defining the high-voltage device region, the medium-voltage device region, and the low-voltage device region.

In some embodiments of the present application, the isolation structure 110 may be composed of silicon oxide or a composite layer of silicon oxide and silicon nitride or silicon oxynitride. The isolation structure 110 may be used to separate the first region 101 and the fourth region 104 in the semiconductor substrate 100.

Continuing to refer to FIG9 , a dummy gate 131a and a gate dielectric layer 121a are formed on the semiconductor substrate of the first region 101, and a dummy gate 131b and a gate dielectric layer 121b are formed on the semiconductor substrate of the fourth region 104. The thickness of the gate dielectric layer 121a is greater than the thickness of the gate dielectric layer 121b. The length of the dummy gate 131a is greater than the length of the dummy gate 131b (i.e., the size of the dummy gate 131a in the channel length direction is greater than the size of the dummy gate 131b in the channel length direction).

In some embodiments of the present application, a top surface of the gate dielectric layer 121 a is lower than a top surface of the gate dielectric layer 121 b .

The gate dielectric layer 121 a and the gate dielectric layer 121 b include a high dielectric constant material, for example, may include at least one of silicon oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide and aluminum oxide.

In some embodiments of the present application, the thickness of the dummy gate 131 a on the first region 101 is equal to the thickness of the dummy gate 131 b on the fourth region 104 .

In some embodiments of the present application, the length of the dummy gate 131 a on the first region 101 ranges from 1 micrometer to 12 micrometers.

In some embodiments of the present application, the length of the dummy gate 131 b on the fourth region 104 is in a range of 0.03 micrometers to 3 micrometers.

The embodiments of the present application also include sidewalls (not shown) formed on the sidewalls of the dummy gate structure in the first region and the fourth region, and source doping layers and drain doping layers (not shown) formed in the semiconductor substrate on both sides of the dummy gate structure.

Continuing to refer to FIG. 9 , a barrier layer 150 is formed on the gate structure in the first region 101 , and the barrier layer 150 includes a plurality of trenches penetrating the barrier layer 150 .

In some embodiments of the present application, the material of the barrier layer 150 includes silicon nitride.

In some embodiments of the present application, the barrier layer 150 has a thickness of 100 angstroms to 250 angstroms. The barrier layer 150 is relatively thin relative to the semiconductor structure, and even if the barrier layer 150 remains on the gate structure, it will not affect the performance of the semiconductor device.

Since the first region 101 is a high-voltage device region, the channel size of the high-voltage device region is relatively large, and the size of the pseudo gate 131a on the first region 101 is also relatively large. It is easy to produce a depression on the pseudo gate 131a during the subsequent chemical mechanical polishing. Therefore, the plurality of grooves 160 are formed in the barrier layer 150 on the first region 101. The barrier layer 150 is divided into several parts by the grooves 160, and the size of each part becomes smaller. Therefore, it is not easy to produce a depression during the subsequent chemical mechanical polishing process, which can improve the device performance.

In order to more completely and clearly illustrate the trench 160 , the embodiment of the present application also provides a top view of the semiconductor substrate 100 .

Referring to Fig. 7, Fig. 7 is a top view of the semiconductor structure according to an embodiment of the present application. In order to briefly illustrate the structure and distribution of the plurality of trenches 160, a part of the structure, such as the isolation structure and the sidewall, is omitted in the figure.

Referring to FIG7 , direction A is defined as the channel length direction, and direction B is defined as the channel width direction. The semiconductor substrate 100 includes a first region 101 and a fourth region 104. A barrier layer 150 and a plurality of trenches 160 penetrating the barrier layer 150 are formed on the gate structure of the first region 101; the barrier layer 150 on the gate structure of the fourth region 104 is removed to expose the dummy gate 131b.

In some embodiments of the present application, the plurality of grooves 160 include a plurality of first grooves 161 distributed along the channel length direction A and a plurality of second grooves 162 distributed along the channel width direction B. It should be noted that the second groove 162 at the bottom in FIG. 7 is relatively wide. The second groove 162 at the bottom is to facilitate the etching and removal of the pseudo gate there and replace it with a metal gate in the subsequent process. Since the height of the pseudo gate under the second groove 162 at the bottom is slightly higher than the height of the pseudo gate of the remaining part, it will not affect the formation of the metal gate. The groove 160 divides the barrier layer 150 into several parts, and the size of each part becomes smaller. Therefore, it is not easy to produce a depression on the pseudo gate during the chemical mechanical polishing process, which can improve the device performance.

In some other embodiments of the present application, the plurality of grooves 160 are distributed along the channel length direction. In some other embodiments of the present application, the plurality of grooves 160 are distributed along the channel width direction. Specifically, the structure and distribution of the plurality of grooves 160 can be designed according to the situation of the recess generated on the pseudo gate in the actual process.

9 , a dielectric layer 170 is formed on the semiconductor substrate 100 , the gate structure and the barrier layer 150 , the top surface of the dielectric layer 170 is coplanar with the top surface of the barrier layer 150 , and the dielectric layer 170 fills the trench.

In some embodiments of the present application, the material of the dielectric layer 170 includes silicon oxide.

The semiconductor structure described in the present application forms a barrier layer and a plurality of grooves penetrating the barrier layer on the gate structure of the first region, and the plurality of grooves are filled with a dielectric layer. The barrier layer and the dielectric layer located in the grooves are divided into a plurality of parts, and the size of each part becomes smaller. Therefore, when the dielectric layer is flattened by a chemical mechanical polishing process, it is not easy to be recessed, which can improve the device performance.

In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

It should be understood that the term "and/or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may also be present.

Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and/or plan views and/or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims (10)

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a fourth region;

Etching the semiconductor substrate of the first region to make the surface of the semiconductor substrate of the first region lower than the surface of the semiconductor substrate of the fourth region;

Forming a gate structure on the semiconductor substrate of the first region and the semiconductor substrate of the fourth region respectively, wherein the dimension of the gate structure of the first region along the channel length direction is larger than that of the gate structure of the fourth region along the channel length direction, the top surface of the gate structure of the first region is lower than that of the gate structure of the fourth region, and the thickness of the gate structure of the first region is larger than that of the gate structure of the fourth region;

a barrier layer is formed on the gate structure of the first region, the barrier layer including a plurality of trenches extending through the barrier layer.

2. The method of forming a semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer and a dummy gate layer, the method further comprising: and removing the pseudo gate layers of the first region and the fourth region, and forming a metal gate on the surface of the gate dielectric layer.

3. The method of forming a semiconductor structure of claim 1, wherein forming a barrier layer on the gate structure of the first region, the barrier layer comprising a plurality of trenches extending through the barrier layer, comprises:

Forming a barrier material layer on the semiconductor substrate of the first region and the fourth region and the side wall and the top surface of the gate structure;

And etching the barrier material layer, only retaining part of the barrier material layer positioned on the top surface of the first region gate structure, and forming a groove penetrating through the barrier material layer in the barrier material layer to form the barrier layer.

4. The method of forming a semiconductor structure of claim 1, wherein the fourth region comprises at least one of a second region and a third region.

5. The method of forming a semiconductor structure of claim 4, wherein the first region is a high voltage device region, the second region is a medium voltage device region, and the third region is a low voltage device region.

6. The method of forming a semiconductor structure of claim 1, wherein the barrier layer has a thickness of 100 a to 250 a.

7. The method of forming a semiconductor structure of claim 1, wherein the plurality of trenches comprises a plurality of first trenches distributed along a channel length direction and a plurality of second trenches distributed along a channel width direction.

8. The method of forming a semiconductor structure of claim 1, further comprising: forming a dielectric layer covering the semiconductor substrate, the gate structure and the barrier layer in the first region and the fourth region, wherein the dielectric layer fills the trenches; and removing the dielectric layer higher than the top surface of the fourth region gate structure.

9. A semiconductor structure, comprising:

A semiconductor substrate comprising a first region and a fourth region, the semiconductor substrate surface of the first region being lower than the semiconductor substrate surface of the fourth region;

the grid structure is positioned on the semiconductor substrate of the first region and the fourth region, the size of the grid structure of the first region along the length direction of the channel is larger than that of the grid structure of the fourth region along the length direction of the channel, the top surface of the grid structure of the first region is lower than that of the grid structure of the fourth region, and the thickness of the grid structure of the first region is larger than that of the grid structure of the fourth region;

the barrier layer is positioned on the grid structure of the first area and comprises a plurality of grooves penetrating through the barrier layer;

and the dielectric layer is positioned on the semiconductor substrate and the gate structure and fills the groove, and the upper surface of the dielectric layer is flush with the upper surface of the barrier layer.

10. The semiconductor structure of claim 9, wherein the plurality of trenches comprises a plurality of first trenches distributed along a channel length direction and a plurality of second trenches distributed along a channel width direction.