CN113760814B - Comprehensive computing system - Google Patents
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Abstract
The invention relates to a comprehensive computing system which comprises a traditional computing unit, a cooperative computing unit, a custom IPU bus slot, a custom computing unit and a power supply unit.
Description
Technical Field
The invention relates to a new computing architecture, in particular to a comprehensive computing system.
Background
The requirements of an automation control site are various, various personalized requirements such as real-time, redundancy, high bandwidth, synchronization and the like are difficult to meet, and the cost for targeted development is great. The working environment is also very severe, and high temperature, high humidity, dust, salt fog, vibration, electromagnetic interference and the like all provide serious challenges for the reliability of equipment. Once the system fails, economic loss is directly caused, and even personnel life safety is affected.
In particular, in some data acquisition applications, the amount of data that needs to be acquired or transmitted by a conventional computing unit is very large, so that multiple high-speed signal acquisition custom computing units or high-speed signal output custom computing units need to be installed in the system, if pure GPIO protocol signal lines are used, all custom computing units communicate with the conventional computing unit through parallel computing units, and the parallel computing units and the conventional computing units have only one high-speed data transmission channel, so that bandwidth bottleneck is caused.
Disclosure of Invention
The embodiment of the invention aims to provide a comprehensive computing system which aims to meet various personalized requirements of an automatic control field.
The embodiments of the present invention are so implemented,
An integrated computing system, characterized in that,
The integrated computing system includes a conventional computing unit, one or more co-computing units, one or more custom IPU bus slots, one or more custom computing units,
The conventional computing units are directly connected to one or more co-computing units,
The traditional computing unit, the assistant computing unit and the custom computing unit are all connected with the IPU bus slot, the traditional computing unit is connected with one or more custom IPU bus slots, each assistant computing unit is connected with one or more custom IPU bus slots, each custom computing unit is connected with one custom IPU bus slot,
The custom IPU bus slot comprises one or more protocol signal lines and GPIO signal lines, the traditional computing unit and the co-computing unit are directly communicated through the protocol signal lines of the traditional computing unit, the traditional computing unit and the custom computing unit are communicated through the protocol signal lines of the traditional computing unit in the custom IPU bus slot, and the co-computing unit and the custom computing unit are communicated through the GPIO signal lines in the custom IPU bus slot.
The invention can meet various personalized requirements of an automatic control site through the mutual coordination of the traditional calculation unit, the cooperative calculation unit and the customized calculation unit.
Drawings
The invention will be described in further detail with reference to the accompanying drawings and embodiments:
Figure 1 is a block diagram of the whole,
Figure 2 is a block diagram of an IPU bus slot,
Figure 3 is a block diagram of the co-computing unit,
Figure 4 is a block diagram of the co-computing unit,
Figure 5 is a block diagram of the co-computing unit,
Figure 6 is a block diagram of the co-computing unit,
Figure 7 is a block diagram of the co-computing unit communication module,
Figure 8 is a block diagram of the co-computing unit communication module,
Figure 9 is a block diagram of the co-computing unit communication module,
Figure 10 is a block diagram of the timing module of the co-computing unit interface,
Figure 11 is a block diagram of the timing module of the co-computing unit interface,
Figure 12 is a block diagram of the timing module of the co-computing unit interface,
Figure 13 is a block diagram of the timing module of the co-computing unit interface,
Figure 14 is a block diagram of the co-computing unit parallel computing module,
Figure 15 is a block diagram of a co-computing unit handshake module,
Figure 16 is a block diagram of the custom computing unit,
Figure 17 is a block diagram of the custom computing unit,
Figure 18 is a block diagram of the custom computing unit,
Figure 19 is a block diagram of the custom computing unit,
Figure 20 is a block diagram of the custom computing unit,
Figure 21 is a block diagram of the custom computing unit,
Figure 22 is a block diagram of the custom computing unit,
Figure 23 is a block diagram of the custom computing unit,
Figure 24 is a block diagram of a custom computing unit,
Figure 25 is a block diagram of the custom computing unit,
Figure 26 is a block diagram of the custom computing unit,
Fig. 27 is a block diagram of a custom computing unit.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
The requirements of an automation control site are various, various personalized requirements such as real-time, redundancy, high bandwidth, synchronization and the like are difficult to meet, and the cost for targeted development is great. The working environment is also very severe, and high temperature, high humidity, dust, salt fog, vibration, electromagnetic interference and the like all provide serious challenges for the reliability of equipment. Once the system fails, economic loss is directly caused, and even personnel life safety is affected.
For example, the existing automation control field requirements have higher technical requirements, and the following problems in terms of architecture, computing power, interfaces and buses are caused:
Some applications require synchronizing the acquisition process of multiple channels,
Some applications have a logical relationship between input and output channels, and respond in real time,
There are applications that require ensuring the closed loop control accuracy of the overall system,
The channels can come from different functional boards, the co-processing capability between boards of the industrial personal computer must be completed by a CPU, the co-processing speed of the boards is at most ms, the requirements are difficult to meet,
Some applications have very high stability requirements, and if the operating system crashes or restarts, the external channel cannot be controlled correctly, which may cause equipment damage or even casualties.
Through long-term careful practice and design of a large number of hardware architects, we propose a comprehensive computing system which can effectively solve the above problems. The specific scheme is as follows (as shown in figure 1):
An integrated computing system, characterized in that,
The integrated computing system includes a conventional computing unit, one or more co-computing units, one or more custom IPU bus slots, one or more custom computing units,
The conventional computing units are directly connected to one or more co-computing units,
The traditional computing unit, the assistant computing unit and the custom computing unit are all connected with the IPU bus slot, the traditional computing unit is connected with one or more custom IPU bus slots, each assistant computing unit is connected with one or more custom IPU bus slots, each custom computing unit is connected with one custom IPU bus slot,
The custom IPU bus slot comprises one or more protocol signal lines and GPIO signal lines (shown in figure 2), the traditional computing unit and the cooperative computing unit are directly communicated through the protocol signal lines of the traditional computing unit, the traditional computing unit and the custom computing unit are communicated through the protocol signal lines of the traditional computing unit in the custom IPU bus slot, and the cooperative computing unit and the custom computing unit are communicated through the GPIO signal lines in the custom IPU bus slot.
Because the co-computing unit and the custom computing unit are relatively independent of the traditional computing unit, if the traditional computing unit crashes or restarts, the co-computing unit and the custom computing unit can correctly control the external channel, thereby not causing equipment damage and further causing personal injury.
In particular, the temperature stability is required to be extremely high in some cases. The fan is adopted for heat dissipation of the general industrial personal computer, dust can be accumulated by the fan for a long time, the heat dissipation effect can be poor, even the computer can be out of order, and the computer can be out of order due to the fact that the temperature of the CPU is too high. In particular, in some occasions, because of a lot of processing dust, the general industrial personal computer is designed with ventilation holes for heat dissipation, and the dust enters the interior of the case in a large amount through the holes and is accumulated in the fan or other key parts, so that the CPU is in fault, and finally, the whole system is in fault, and huge loss is caused. In this case, the external channel is correctly controlled by the co-computing unit and the custom computing unit, so that equipment damage and personal injury are avoided.
Some devices are not found to have design defects until they are commissioned on site or even after they are sold, and general hardware devices can only be resolved by recall. In this case, the invention can solve the problem by only remotely upgrading the relevant firmware of the cooperative computing unit and the customized computing unit, thereby greatly reducing the cost of repairing the problem and shortening the upgrading time.
Preferably, the traditional computing unit and the co-computing unit directly communicate through PCI/PCIe protocol signal lines of the traditional computing unit. Because the PCI/PCIe protocol signal lines have a much larger bandwidth than the common bus protocol, a single legacy computing unit may often support fast communication between multiple, custom computing units and legacy computing units.
In some applications, because the data size is very large, if the data is transmitted to the computer through the expansion bus, the bus bandwidth is insufficient, and only the calculation data with processing delay is transmitted to the computer, so that the industrial personal computer is difficult to meet. Because the PCI/PCIe protocol signal lines have a much larger bandwidth than the common bus protocol, a single legacy computing unit may often support fast communication between multiple, custom computing units and legacy computing units.
Preferably, the legacy computing unit communicates with the custom computing unit via a PCI/PCIe or USB protocol signal line that is self-contained with the legacy computing unit in the custom IPU bus slot.
The expansion of the general expansion card and the industrial personal computer must be designed into PCI or PCIe interfaces to work normally, the interface design difficulty is high, the cost is high, and the interface can not be in the same connector, and a plurality of common interfaces are supported: such as pcie\usb\gpio, etc. And the self-defined IPU bus slot supports PCI/PCIe or USB protocol, so that the interface design difficulty is low.
From the complexity of the bus, PCIe > USB > GPIO, which results in PCIe > USB > GPIO at learning cost. The higher the speed of the signal, the higher the skill requirement for signal routing, and the higher the complexity of problem debugging. Because the traditional industrial personal computer only has PCIe and USB buses, some simple low-speed applications also have to be converted through a high-speed high-bandwidth bus, so that the threshold of design is greatly improved. The IPU provides these three buses simultaneously for the user to use, who may be free to choose any one of the familiar buses to develop, through his own ability, past experience and success.
In the board card design of the traditional industrial personal computer, whether the board card of PCIe/PCI or USB bus is developed, the standard buses are converted into local buses through a protocol conversion module, and then various interface circuits are hung on the local buses. The protocol conversion modules are similar in structure and function for boards of different functions. Any standard bus may be used to convert the local bus, generally as long as the bandwidth is satisfactory. The IPU's co-computing unit converts the standard computer bus into a plurality of GPIOs, and then divides the GPIOs into a plurality of groups for different IPU slots to be used as local buses, so that when users design different functional board cards, interface circuits can be directly designed from the GPIOs, namely, only the custom computing unit needs to be designed, thereby greatly reducing development difficulty, and saving development time, production and maintenance cost.
Preferably, the traditional computing unit adopts an X86 platform or an ARM platform, and the cooperative computing unit adopts an FPGA platform or a CPLD platform.
Some application site environments are very complex, and the designer cannot find the application from the previous selection of the expansion hardware to the use site, and the re-purchase or the re-design is not available at this time. There is therefore an urgent need to be able to achieve this by programmable hardware, whereas FPGA or CPLD platforms can.
The self-defined IPU bus slot is a flat feeler type golden finger or a pinhole type EuroCard connector.
When the flat feeler type golden finger is adopted, vibration frequently occurs in an application environment of impact or vibration to cause a fault of loose contact, and in addition, the golden finger is oxidized to cause a fault due to poor contact along with the time, but the flat feeler type golden finger has a simple structure, low manufacturing cost and convenient plugboard.
When the pinhole type EuroCard connector is adopted, the industrial personal computer is low in replacement cost for the scene of frequent change or upgrading requirement of specific application, and can not malfunction due to poor contact in some impact and vibration environments. The specific application of some occasions is changed frequently or needs to be updated, and the industrial personal computer can only replace the board cards of various golden finger structures according to the situation, so that the replacement cost is high, the golden fingers are easily damaged in the replacement process, the problems of poor contact and the like are caused, and the problem of poor contact and failure in some impact and vibration environments is easily caused.
The above technical solution may be applicable to some of the following scenarios.
Application scenario 1:
Some algorithms for applying data processing are complex or there are a large number of parallel computing tasks that cannot be directly undertaken by the CPU of X86. In some lumber processing plants, accidents in which workers inadvertently cut their fingers often occur, and there has been no very perfect solution for at least 100ms to react from human perception of pain, long enough to cause irreparable accidents.
Aiming at the application scene, the specific technical scheme is as follows:
The co-computing unit consists of a communication module, a parallel computing module, a handshake module and an interface time sequence module,
The parallel computing module is respectively connected with the communication module and the interface time sequence module, and the handshake module is respectively connected with the communication module and the interface time sequence module, wherein:
The communication module is connected with the traditional computing unit and communicates with the PCI/PCIe protocol main controller of the traditional computing unit through a PCI/PCIe protocol signal line,
The parallel computing module is used for parallel processing or computing, acquiring computing tasks through the communication module or the interface time sequence module, outputting computing results to the communication module or the interface time sequence module,
The handshake module is used for processing the synchronous signals of the interface timing module,
The interface timing module is connected with the custom computing unit and used for controlling an external interface of the custom computing unit.
The problem can be easily solved by using the comprehensive computing system, the comprehensive computing system utilizes vibration data of the electric saw cut by the custom computing unit with the acquisition function, then analyzes the vibration data by the parallel computing unit of the cooperative computing unit to identify whether wood or human body is cut currently, if the wood or human body is cut currently, the electric saw is controlled to stop immediately by the custom computing unit with the notification of the braking function through the handshake module, the whole process is completed through hardware computation, and the method has high reliability and high real-time performance, and the whole process can not exceed 1ms. When such an accident occurs, the fingers have only some skin trauma, and the electric saw has stopped.
Application scenario 2:
In the distributed synchronous acquisition application, the PPS signals of the GPS are used for synchronization, and because the PPS signals are pulse signals of one per second, when other subsystems needing synchronization do not receive pulses as synchronous signals, the synchronous signals need to be converted; when the synchronization period of other systems is not 1S, the synchronous signals need to be subjected to phase locking and frequency division; the existing data acquisition systems all need other synchronized subsystems to be customized to achieve these functions.
Aiming at the application scene, the specific technical scheme is as follows:
The co-computing unit consists of a communication module, a handshake module and an interface time sequence module,
The handshake module is respectively connected with the communication module and the interface time sequence module,
Wherein:
The communication module is connected with the traditional computing unit and communicates with the PCI/PCIe protocol main controller of the traditional computing unit through a PCI/PCIe protocol signal line,
The handshake module is used for processing the synchronous signals of the interface timing module,
The interface timing module is connected with the custom computing unit and used for controlling an external interface of the custom computing unit.
Some applications require synchronization of the acquisition process of multiple channels, and some applications have logical relationships between input and output channels and respond in real time. Some applications require ensuring the closed loop control accuracy of the whole system. The channels may come from different functional boards, and the co-processing capability between boards of the industrial personal computer must be completed through a CPU, and the co-processing speed of the boards is at most ms, which is difficult to meet the requirements. The IPU can directly utilize the handshake mode of the co-computing unit to realize various synchronization requirements of each custom computing unit. The handshake module mainly provides synchronous clocks for the receiving time sequence modules, and helps signals between different interface time sequence modules or start and stop and the like, and real-time data transmission between the modules. Some tasks are accomplished by two different custom computing interface units working in turn, so that when switching tasks between them, the opposite party is notified by handshaking, which would take too long to be efficient if the opposite party were notified by a conventional computing unit.
Application scenario 3:
In the thermal strength test of the rocket, a huge temperature field needs to be designed to simulate the severe change of the temperature in the rising process of the rocket. Thus, a distributed high performance closed loop controller is needed, the control period of which must be less than 0.1ms. The conventional closed-loop control is completed in a conventional computing unit, and the conventional closed-loop control period often cannot meet the requirement due to more communication links and dependence on operating system scheduling.
Aiming at the application scene, the specific technical scheme is as follows:
the co-computing unit consists of a communication module, a parallel computing module and an interface time sequence module,
The parallel computing module is respectively connected with the communication module and the interface time sequence module,
Wherein:
The communication module is connected with the traditional computing unit and communicates with the PCI/PCIe protocol main controller of the traditional computing unit through a PCI/PCIe protocol signal line,
The parallel computing module is used to process parallel computing tasks,
The interface timing module is connected with the custom computing unit and used for controlling an external interface of the custom computing unit.
Some algorithms for applying data processing are complex or there are a large number of parallel computing tasks that cannot be directly undertaken by the CPU of X86. In the solution of the IPU, all closed loop calculation is completed through a parallel calculation module of the cooperative calculation unit, the communication links are few, hardware calculates and judges in real time, and the closed loop control period is easy to realize for 0.1ms.
Application scenario 4:
In some data acquisition applications, because the signals to be acquired are special, so that standard shelf products cannot be purchased, a data acquisition card is custom-developed and developed conventionally, and the acquisition card comprises an external interface, time sequence control and a communication interface, so that the board card is difficult to develop, long in period and high in risk.
Aiming at the application scene, the specific technical scheme is as follows:
the co-computing unit consists of a communication module and an interface time sequence module,
The communication module is directly connected with the interface timing module,
Wherein:
The communication module is connected with the traditional computing unit and communicates with the PCI/PCIe protocol main controller of the traditional computing unit through a PCI/PCIe protocol signal line,
The interface timing module is connected with the custom computing unit and used for controlling an external interface of the custom computing unit.
Some application site environments are very complex, and the designer cannot find the application from the previous selection of the expansion hardware to the use site, and the re-purchase or the re-design is not available at this time. There is thus an urgent need to be able to pass through programmable hardware. By adopting the IPU system, only the custom computing unit is required to be developed as an external interface, and the time sequence control and communication interface can be directly realized by adopting the interface time sequence module and the communication module of the co-computing unit, so that the difficulty of the whole development process is greatly reduced, the period is shortened, and the research and development risk is greatly reduced.
In the board card design of the traditional industrial personal computer, whether the board card of PCIe/PCI or USB bus is developed, the standard buses are converted into local buses through a protocol conversion module, and then various interface circuits are hung on the local buses. The protocol conversion modules are similar in structure and function for boards of different functions. Any standard bus may be used to convert the local bus, generally as long as the bandwidth is satisfactory. The IPU's co-computing unit converts the standard computer bus into a plurality of GPIOs, and then divides the GPIOs into a plurality of groups for different IPU slots to be used as local buses, so that when users design different functional board cards, interface circuits can be directly designed from the GPIOs, namely, only the custom computing unit needs to be designed, thereby greatly reducing development difficulty, and saving development time, production and maintenance cost.
Application scenario 5:
In some data acquisition applications, the amount of data required to be acquired or transmitted by a conventional computing unit is very large, so that multiple high-speed signal acquisition custom computing units or high-speed signal output custom computing units need to be installed in a system, if pure GPIO protocol signal lines are adopted, all custom computing units communicate with the conventional computing unit through parallel computing units, and the parallel computing units and the conventional computing units have only one high-speed data transmission channel, so that the bandwidth bottleneck problem is caused. If the PCIe/PCI/USB protocol signal line of the IPU bus is adopted for transmission, a new data transmission channel can be added for the custom-made unit and the traditional computing unit, and the custom-made computing unit can still use the GPIO protocol signal line to communicate with the traditional computing unit or carry out real-time data exchange with other custom-made computing units through the GPIO protocol signal line, so that the high-bandwidth channel of the custom-made computing unit and the traditional computing unit is further ensured.
Aiming at the application scene, the specific technical scheme is as follows:
the IPU bus is formed from a signal line comprising GPIO, PCIe, USB protocols,
The IPU bus is connected to the parallel computing unit and the custom computing unit respectively,
The parallel computing unit is connected to a conventional computing unit,
The communication module is directly connected with the interface timing module,
Wherein:
The communication module is connected with the traditional computing unit and communicates with the PCI/PCIe protocol main controller of the traditional computing unit through a PCI/PCIe protocol signal line,
The parallel computing module is used to process parallel computing tasks,
The interface timing module is connected with the custom computing unit and used for controlling an external interface of the custom computing unit.
In some application sites, clients have passed through the traditional solutions based on PCI/PCIe/USB, when they need to migrate to the present comprehensive computing system, if they do not need to use parallel computing units, they only need to redesign PCBs according to the structural dimensions of custom computing units, if they need to use parallel computing units, they only need to add the part of interface circuits, thus greatly reducing the time required for them to migrate from the existing solutions to the new comprehensive computing system and reducing the design risk.
In the above-mentioned several scenarios, the following is preferred,
The communication module is used for the communication between the traditional computing unit and the co-computing unit and consists of one PCI/PCIe bus sub-module, one PCI/PCIe bus state machine sub-module, one FIFO sub-module, one local bus state machine sub-module, one local bus sub-module, one logic control sub-module and one configuration parameter sub-module,
The PCI/PCIe bus sub-module, PCI/PCIe bus state machine sub-module, FIFO sub-module, local bus state sub-module and local bus state machine sub-module are connected in sequence, the configuration parameter sub-module is connected with the logic control sub-module, the logic control sub-module is connected with the FIFO sub-module,
The PCI/PCIe bus sub-module is connected with the PCIe protocol main controller of the traditional computing unit, the local bus sub-module is connected with the interface time sequence module, or the parallel computing module, or the handshake module,
Wherein:
the PCI/PCIe bus submodule completes information transmission of interfaces such as data, address, control and the like of PCI/PCIe,
The PCI/PCIe bus state machine submodule completes automatic switching of PCI/PCIe working states,
The FIFO submodule stores management data in a first-in first-out mode,
The local bus state machine submodule is used for controlling the automatic switching of various working states of the local bus,
The local bus submodule is used for realizing signal transmission of data, address, control and the like of a local bus.
The logic control sub-module is used for controlling the interface time sequence module to transmit to the traditional computing unit through the local bus state machine sub-module, the FIFO sub-module and the PCI/PCIe bus state machine sub-module, controlling the data of the traditional computing unit to sequentially transmit to the interface time sequence module through the PCI/PCIe bus state machine sub-module, the FIFO sub-module and the local bus state machine sub-module,
The configuration parameter sub-module initializes the logic control sub-module according to the configured related parameters.
The interface time sequence module is mainly used for controlling the custom-made computing unit by the co-computing unit through GPIO signals and communicating with the custom-made computing unit, and consists of a read-write cache sub-module, a time sequence logic sub-module and a read-write control sub-module,
The read-write control sub-module is connected with the read-write buffer sub-module, the read-write buffer sub-module is connected with the sequential logic sub-module,
The read-write control sub-module is connected with a local communication bus sub-module of the communication module, or is connected with a task management sub-module of the parallel computing module, or is connected with a monitoring sub-module of the handshake module, the time sequence logic sub-module is connected with a control module of the custom computing unit,
Wherein:
The read-write control submodule is used for controlling the data of the custom computation unit to be sequentially transmitted to the communication module or the parallel computation module through the time sequence logic submodule and the read-write buffer submodule, controlling the communication module data or the parallel computation data to be sequentially transmitted to the custom computation unit through the read-write buffer submodule and the logic time sequence submodule,
The read-write buffer submodule is used for matching different communication speeds between the sequential logic submodule and the read-write control submodule,
The sequential logic sub-module is used for realizing a clock and data interface of the sequential logic bus,
The sequential logic submodule comprises an SPI sequential logic submodule or an I2C sequential logic submodule or a parallel sequential logic submodule or a UART sequential logic submodule.
The parallel computing module is used for parallel processing or computing, acquiring computing tasks through the communication module or the interface time sequence module, outputting computing results to the communication module or the interface time sequence module,
Comprises a task management sub-module, more than one task calculation sub-module and a result collection sub-module, wherein each task calculation sub-module is independently connected with the task management sub-module and the result collection sub-module,
The task management sub-module is connected with the read-write control sub-module of the interface time sequence module, is connected with the local bus communication sub-module of the communication module,
Wherein:
the task management submodule is used for dividing the task transmitted by the communication module into a plurality of mutually independent calculation submodules and distributing the mutually independent calculation submodules to different task calculation submodules,
The task calculation sub-module is used for calculating the calculation sub-tasks distributed by the task management sub-module,
The result collection submodule is used for collecting the calculation result of the task calculation submodule and returning the result to the communication module or the interface time sequence module.
The handshake module is used for collaborative handshake of the custom computing units, different custom computing units can realize mutual synchronous work by using the handshake module, can also realize mutual collaborative work by using the handshake module to transmit control signals, and consists of a monitoring sub-module, a clock source sub-module, a triggering bus sub-module and a custom bus sub-module,
The clock source sub-module, the triggering bus sub-module and the custom bus sub-module are all connected with the monitoring sub-module,
The monitoring sub-module is connected with the local bus communication sub-module of the communication module, is connected with the read-write control sub-module of the interface time sequence module,
Wherein:
The monitoring sub-module is used for managing the distribution of signals and monitoring the working state of handshaking,
The clock sub-module provides a clock reference,
The trigger bus submodule is used for transmitting a trigger signal,
The custom bus submodule is used for realizing data transmission among different custom computing units.
In the above application scenarios 1,3,4,5,
The custom computing unit consists of a signal conditioning module, a sampling module and a control module,
The signal conditioning module is connected with the sampling module, the sampling module is connected with the control module,
The control module is connected with the sequential logic sub-module of the interface sequential module,
Wherein the method comprises the steps of
The signal conditioning module is used for conditioning the signal,
The sampling module is used for sampling each path of analog channel, converting the analog channel into digital signals,
The control module is used for controlling the starting operation and the stopping operation of the sampling module and collecting or providing sampling data. In the above application scenarios 1,3,4,5,
The custom computing unit consists of a signal holding module, a digital-to-analog conversion module and a control module,
The control module is connected with the analog-digital conversion module, the analog-digital conversion module is connected with the signal holding module,
The control module is connected with the sequential logic sub-module of the interface sequential module,
Wherein:
wherein the signal holding module is used for holding analog output of each channel,
The digital-to-analog conversion module is used for converting the digital signal into an analog signal,
The control module controls span switching, update rate, and data communication with the legacy computing unit/co-computing unit.
In the above application scenarios 1,2,4,5,
The custom computing unit consists of a level conversion module and a control module,
The control module is connected with the level conversion module,
The control module is connected with the sequential logic sub-module of the interface sequential module,
Wherein:
wherein the level conversion module is used for converting an external input signal into an internal working signal and converting the internal working signal into an external output signal,
The control module is used for controlling the level switching and inputting and outputting time sequences.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (8)
1. An integrated computing system, characterized in that,
The integrated computing system includes a conventional computing unit, one or more co-computing units, one or more custom IPU bus slots, one or more custom computing units,
The conventional computing units are directly connected to one or more co-computing units,
The traditional computing unit, the assistant computing unit and the custom computing unit are all connected with the IPU bus slot, the traditional computing unit is connected with one or more custom IPU bus slots, each assistant computing unit is connected with one or more custom IPU bus slots, each custom computing unit is connected with one custom IPU bus slot, the custom IPU bus slot comprises one or more protocol signal lines and GPIO signal lines,
The traditional computing unit and the co-computing unit directly communicate through PCI/PCIe protocol signal lines of the traditional computing unit,
The conventional computing unit communicates with the custom computing unit via a protocol signal line that is self-contained in the conventional computing unit in the custom IPU bus slot,
The co-calculation unit and the custom calculation unit are communicated through GPIO signal lines in the custom IPU bus slot, the custom calculation unit consists of a signal conditioning module, a sampling module and a control module,
The signal conditioning module is connected with the sampling module, the sampling module is connected with the control module,
The control module is connected with the sequential logic sub-module of the interface sequential module,
Wherein the method comprises the steps of
The signal conditioning module is used for conditioning the signal,
The sampling module is used for sampling each path of analog channel, converting the analog channel into digital signals,
The control module is used for controlling the sampling module to start and stop working and collecting or providing sampling data;
Or alternatively
The custom computing unit consists of a signal holding module, a digital-to-analog conversion module and a control module,
The control module is connected with the analog-digital conversion module, the analog-digital conversion module is connected with the signal holding module,
The control module is connected with the sequential logic sub-module of the interface sequential module,
Wherein:
wherein the signal holding module is used for holding analog output of each channel,
The digital-to-analog conversion module is used for converting the digital signal into an analog signal,
The control module controls range switching, updating rate and data communication with the traditional computing unit/co-computing unit;
Or alternatively
The custom computing unit consists of a level conversion module and a control module,
The control module is connected with the level conversion module,
The control module is connected with the sequential logic sub-module of the interface sequential module,
Wherein:
wherein the level conversion module is used for converting an external input signal into an internal working signal and converting the internal working signal into an external output signal,
The control module is used for controlling the level switching and inputting and outputting time sequences.
2. An integrated computing system as recited in claim 1, wherein,
The conventional computing unit communicates with the custom computing unit via PCI/PCIe or USB protocol signal lines that the conventional computing unit has in the custom IPU bus slot.
3. An integrated computing system as recited in claim 1, wherein,
The conventional computing unit adopts an X86 platform or an ARM platform,
The co-computing unit adopts an FPGA platform or a CPLD platform.
4. An integrated computing system as recited in claim 1, wherein,
The self-defined IPU bus slot is a flat feeler type golden finger or a pinhole type EuroCard connector.
5. An integrated computing system as recited in claim 1, wherein,
The co-computing unit consists of a communication module, a parallel computing module and an interface time sequence module,
The parallel computing module is respectively connected with the communication module and the interface time sequence module,
Wherein:
the communication module is connected with the traditional computing unit and communicates with the protocol main controller of the traditional computing unit through the protocol signal wire of the traditional computing unit,
The parallel computing module is used to process parallel computing tasks,
The interface timing module is connected with the custom computing unit and used for controlling an external interface of the custom computing unit.
6. The integrated computing system of claim 5,
The communication module is used for the communication between the traditional computing unit and the co-computing unit and consists of one PCI/PCIe bus sub-module, one PCI/PCIe bus state machine sub-module, one FIFO sub-module, one local bus state machine sub-module, one local bus sub-module, one logic control sub-module and one configuration parameter sub-module,
The PCI/PCIe bus sub-module, PCI/PCIe bus state machine sub-module, FIFO sub-module, local bus state sub-module and local bus state machine sub-module are connected in sequence, the configuration parameter sub-module is connected with the logic control sub-module, the logic control sub-module is connected with the FIFO sub-module,
The PCI/PCIe bus sub-module is connected with the PCIe protocol main controller of the traditional computing unit, the local bus sub-module is connected with the interface time sequence module, or the parallel computing module, or the handshake module,
Wherein:
The PCI/PCIe bus submodule completes information transmission of interfaces such as data, address, control and the like of PCI/PCIe, the PCI/PCIe bus state machine submodule completes automatic switching of PCI/PCIe working states,
The FIFO submodule stores management data in a first-in first-out mode,
The local bus state machine submodule is used for controlling the automatic switching of various working states of the local bus,
The local bus submodule is used for realizing signal transmission of data, address, control and the like of a local bus,
The logic control sub-module is used for controlling the interface time sequence module to transmit to the traditional computing unit through the local bus state machine sub-module, the FIFO sub-module and the PCI/PCIe bus state machine sub-module, controlling the data of the traditional computing unit to sequentially transmit to the interface time sequence module through the PCI/PCIe bus state machine sub-module, the FIFO sub-module and the local bus state machine sub-module,
The configuration parameter sub-module initializes the logic control sub-module according to the configured related parameters.
7. The integrated computing system of claim 5,
The interface time sequence module is mainly used for controlling the custom-made computing unit by the co-computing unit through GPIO signals and communicating with the custom-made computing unit, and consists of a read-write cache sub-module, a time sequence logic sub-module and a read-write control sub-module,
The read-write control sub-module is connected with the read-write buffer sub-module, the read-write buffer sub-module is connected with the sequential logic sub-module,
The read-write control sub-module is connected with a local communication bus sub-module of the communication module, or is connected with a task management sub-module of the parallel computing module, or is connected with a monitoring sub-module of the handshake module, the time sequence logic sub-module is connected with a control module of the custom computing unit,
Wherein:
The read-write control submodule is used for controlling the data of the custom computation unit to be sequentially transmitted to the communication module or the parallel computation module through the time sequence logic submodule and the read-write buffer submodule, controlling the communication module data or the parallel computation data to be sequentially transmitted to the custom computation unit through the read-write buffer submodule and the logic time sequence submodule, the read-write buffer submodule is used for matching different communication speeds between the time sequence logic submodule and the read-write control submodule,
The sequential logic sub-module is used for realizing a clock and data interface of the sequential logic bus,
The sequential logic submodule comprises an SPI sequential logic submodule or an I2C sequential logic submodule or a parallel sequential logic submodule or a UART sequential logic submodule.
8. The integrated computing system of claim 5,
The parallel computing module is used for parallel processing or computing, acquiring computing tasks through the communication module or the interface time sequence module, outputting computing results to the communication module or the interface time sequence module,
Comprises a task management sub-module, more than one task calculation sub-module and a result collection sub-module, wherein each task calculation sub-module is independently connected with the task management sub-module and the result collection sub-module,
The task management sub-module is connected with the read-write control sub-module of the interface time sequence module, is connected with the local bus communication sub-module of the communication module,
Wherein:
the task management submodule is used for dividing the task transmitted by the communication module into a plurality of mutually independent calculation submodules and distributing the mutually independent calculation submodules to different task calculation submodules,
The task calculation sub-module is used for calculating the calculation sub-tasks distributed by the task management sub-module,
The result collection submodule is used for collecting the calculation result of the task calculation submodule and returning the result to the communication module or the interface time sequence module.
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| CN113721729B (en) | 2024-05-14 |
| CN113760814A (en) | 2021-12-07 |
| CN108664436B (en) | 2021-10-15 |
| CN108664436A (en) | 2018-10-16 |
| CN113760817A (en) | 2021-12-07 |
| CN113760817B (en) | 2024-05-24 |
| CN113721729A (en) | 2021-11-30 |
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| CN113721725A (en) | 2021-11-30 |
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