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CN113760174A - Read-write conversion circuit and memory - Google Patents

Read-write conversion circuit and memory Download PDF

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Publication number
CN113760174A
CN113760174A CN202010505672.3A CN202010505672A CN113760174A CN 113760174 A CN113760174 A CN 113760174A CN 202010505672 A CN202010505672 A CN 202010505672A CN 113760174 A CN113760174 A CN 113760174A
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read
write
local
data line
global
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CN113760174B (en
Inventor
尚为兵
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Changxin Memory Technologies Shanghai Inc
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Changxin Memory Technologies Shanghai Inc
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Priority to CN202510273956.7A priority Critical patent/CN120179172A/en
Application filed by Changxin Memory Technologies Shanghai Inc filed Critical Changxin Memory Technologies Shanghai Inc
Priority to CN202010505672.3A priority patent/CN113760174B/en
Priority to PCT/CN2021/074702 priority patent/WO2021244055A1/en
Priority to KR1020227022256A priority patent/KR102865649B1/en
Priority to JP2022538927A priority patent/JP7352741B2/en
Priority to EP21818317.6A priority patent/EP4002081A4/en
Priority to US17/445,604 priority patent/US11783877B2/en
Publication of CN113760174A publication Critical patent/CN113760174A/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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Abstract

本发明实施例提供一种读写转换电路以及存储器，读写转换电路包括：读写转换模块，响应于读写控制信号以进行读写操作，以使所述本地数据线以及所述本地互补数据线与所述全局数据线之间进行数据传输，且在所述读写操作期间，所述本地数据线与所述本地互补数据线的数据信号相位相反；控制模块，响应于读写速度配置信号以输出可变的所述读写控制信号，以控制所述读写转换模块的读写操作的速度可变。本发明实施例中的读写转换电路的读写操作的速度可以变化，有利于改善存储器的性能。

Figure 202010505672

Embodiments of the present invention provide a read-write conversion circuit and a memory. The read-write conversion circuit includes: a read-write conversion module that performs read-write operations in response to a read-write control signal, so that the local data line and the local complementary data Data transmission is performed between the line and the global data line, and during the read and write operations, the data signals of the local data line and the local complementary data line are in opposite phases; the control module, in response to the read and write speed configuration signal The variable read-write control signal is output to control the speed of read-write operation of the read-write conversion module to be variable. The speed of the read-write operation of the read-write conversion circuit in the embodiment of the present invention can be varied, which is beneficial to improve the performance of the memory.

Figure 202010505672

Description

Read-write conversion circuit and memory
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a read-write conversion circuit and a memory.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell generally includes a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor, and a voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.
The DRAM may be classified into a Double Data Rate (DDR) DRAM, a gddr (graphics Double Data Rate) DRAM, and a Low Power Double Data Rate (LPDDR) DRAM. With the increasing application fields of DRAM, such as the increasing application of DRAM to mobile fields, the demands of users on DRAM power consumption indexes are higher and higher.
However, the performance of current DRAMs is still to be improved.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a read/write conversion circuit and a memory, so that the read/write operation speed of the read/write conversion circuit can be changed to improve the performance of the memory.
To solve the above problem, an embodiment of the present invention provides a read/write conversion circuit, including: the read-write conversion module responds to the read-write control signal to perform read-write operation; and the control module responds to the read-write speed configuration signal to output the variable read-write control signal so as to control the variable speed of the read-write operation of the read-write conversion module.
In addition, still include: and the speed configuration module is connected with the control module and used for outputting the read-write speed configuration signal to the control module.
In addition, the read-write control signal comprises a read control signal and a write control signal, and the read-write conversion module responds to the read control signal to perform read operation and responds to the write control signal to perform write operation; the speed configuration module comprises: a reading speed configuration unit, configured to output a reading speed configuration signal in the reading and writing speed configuration signals to the control module, so that the control module outputs the variable reading control signal in response to the reading speed configuration signal to control the speed of the reading operation to be variable; and the writing speed configuration unit is used for outputting a writing speed configuration signal in the reading and writing speed configuration signals to the control module so that the control module outputs a variable writing control signal in response to the reading speed configuration signal to control the variable speed of the writing operation.
In addition, still include: the local data line, the local complementary data line and the global data line; during the read-write operation, data transmission is performed between the local data line and the local complementary data line and the global data line, and the phases of data signals of the local data line and the local complementary data line are opposite.
In addition, the read-write conversion module includes: the local read-write unit responds to a local read-write control signal in the read-write control signal to perform local read-write operation; the control module includes: and the local control unit responds to a local read-write speed configuration signal in the read-write speed configuration signal to output a variable local read-write control signal and control the speed of local read-write operation of the local read-write unit to be variable.
In addition, the read-write conversion circuit further includes: and the local speed configuration module is connected with the local control unit and used for outputting the local read-write speed configuration signal to the local control unit.
In addition, the read-write conversion circuit further includes: a sense amplifier connected with the local read-write unit via the local data line and the local complementary data line for sensing a bit line voltage.
In addition, the same local read-write unit is connected with a plurality of the sensitive amplifiers through the local data line and the local complementary data line.
In addition, the write data path includes: from the local read-write unit to the sense amplifier via the local data line and the local complementary data line and then to the bit line via the sense amplifier; the read data path includes: and the bit line passes through the sense amplifier to the local data line and the local complementary data line and then passes through the local data line and the local complementary data line to the local read-write unit.
In addition, the read-write conversion module includes: the global read-write unit responds to a global read-write control signal in the read-write control signals to perform global read-write operation; the control module includes: and the global control unit responds to a global read-write speed configuration signal in the read-write speed configuration signals to output a variable global read-write control signal so as to control the global read-write operation speed of the global read-write unit to be variable.
In addition, the read-write conversion circuit further includes: and the global speed configuration module is connected with the global control unit and used for outputting the global read-write speed configuration signal to the global control unit.
In addition, the local read-write unit includes: and the local amplifier is connected between the local data line and the local complementary data line and is used for amplifying the data of the local data line and the data of the local complementary data line.
In addition, the local amplifier includes: a first inverter, an input terminal of which is electrically connected with the local data line, and an output terminal of which is electrically connected with the local complementary data line; a second inverter having an input electrically connected to the output of the first inverter and the local complementary data line, and an output electrically connected to the input of the first inverter and the local data line.
In addition, the first inverter includes: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected and used as the input end of the first phase inverter, the source electrode of the first PMOS tube is connected with a working power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and used as the output end of the first phase inverter; the second inverter includes: the zero PMOS tube grid electrode is connected with the zero NMOS tube grid electrode and serves as the input end of the second phase inverter, the zero PMOS tube source electrode is connected with a working power supply, and the zero PMOS tube drain electrode is connected with the zero NMOS tube drain electrode and serves as the output end of the second phase inverter.
In addition, the local read-write unit comprises a local read conversion circuit, which is used for responding to a local read control signal in the local read-write control signal and transmitting the data of the local data line and the local complementary data line to the global data line; the local read converting circuit includes: a third NMOS transistor and a fourth NMOS transistor; the drain electrode of the third NMOS transistor is connected with the global data line, the grid electrode of the third NMOS transistor is connected with the local complementary data line, and the source electrode of the third NMOS transistor is connected with the drain electrode of the fourth NMOS transistor; and the grid electrode of the fourth NMOS tube receives a local reading signal in the local reading control signal, and the source electrode of the fourth NMOS tube is grounded.
In addition, the read-write conversion circuit further includes: global complementary data lines, and during the read operation, data signals of the global complementary data lines are in opposite phase to the global data lines; the local read converting circuit further comprises: an eighth NMOS transistor and a ninth NMOS transistor; the drain electrode of the eighth NMOS transistor is connected with the global complementary data line, the grid electrode of the eighth NMOS transistor is connected with the local data line, and the source electrode of the eighth NMOS transistor is connected with the drain electrode of the ninth NMOS transistor; and the grid electrode of the ninth NMOS tube receives the local reading signal, and the source electrode of the ninth NMOS tube is grounded.
In addition, the local read-write unit includes: the local write conversion circuit is used for responding to a local write control signal in the local read-write control signals and transmitting the data of the global data line to the local data line and the local complementary data line; the local write translation circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; the drain electrode of the fifth NMOS transistor is connected with the local complementary data line, the grid electrode of the fifth NMOS transistor is connected with the source electrode of the seventh NMOS transistor, and the source electrode of the fifth NMOS transistor is connected with the drain electrode of the sixth NMOS transistor; the grid electrode of the sixth NMOS tube receives a local write signal in the local write control signal, and the source electrode of the sixth NMOS tube is grounded; and the drain electrode of the seventh NMOS transistor is connected with the local data line, and the grid electrode of the seventh NMOS transistor receives the local write signal.
In addition, the read-write conversion circuit further includes: global complementary data lines, and during the read and write operations, data signals of the global complementary data lines and the global data lines are in opposite phases; the local write translation circuit further includes: a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; the drain electrode of the tenth NMOS transistor is connected with the local data line, the grid electrode of the tenth NMOS transistor is connected with the source electrode of the twelfth NMOS transistor and is connected with the global complementary data line, and the source electrode of the tenth NMOS transistor is connected with the drain electrode of the eleventh NMOS transistor; the grid electrode of the eleventh NMOS tube receives the local write signal, and the source electrode of the eleventh NMOS tube is grounded; and the drain electrode of the twelfth NMOS tube is connected with the local complementary data line, and the grid electrode of the twelfth NMOS tube receives the local write signal.
In addition, the local read-write unit further comprises: a precharge circuit connected between the local data line and the local complementary data line for precharging the local data line and the local complementary data line in response to a precharge control signal.
In addition, the precharge circuit includes: the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube receive a pre-charging control signal; the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are connected with a working power supply, and the drain electrode of the third PMOS tube is electrically connected with the local data line; the drain electrode of the fourth PMOS tube is electrically connected with the local complementary data line; the fifth PMOS transistor electrically connects the local data line and the local complementary data line in response to the precharge control signal.
Correspondingly, the embodiment of the invention also provides a memory, which comprises the read-write conversion circuit.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
the embodiment of the invention provides a read-write conversion circuit with excellent structural performance, which comprises a read-write conversion module for responding to a read-write control signal to perform read-write operation, and a control module for responding to a read-write speed configuration signal to output a variable read-write control signal so as to control the variable speed of the read-write operation of the read-write conversion module. Because the read-write control signal output by the control module is variable, the speed of the read-write conversion module for receiving the variable read-write control to carry out the read-write operation is also variable, so that the speed of the read-write operation of the read-write conversion circuit can be configured. Compared with the fixed speed of the read-write operation of the read-write conversion circuit, the read-write conversion circuit provided by the embodiment of the invention can adjust the speed of the read-write operation according to actual requirements, so that the read-write conversion circuit can be widely applied, such as being applied to not only a low-speed read-write operation scene but also a high-speed read-write operation scene; in addition, by adopting the read-write conversion circuit provided by the embodiment of the invention, when high-speed read-write operation is not needed, the low-speed read-write operation can be adjusted, so that the problem of high power consumption caused by high-speed read-write operation is avoided. Therefore, the performance of the read-write conversion circuit provided by the embodiment of the invention is improved.
In addition, the read-write conversion module comprises a local read-write unit, and the control module comprises a local control unit, responds to a local read-write speed configuration signal in the read-write speed configuration signal to output a variable local read-write control signal, and controls the speed of the local read-write operation of the local read-write unit to be variable. Therefore, the local read-write operation speed of the read-write conversion circuit provided by the embodiment of the invention can be configured.
In addition, the read-write conversion module comprises a global read-write unit, and the control module comprises: and the local control unit responds to the global read-write speed configuration signal in the read-write speed configuration signal to output a variable global read-write control signal so as to control the global read-write operation of the global read-write unit to be variable in speed. Therefore, the overall read-write operation speed of the read-write conversion circuit provided by the embodiment of the invention can be configured.
In addition, the local read-write unit comprises: and the local amplifier is connected between the local data line and the local complementary data line and is used for amplifying the data of the local data line and the data of the local complementary data line. The local amplifier is beneficial to accelerating the distinguishing of the local data line and the local complementary data line, not only is beneficial to improving the speed of local read-write operation, but also is beneficial to reducing the driving requirements of the local data line and the local complementary data line on the sensitive amplifier, thereby reducing the design difficulty of the sensitive amplifier.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a read-write conversion circuit according to an embodiment of the present invention;
fig. 2 is a read/write conversion circuit according to another embodiment of the present invention;
FIG. 3 is a diagram of another read/write conversion circuit according to another embodiment of the present invention;
fig. 4 is a timing diagram of read/write control signals corresponding to a high-speed write operation and a low-speed write operation performed by the read/write conversion circuit according to another embodiment of the present invention;
fig. 5 is a timing diagram of read/write control signals corresponding to a high-speed read operation and a low-speed read operation performed by the read/write conversion circuit according to another embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a local read/write unit in the read/write conversion circuit according to another embodiment of the present invention;
fig. 7 is a schematic circuit diagram of another circuit structure of a local read/write unit in the read/write conversion circuit according to another embodiment of the present invention.
Detailed Description
As is known in the art, the performance of the prior art DRAM still remains to be improved.
The inventor of the present invention found that the speed of the read/write operation (including the read speed and the write speed) is constant for the same DRAM in the prior art. Since the speed of the read-write operation of the DRAM is already fixed, it is difficult to realize the requirement that the DRAM has a high speed of the read-write operation at a certain period; if the DRAM is designed to have a fixed high read/write speed, the high read/write speed will cause a problem of large DRAM power consumption for the situation that the DRAM has a low read/write speed to meet the requirement in a certain period. That is, the speed of the read/write operation of the memory is fixed and the power consumption is large.
In order to solve the above problems, embodiments of the present invention provide a read-write conversion circuit, which includes a read-write conversion module and a control module, where the control module responds to a read-write speed configuration signal to output a variable read-write control signal, so as to control the speed of the read-write operation of the read-write conversion module to be variable. Therefore, the embodiment of the invention can realize the configuration of the speed of the read-write operation, so as to adjust the speed of the read-write operation of the read-write conversion circuit to achieve the expectation, and avoid the unnecessary power consumption generated by the read-write conversion circuit, thereby improving the performance of the read-write conversion circuit.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
Fig. 1 is a read-write conversion circuit according to an embodiment of the present invention.
Referring to fig. 1, in this embodiment, the read-write conversion circuit includes: the read-write conversion module 101 responds to the read-write control signal to perform read-write operation; the control module 102 responds to the read/write speed configuration signal to output a variable read/write control signal to control the variable speed of the read/write operation of the read/write conversion module 101.
The read-write conversion circuit provided in the present embodiment will be described in detail below with reference to the drawings.
In this embodiment, the read/write conversion circuit further includes: the local data line Ldat, the local complementary data line Ldat #, and the global data line Gdat, and during the read/write operation, data transmission is performed between the local data line Ldat and the local complementary data line Ldat # and between the global data line Gdat #, wherein the phase of the data signal of the local data line Ldat is opposite to that of the data signal of the local complementary data line Ldat #.
In this embodiment, the data read by the read-write conversion circuit or the data written by the read-write conversion circuit are paired, each pair of data signals includes two data, and during the read-write operation, one of the two data is a high level signal and the other data is a low level signal. Specifically, during a read operation, the read/write conversion circuit transmits data to the global data line Gdat via the local data line Ldat and the local complementary data line Ldat #; during a write operation, the read/write conversion circuit transfers data to the local data line Ldat and the local complementary data line Ldat # via the global data line Gdat.
The local data line Ldat is also referred to as a local data line (local data line), and the local complementary data line Ldat # is also referred to as a complementary local data line; the global data line Gdat is also called global data line.
In this embodiment, the global data line Gdat of the read/write conversion circuit is in a single-ended transmission mode, that is, a global complementary data line complementary to the data signal phase of the global data line Gdat is not provided in the read/write conversion circuit.
It should be noted that, in other embodiments, the global data line of the read/write conversion circuit may also be in a dual-end transmission manner, that is, the read/write conversion circuit further includes a global complementary data line, and during the read/write operation, the phases of the data signals of the global complementary data line and the global data line are opposite.
Specifically, the read-write conversion circuit is applied to a memory, which includes a column selection module 100, a local data line Ldat is connected to a bit line BL through the column selection module 100, and a local complementary data line Ldat # is connected to a complementary bit line BL # through the column selection module 100. A memory cell performing a read operation or a write operation is selected by the column selection module 100, and accordingly, a signal is transmitted between the bit line BL connected to the selected memory cell and the local data line Ldat, and a signal is transmitted between the complementary bit line BL # connected to the selected memory cell and the local complementary data line Ldat #.
During a read operation, the read-write conversion module 101 transmits data of the local data line Ldat and the local complementary data line Ldat # to the global data line Gdat; during a write operation, the read/write conversion module 101 transmits data of the global data line Gdat to the local data line Ldat and the local complementary data line Ldat #.
The read/write control signals include: the read-write control module comprises a column selection signal, a local read-write control signal and a global read-write control signal, wherein the local read-write control signal is used for controlling the read-write conversion module 101 to perform local read-write operation, and the global read-write control signal is used for controlling the read-write conversion module 101 to perform global read-write operation.
The rate of the read/write control signal affects the speed of the read/write operation of the read/write conversion circuit. For example, the faster the rate of the read/write control signal is, the faster the corresponding read/write operation is; the slower the rate of the read and write control signals, the slower the speed of the corresponding read and write operations.
The read/write control signal is provided by the control module 102, and the read/write control signal output by the control module 102 is variable, specifically, the rate of the read/write control signal is variable. The read-write speed configuration signal is related to the expected speed of the read-write operation, and when the speed of the read-write operation is not the expected speed, the read-write control signal output by the control module 102 changes, that is, the rate of the read-write control signal changes, so that the speed of the read-write operation performed by the read-write conversion module 101 in response to the changed read-write control signal changes, thereby ensuring that the read-write speed of the read-write operation is the expected speed.
For example, when the speed of the read-write operation performed by the read-write conversion module 101 in response to the first read-write control signal is lower than the desired speed, the control module 102 outputs a second read-write control signal in response to the read-write speed configuration signal, so as to increase the read-write operation speed of the read-write conversion module 101 to the desired speed; when the speed of the read-write operation performed by the read-write conversion module 101 in response to the third read-write control signal is higher than the desired speed, the control module 102 outputs a fourth read-write control signal in response to the read-write speed configuration signal, so that the read-write operation speed of the read-write conversion module 101 is reduced to the desired speed.
Because the speed of the read-write operation of the read-write conversion module 101 is variable, the speed of the read-write operation of the read-write conversion module 101 can be adjusted according to the actual performance requirements, for example, the speed of data transmission in the read-write operation is increased or the speed of data transmission in the read-write operation is decreased, so that unnecessary power consumption can be reduced while different read-write performance requirements are met.
In this embodiment, the read-write conversion circuit may further include: and the speed configuration module 103 is connected to the control module 102 and configured to output a read-write speed configuration signal to the control module 102. Thus, the speed configuration module 103 is integrated in the read-write conversion circuit, which is beneficial to reducing the transmission path for transmitting the read-write speed configuration signal to the control module 102, and further improving the response speed of the control module 102, so that the control module 102 can output the adjusted read-write control signal more timely, and the purpose of changing the read-write operation speed of the read-write conversion module 101 can be achieved more quickly.
The read/write control signal includes a read control signal and a write control signal, and the read/write conversion module 101 performs a read operation in response to the read control signal and performs a write operation in response to the write control signal. In this embodiment, the control module 102 responds to the read-write speed configuration signal to output a variable read control signal to control the speed of the read operation of the read-write conversion module 101 to be variable; the control module 102 is further responsive to the read/write speed configuration signal to output a variable write control signal to control the variable speed of the write operation of the read/write conversion module 101.
Correspondingly, the read-write speed configuration signal comprises a read-speed configuration signal and a write-speed configuration signal; the speed configuration module 103 includes: a reading speed configuration unit 113, configured to output a reading speed configuration signal of the reading and writing speed configuration signals to the control module 102, so that the control module 102 outputs a variable reading control signal in response to the reading speed configuration signal to control the speed of the reading operation to be variable; a write speed configuration unit 123, configured to output a write speed configuration signal in the read/write speed configuration signal to the control module 102, so that the control module outputs a variable write control signal in response to the read speed configuration signal to control the speed of the write operation to be variable.
It should be noted that the speed configuration module may further include a local speed configuration module and a global speed configuration module. The local speed configuration module is used for outputting a local read-write speed configuration signal to the control module so as to control the speed of the local read-write operation of the read-write conversion module to be variable; the global speed configuration module is used for outputting a global read-write speed configuration signal to the control module so as to control the variable speed of the global read-write operation of the read-write conversion module.
It should be noted that, in other embodiments, the speed configuration module may also be provided by other circuits besides the read-write conversion circuit.
In the read-write conversion circuit provided by this embodiment, the control module 101 outputs a variable read-write control signal, so that the speed of the read-write operation of the read-write conversion module 101 is variable, and thus the application scenario of the read-write conversion circuit is wider, for example, both high-speed read-write operation and low-speed read-write operation can be performed, and the problem of large power consumption caused by long-time high-speed read-write operation state is avoided.
Another embodiment of the present invention further provides a read-write converting circuit, which is substantially the same as the read-write converting circuit provided in the previous embodiment, except that: in this embodiment, the read-write conversion module and the control module are explained in more detail. The read-write conversion circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings, and the same or corresponding parts as those in the previous embodiment can be referred to for the detailed description of the previous embodiment.
Fig. 2 is a read/write conversion circuit according to another embodiment of the present invention.
Referring to fig. 2, the read-write conversion circuit includes: a local data line Ldat, a local complementary data line Ldat #, a global data line Gdat, and a global complementary data line Gdat #; the read-write conversion module 201 performs a read-write operation in response to the read-write control signal, so that data transmission is performed between the local data line Ldat and the local complementary data line Ldat # and between the global data line Gdat and the global complementary data line Gdat #, and during the read-write operation, phases of data signals of the local data line Ldat and the local complementary data line Ldat # are opposite, and phases of data signals of the global data line Gdat and the global complementary data line Gdat # are opposite.
It should be noted that, in other embodiments, the read-write conversion circuit may not be provided with the global complementary data line.
In this embodiment, the read-write conversion module 201 includes: and the local read-write unit 211 responds to the local read-write control signal in the read-write control signal to perform local read-write operation. The local read-write control signal comprises a local read signal Rd and a local amplification enabling signal.
Accordingly, the control module 202 includes: the local control unit 212 responds to the local read-write speed configuration signal in the read-write speed configuration signal to output a variable local read-write control signal, and controls the speed of the local read-write operation of the local read-write unit 211 to be variable.
Thus, the speed of local read and write operations in the read and write conversion circuit is variable. Specifically, the speed of the local read operation in the local read-write operation is variable, and the speed of the local write operation in the local read-write operation is variable. For example, the local read operation may be reduced from a high speed read to a low speed read, or alternatively, from a low speed read to a high speed read; the local write operation can be reduced from high-speed writing to low-speed writing or increased from low-speed writing to high-speed writing. Because the speed of the local read-write operation is variable, the speed of the local read-write operation can be adjusted according to actual requirements, and therefore the read-write conversion circuit is guaranteed to have the advantage of low power consumption while the requirement of data transmission speed is met.
In this embodiment, the read-write conversion circuit may further include: the local speed configuration module 213 is connected to the local control unit 212, and configured to output a local read/write speed configuration signal to the local control unit 212, so that the local read/write control signal output by the local control unit 212 is adjustable.
It should be noted that, in other embodiments, the local read-write speed configuration signal may also be provided to the local control unit by an external circuit, that is, the read-write conversion circuit does not need the local speed configuration module.
The read-write conversion circuit may further include: the sense amplifier 214, the sense amplifier 214 is connected to the local read/write unit 211 via a local data line Ldat and a local complementary data line Ldat # for sensing the voltages of the bit line BL and the complementary bit line BL #.
The bit line BL is connected to a local data line Ldat via a sense amplifier 214, and the complementary bit line BL # is connected to a local complementary data line Ldat # via a sense amplifier 214.
In this embodiment, the sense amplifier 214 receives the column selection signal CSL. Sense amplifier 214 includes 2 NMOS transistors (not shown), and the gates of the NMOS transistors receive column select signal CSL, one NMOS transistor connects bit line BL with local data line Ldat in response to column select signal CSL, and the other NMOS transistor connects complementary bit line BL # with local complementary data line Ldat # in response to column select signal CSL.
It is understood that in other embodiments, the sense amplifier may include any number of transistors, such as multiple NMOS transistors and/or multiple PMOS transistors. Any device capable of realizing the sensitive amplification function can be used as the sensitive amplifier.
The bit line BL is connected to a memory transistor (not shown), the gate of the memory transistor is connected to the word line WL, one end of the memory transistor is connected to the bit line BL, and the other end thereof is connected to a voltage Vplate via a capacitor (not shown). The complementary bit line BL # is connected to a control transistor (not shown) having one end connected to the complementary bit line BL # and the other end connected to the voltage Vplate.
In addition, the same local read/write unit 211 can be connected to a plurality of sense amplifiers 214 via the local data line Ldat and the local complementary data line Ldat #. For ease of illustration and explanation, only one sense amplifier 214 is shown in FIG. 2.
In this embodiment, the read/write conversion circuit is applied to a memory, and the write data path includes: from the local read/write unit 211, through the local data line Ldat and the local complementary data line Ldat #, to the sense amplifier, and then through the sense amplifier 214 to the bit line BL and the complementary bit line BL #; the read data path includes: from the bit line, through the sense amplifier 214, to the local data line Ldat and the local complementary data line Ldat #, and then to the local read/write unit 211 through the local data line Ldat and the local complementary data line Ldat #.
In this embodiment, the read-write conversion module 201 further includes: and a global read/write unit 221, which responds to the global read/write control signal in the read/write control signal to perform global read/write operation.
The control module 202 includes: the global control unit 222 is configured to respond to the global read/write speed configuration signal in the read/write speed configuration signals to output a variable global read/write control signal to control the global read/write operation of the global read/write unit 221 to be variable in speed. Thus, the speed of the global read-write operation in the read-write conversion circuit is variable. Specifically, the speed of the global read operation in the global read/write operation is variable, and the speed of the global write operation in the global read/write operation is variable.
That is, in this embodiment, not only the speed of the local read/write operation is variable, but also the speed of the global read/write operation is variable.
It should be noted that, in other embodiments, the control module may include only one of the local control unit or the global control unit, and accordingly, only the speed of the local read/write operation is variable or only the speed of the global read/write operation is variable.
Correspondingly, the read-write conversion circuit may further include: and the global speed configuration module 223 is connected to the global control unit 222, and is configured to output a global read-write speed configuration signal to the global control unit 222.
The local speed configuration module 213 and the global speed configuration module 223 may be integrated into the same speed configuration module 203, where the speed configuration module 203 is configured to output a local read/write speed configuration signal to the local control unit 212, and is further configured to output a global read/write speed configuration signal to the global control unit 222.
It is understood that in other embodiments, the global read/write speed configuration signal may also be provided by an external circuit to the global control unit, i.e. the read/write conversion circuit does not need a global speed configuration module.
Fig. 3 is another read-write conversion circuit according to another embodiment. As shown in fig. 3, in another example, the read-write conversion circuit may further include: a read speed configuration unit 243, configured to output a read speed configuration signal in the read/write speed configuration signals to the local control unit 212 and the global control unit 222, so that the local control unit 212 outputs a variable local read control signal in response to the read speed configuration signal to control the speed of the local read operation to be variable, and so that the global control unit 222 outputs a variable global read control signal in response to the read speed configuration signal to control the speed of the global read operation to be variable; a write speed configuration unit 253, configured to output a write speed configuration signal in the read/write speed configuration signals to the local control unit 212 and the global control unit 222, so that the local control unit 212 outputs a variable local write control signal in response to the write speed configuration signal to control the speed of the local write operation to be variable, and so that the global control unit 222 outputs a variable global write control signal in response to the write speed configuration signal to control the speed of the global write operation to be variable. The read speed configuration unit 243 and the write speed configuration unit 253 can be integrated into the same speed configuration module 203, and the speed configuration module 203 can be described with reference to the foregoing embodiments.
For a read-write conversion circuit with global read-write unit 221, the write data path includes: the global data line Gdat and the global complementary data line Gdat # are transmitted to the local read/write unit 211 via the global read/write unit 221, and then the global data line Gdat and the global complementary data line Gdat # are transmitted to the local read/write unit 211; from the local read/write unit 211, through the local data line Ldat and the local complementary data line Ldat #, to the sense amplifier 214, and then through the sense amplifier 214, to the bit line BL and the complementary bit line BL #.
For a read-write conversion circuit with global read-write unit 221, the read data path includes: from bit line BL and complementary bit line BL # through sense amplifier 214 to local data line Ldat and local complementary data line Ldat #, and then through local data line Ldat and local complementary data line Ldat # to local read/write unit 211; then to the global data line Gdat and the global complementary data line Gdat # via the local read/write unit 211; to the global read/write unit 221 via the global data line Gdat and the global complementary data line Gdat #.
In this embodiment, the local read/write unit 211 includes a local read switching circuit 2111, configured to transmit data of the local data line Ldat and the local complementary data line Ldat # to the global data line Gdat and the global complementary data line Gdat # in response to a local read control signal in the local read/write control signal.
The control module 202 outputs a local read control signal, and the control module 202 outputs a variable local read control signal in response to the read/write speed configuration signal to adjust the read speed of the local read/write conversion circuit 2111, so that the speed of the local read operation of the read/write conversion module 201 is variable.
The local read-write unit 211 further comprises: a local write switching circuit 2112, for transmitting data of the global data line Gdat and the global complementary data line Gdat # to the local data line Ldat and the local complementary data line Ldat # in response to a local write control signal among the local read and write control signals.
The control module 202 outputs a local write control signal, and the control module 202 outputs a variable local write control signal in response to the read/write speed configuration signal to adjust the write speed of the local write conversion circuit 2112, so that the speed of the local write operation of the read/write conversion module 201 is variable.
The local read-write unit 211 further comprises: a local amplifier 2113 connected between the local data line Ldat and the local complementary data line Ldat #, for amplifying data of the local data line Ldat and data of the local complementary data line Ldat #.
The control module 202 outputs a variable local read control signal or local write control signal so that the amplification speed of the local amplifier 2113 is variable, thereby also being able to change the speed of the local read operation and the local write operation of the read-write conversion module 201 to some extent.
The local amplifier 2113 constitutes a circuit for amplifying the signal of the local data line Ldat and the signal of the local complementary data line Ldat # and is helpful for accelerating the differentiation between the local data line Ldat and the local complementary data line Ldat #, thereby increasing the transmission speed of the data signal and improving the data read-write speed. In addition, since the data signals of the local data line Ldat and the local complementary data line Ldat # are amplified, so that the requirement of the local data line Ldat and the local complementary data line Ldat # on the driving capability of the sense amplifier in the memory is reduced, even if the area of the sense amplifier is gradually reduced, the sense amplifier still has sufficient driving capability for the local data line Ldat and the local complementary data line Ldat # so as to meet the trend of miniaturization of devices, ensure that the read-write conversion circuit has good electrical performance, and further improve the storage performance of the memory comprising the read-write conversion circuit.
Global read/write unit 221 includes sense amplifier 2211, precharge unit 2212, and write driver unit 2213. The sense amplifier 2211 amplifies the data signals of the global data line Gdat and the global complementary data line Gdat #, and the precharge unit 2212 precharges the global data line Gdat and the global complementary data line Gdat #.
The control block 202 outputs a variable global read control signal to adjust the speed of the global read operation of the global read/write unit 221 or the speed of the global write operation, such as adjusting the amplification speed of the sense amplifier 2211, the precharge speed of the precharge unit 2212, and the driving speed of the write driving unit 2213, so as to achieve the purpose of changing the speed of the global read/write operation of the read/write conversion block 201.
In this embodiment, the read-write conversion circuit may further include: and a precharge circuit (not shown) connected between the local data line Ldat and the local complementary data line Ldat # for precharging the local data line Ldat and the local complementary data line Ldat # in response to a precharge control signal.
Fig. 4 is a timing diagram of read/write control signals corresponding to a high-speed write operation and a low-speed write operation performed by the read/write conversion circuit according to this embodiment; fig. 5 is a timing diagram of read/write control signals corresponding to a high-speed read operation and a low-speed read operation performed by the read/write conversion circuit according to this embodiment; also illustrated in fig. 4 and 5 are bitline/complement bitline signal (BL/BL #), global data line/global complement data line signal (Gdat/Gdat #), local data line/local complement data line signal (Ldat/Ldat #). It will be appreciated that high speed as well as low speed are relative terms.
Referring to fig. 4, when performing a write operation, the read/write control signal includes: a global write control signal, a column select signal CSL, a local write signal Wr, and a local amplification enable. It is to be understood that, when the low-speed writing operation is performed, the level of the local amplification enable may be 0, and thus the low-speed writing operation corresponds to a timing chart in which the local amplification enable is not illustrated.
As can be seen from fig. 4, when the write operation is changed from the high-speed write operation to the low-speed write operation, the rate of the read/write control signal is slowed, the data transfer rates of the global data line Gdat and the global complementary data line Gdat # are slowed, and the data transfer rates of the local data line Ldat and the local complementary data line Ldat # are slowed. When the low-speed writing operation is changed into the high-speed writing operation, the rate of the read-write control signal is increased, the data transmission rates of the global data line Gdat and the global complementary data line Gdat # are increased, and the data transmission rates of the local data line Ldat and the local complementary data line Ldat # are increased.
In addition, fig. 4 only shows a timing chart of each read/write control signal in a single clock cycle, and from the whole clock cycle, the low-speed write operation is changed into the high-speed write operation, the rate of the write control signal in the corresponding read/write control signal is increased, the high-speed write operation is changed into the low-speed write operation, and the rate of the write control signal in the corresponding read/write control signal is decreased.
Referring to fig. 5, when a read operation is entered, the read/write control signals include: a column selection signal CSL, a local read signal Rd, a global amplification enable, a global precharge signal, and a local amplification enable. It is to be understood that the level of the local amplification enable may be 0 when performing a low-speed read operation, and thus the low-speed read operation corresponds to a timing diagram in which the local amplification enable is not illustrated. As can be easily seen from fig. 5, when the high-speed read operation is changed to the low-speed read operation, the rate of the read/write control signal is slowed, the data transmission rates of the local data line Ldat and the local complementary data line Ldat # are slowed, and the data transmission rates of the global data line Gdat and the global complementary data line Gdat # are slowed; when the low-speed reading operation is changed into the high-speed reading operation, the rate of the read-write control signal is increased, the data transmission rates of the local data line Ldat and the local complementary data line Ldat # are increased, and the data transmission rates of the global data line Gdat and the global complementary data line Gdat # are increased.
Fig. 5 shows a timing chart of each read/write control signal in a single clock cycle, and from the whole clock cycle, the low-speed read operation is changed into the high-speed read operation, the rate of the read control signal in the corresponding read/write control signal is increased, the high-speed read operation is changed into the low-speed write operation, and the rate of the read control signal in the corresponding read/write control signal is decreased.
It should be noted that fig. 4 and fig. 5 only show some common read/write control signals that affect the read/write operation speed, and in an actual circuit, depending on the circuit design, there may be other read/write control signals that affect the read/write operation speed.
The circuit structure of the local read-write unit in the read-write conversion single path provided in this embodiment will be specifically described below with reference to the accompanying drawings.
Fig. 6 is a schematic circuit structure diagram of a local read/write unit in the read/write conversion circuit provided in this embodiment; fig. 7 is a schematic diagram of another circuit structure of a local read/write unit in the read/write conversion circuit provided in this embodiment.
Referring to fig. 6, the global data line Gdat is a single transmission type, i.e., the read/write conversion circuit does not include a global complementary data line. The local read/write unit 211 includes a local read conversion circuit 2111 for transmitting data of the local data line Ldat and the local complementary data line Ldat # to the global data line Gdat in response to a local read control signal among the local read/write control signals.
In this embodiment, the local read converting circuit 2111 includes: a third NMOS transistor MN3 and a fourth NMOS transistor MN 4; the drain of the third NMOS transistor MN3 is connected to the global data line Gdat, the gate of the third NMOS transistor MN3 is connected to the local complementary data line Ldat #, and the source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN 4; the gate of the fourth NMOS transistor MN4 receives the local read signal Rd in the local read control signal, and the source is grounded.
It is understood that the local read switch circuit 2111 may be another suitable variant circuit, for example, the gate of the fourth NMOS transistor is connected to the local complementary data line, and the gate of the third NMOS transistor receives the local read signal.
In another example, as shown in fig. 7, the global data line Gdat may also be in a dual transfer mode, that is, the read/write conversion circuit includes a global data line Gdat and a global complementary data line Gdat #, and during a read operation, the global complementary data line Gdat and the global data line Gdat # have opposite phases, and accordingly, the local read conversion circuit 2111 includes, in addition to the third NMOS transistor MN3 and the fourth NMOS transistor MN 4: an eighth NMOS transistor MN8 and a ninth NMOS transistor MN 9; the drain of the eighth NMOS transistor MN8 is connected to the global complementary data line Gdat #, the gate of the eighth NMOS transistor MN8 is connected to the local data line Ldat, and the source of the eighth NMOS transistor MN8 is connected to the drain of the ninth NMOS transistor MN 9; the gate of the ninth NMOS transistor MN9 receives the local read signal Rd, and the source is grounded.
The local read-write unit 211 includes: a local write switching circuit 2112 for transmitting data of the global data line Gdat to the local data line Ldat and the local complementary data line Ldat # in response to a local write control signal among the local read and write control signals.
In this embodiment, the local write conversion circuit 2112 includes: a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN 7; the drain electrode of the fifth NMOS transistor MN5 is connected with the local complementary data line Ldat #, the gate electrode of the fifth NMOS transistor MN5 is connected with the source electrode of the seventh NMOS transistor MN7, and the source electrode of the fifth NMOS transistor MN5 is connected with the drain electrode of the sixth NMOS transistor MN 6; the grid electrode of the sixth NMOS tube MN6 receives the local write signal Wr in the local write control signal, and the source electrode is grounded; the drain of the seventh NMOS transistor MN7 is connected to the local data line Ldat, and the gate receives the local write signal Wr.
In another example, as shown in fig. 7, the read-write conversion circuit 211 further includes: global complementary data line Gdat #, and during a read operation, the data signals of global complementary data line Gdat # and global data line Gdat are in opposite phase; the local write switch circuit 2112 includes, in addition to the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7, the following: a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN 12; the drain of the tenth NMOS transistor MN10 is connected to the local data line Ldat, the gate of the tenth NMOS transistor MN10 is connected to the source of the twelfth NMOS transistor MN12 and to the global complementary data line Gdat #, and the source of the tenth NMOS transistor MN10 is connected to the drain of the eleventh NMOS transistor MN 11; the gate of an eleventh NMOS transistor MN11 receives the local write signal Wr, and the source is grounded; the twelfth NMOS transistor MN12 has a drain connected to the local complementary data line Ldat #, and a gate receiving the local write signal Wr.
The local amplifier includes 2113: a first inverter, an input terminal of which is electrically connected with the local data line, and an output terminal of which is electrically connected with the local complementary data line; a second inverter having an input electrically connected to the output of the first inverter and the local complementary data line, and an output electrically connected to the input of the first inverter and the local data line.
Specifically, the first inverter includes: a first PMOS transistor MP1 and a first NMOS transistor MN1, a gate of the first PMOS transistor MP1 and a gate of the first NMOS transistor MN1 are electrically connected and serve as an input terminal in1 of the first inverter, a source of the first PMOS transistor MP1 is connected with a working power supply VDD, and a drain of the first PMOS transistor MP1 is connected with a drain of the first NMOS transistor MN1 and serves as an output terminal out1 of the first inverter.
The second inverter includes: a zeroth PMOS transistor MP0 and a zeroth NMOS transistor MN0, a gate of the zeroth PMOS transistor MP0 is connected to the gate of the zeroth NMOS transistor MN0 and serves as an input terminal in2 of the second inverter, a source of the zeroth PMOS transistor MP0 is connected to the working power supply VDD, and a drain of the zeroth PMOS transistor MP0 is connected to the drain of the zeroth NMOS transistor MN0 and serves as an output terminal out2 of the second inverter.
The first PMOS transistor MP1, the first NMOS transistor MN1, the zeroth PMOS transistor MP0, and the zeroth NMOS transistor MN0 form a local amplifier 2113.
In addition, the local amplifier 2113 further includes: the enabling NMOS tube mn, the first inverter and the second inverter are further connected with a drain electrode of the enabling NMOS tube mn, the drain electrode of the enabling NMOS tube mn is grounded, and a grid electrode receives a local enabling signal En. Specifically, the source of the first NMOS transistor MN1 and the source of the zeroth NMOS transistor MN0 are connected to the drain of the sixth NMOS transistor MN 6.
Due to the arrangement of the local amplifier 2113, the transmission speed of data from the bit line BL to the local data line Ldat is increased, the transmission speed of data from the complementary bit line BL # to the local complementary data line Ldat # is increased, and the driving requirement of the memory for the sense amplifier is reduced. Specifically, taking the data of the bit line BL as high and the data of the complementary bit line BL # as low, for example, since the first input terminal in1 of the first inverter is connected to the second output terminal out2 of the second inverter, and the first output terminal out1 of the first inverter is connected to the second input terminal in2 of the second inverter, the arrangement of the local amplifier 2113 during the transmission of the bit line BL and the complementary bit line BL # to the local data line Ldat and the local complementary data line Ldat # causes the local complementary data line Ldat # having a lower voltage to be pulled down to "0" more quickly, or causes the local complementary data line Ldat having a higher voltage to be pulled up to "1" more quickly. Therefore, the speed of pulling up the local data line Ldat is increased, the speed of pulling down the local complementary data line Ldat # is also increased, and the driving requirements of the local data line Ldat and the local complementary data line Ldat # for the sense amplifier are reduced.
Meanwhile, since the local data line Ldat and the local complementary data line Ldat # may reach a high level or a low level more quickly, the local data line Ldat and the local complementary data line Ldat # may be transmitted to the global data line Gdat and the global complementary data line Gdat # earlier, so that the speed of data transmission from the local data line Ldat and the local complementary data line Ldat # to the global data line Gdat and the global complementary data line Gdat # is increased when data is read out.
Accordingly, during the write operation, the local amplifier 2113 also amplifies the local data line Ldat and the local complementary data line Ldat #, so as to increase the speed of data transmission from the global data line Gdat and the global complementary data line Gdat # to the local data line Ldat and the local complementary data line Ldat #.
In this embodiment, the precharge circuit includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP 5; the grid electrode of the third PMOS tube MP3, the grid electrode of the fourth PMOS tube MP4 and the grid electrode of the fifth PMOS tube MP5 receive a precharge control signal Eq; the source electrode of the third PMOS transistor MP3 and the source electrode of the fourth PMOS transistor MP4 are connected with a working power supply VDD, and the drain electrode of the third PMOS transistor MP3 is electrically connected with the local data line Ldat; the drain electrode of the fourth PMOS transistor MP4 is electrically connected to the local complementary data line Ldat #; the fifth PMOS transistor MN5 electrically connects the local data line Ldat and the local complementary data line Ldat #, in response to the precharge control signal Eq. The control module 202 outputs a read/write control signal in response to the read/write speed configuration signal to change the data read rate of the local read/write conversion circuit 2111 or the data write rate of the local write/read conversion circuit 2112, and so on, thereby adjusting the speed of the read/write operation of the read/write conversion circuit.
The read-write conversion circuit provided by the embodiment can adjust the speed of local read-write operation and can also adjust the speed of global read-write operation, so that the convenience of the read-write operation speed adjustment of the read-write conversion circuit is further improved.
Correspondingly, an embodiment of the present invention provides a memory, including the read-write conversion circuit.
The memory can be DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, NOR, etc. As can be seen from the foregoing analysis, the memory provided in this embodiment has the advantage of variable data transmission speed, and the requirement for the driving capability of the sense amplifier is low, which is beneficial to meeting the trend of device miniaturization.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A read-write conversion circuit, comprising:
the read-write conversion module responds to the read-write control signal to perform read-write operation;
and the control module responds to the read-write speed configuration signal to output the variable read-write control signal so as to control the variable speed of the read-write operation of the read-write conversion module.
2. The read-write conversion circuit of claim 1, further comprising: and the speed configuration module is connected with the control module and used for outputting the read-write speed configuration signal to the control module.
3. The read-write conversion circuit of claim 2, wherein the read-write control signals include read control signals and write control signals, the read-write conversion module being responsive to the read control signals to perform read operations and to the write control signals to perform write operations;
the speed configuration module comprises: a reading speed configuration unit, configured to output a reading speed configuration signal in the reading and writing speed configuration signals to the control module, so that the control module outputs the variable reading control signal in response to the reading speed configuration signal to control the speed of the reading operation to be variable;
and the writing speed configuration unit is used for outputting a writing speed configuration signal in the reading and writing speed configuration signals to the control module so that the control module outputs a variable writing control signal in response to the reading speed configuration signal to control the variable speed of the writing operation.
4. The read-write conversion circuit of claim 1, further comprising: the local data line, the local complementary data line and the global data line; during the read-write operation, data transmission is performed between the local data line and the local complementary data line and the global data line, and the phases of data signals of the local data line and the local complementary data line are opposite.
5. The read-write conversion circuit of claim 4, wherein the read-write conversion module comprises: the local read-write unit responds to a local read-write control signal in the read-write control signal to perform local read-write operation; the control module includes: and the local control unit responds to a local read-write speed configuration signal in the read-write speed configuration signal to output a variable local read-write control signal and control the speed of local read-write operation of the local read-write unit to be variable.
6. The read-write conversion circuit of claim 5, further comprising: and the local speed configuration module is connected with the local control unit and used for outputting the local read-write speed configuration signal to the local control unit.
7. The read-write conversion circuit of claim 5, further comprising: a sense amplifier connected with the local read-write unit via the local data line and the local complementary data line for sensing a bit line voltage.
8. The read-write conversion circuit of claim 7, wherein the same local read-write unit is connected to multiple sense amplifiers via the local data line and the local complementary data line.
9. The read-write conversion circuit of claim 7, wherein the write data path comprises: from the local read-write unit to the sense amplifier via the local data line and the local complementary data line and then to the bit line via the sense amplifier; the read data path includes: and the bit line passes through the sense amplifier to the local data line and the local complementary data line and then passes through the local data line and the local complementary data line to the local read-write unit.
10. The read-write conversion circuit of claim 4, wherein the read-write conversion module comprises: the global read-write unit responds to a global read-write control signal in the read-write control signals to perform global read-write operation; the control module includes: and the global control unit responds to a global read-write speed configuration signal in the read-write speed configuration signals to output a variable global read-write control signal so as to control the global read-write operation speed of the global read-write unit to be variable.
11. The read-write conversion circuit of claim 10, further comprising: and the global speed configuration module is connected with the global control unit and used for outputting the global read-write speed configuration signal to the global control unit.
12. The read-write conversion circuit of claim 5, wherein the local read-write unit comprises: and the local amplifier is connected between the local data line and the local complementary data line and is used for amplifying the data of the local data line and the data of the local complementary data line.
13. The read-write conversion circuit of claim 12, wherein the local amplifier comprises: a first inverter, an input terminal of which is electrically connected with the local data line, and an output terminal of which is electrically connected with the local complementary data line; a second inverter having an input electrically connected to the output of the first inverter and the local complementary data line, and an output electrically connected to the input of the first inverter and the local data line.
14. The read-write conversion circuit of claim 13, wherein the first inverter comprises: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected and used as the input end of the first phase inverter, the source electrode of the first PMOS tube is connected with a working power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and used as the output end of the first phase inverter; the second inverter includes: the zero PMOS tube grid electrode is connected with the zero NMOS tube grid electrode and serves as the input end of the second phase inverter, the zero PMOS tube source electrode is connected with a working power supply, and the zero PMOS tube drain electrode is connected with the zero NMOS tube drain electrode and serves as the output end of the second phase inverter.
15. The read-write conversion circuit according to claim 5, wherein the local read-write unit includes a local read conversion circuit for transmitting data of the local data line and the local complementary data line to the global data line in response to a local read control signal among the local read-write control signals; the local read converting circuit includes:
a third NMOS transistor and a fourth NMOS transistor; the drain electrode of the third NMOS transistor is connected with the global data line, the grid electrode of the third NMOS transistor is connected with the local complementary data line, and the source electrode of the third NMOS transistor is connected with the drain electrode of the fourth NMOS transistor; and the grid electrode of the fourth NMOS tube receives a local reading signal in the local reading control signal, and the source electrode of the fourth NMOS tube is grounded.
16. The read-write conversion circuit of claim 15, further comprising: global complementary data lines, and during the read operation, data signals of the global complementary data lines are in opposite phase to the global data lines; the local read converting circuit further comprises: an eighth NMOS transistor and a ninth NMOS transistor; the drain electrode of the eighth NMOS transistor is connected with the global complementary data line, the grid electrode of the eighth NMOS transistor is connected with the local data line, and the source electrode of the eighth NMOS transistor is connected with the drain electrode of the ninth NMOS transistor; and the grid electrode of the ninth NMOS tube receives the local reading signal, and the source electrode of the ninth NMOS tube is grounded.
17. The read-write conversion circuit of claim 5, wherein the local read-write unit comprises: the local write conversion circuit is used for responding to a local write control signal in the local read-write control signals and transmitting the data of the global data line to the local data line and the local complementary data line; the local write translation circuit includes:
a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; the drain electrode of the fifth NMOS transistor is connected with the local complementary data line, the grid electrode of the fifth NMOS transistor is connected with the source electrode of the seventh NMOS transistor, and the source electrode of the fifth NMOS transistor is connected with the drain electrode of the sixth NMOS transistor; the grid electrode of the sixth NMOS tube receives a local write signal in the local write control signal, and the source electrode of the sixth NMOS tube is grounded; and the drain electrode of the seventh NMOS transistor is connected with the local data line, and the grid electrode of the seventh NMOS transistor receives the local write signal.
18. The read-write conversion circuit of claim 17, further comprising: global complementary data lines, and during the read and write operations, data signals of the global complementary data lines and the global data lines are in opposite phases; the local write translation circuit further includes: a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; the drain electrode of the tenth NMOS transistor is connected with the local data line, the grid electrode of the tenth NMOS transistor is connected with the source electrode of the twelfth NMOS transistor and is connected with the global complementary data line, and the source electrode of the tenth NMOS transistor is connected with the drain electrode of the eleventh NMOS transistor; the grid electrode of the eleventh NMOS tube receives the local write signal, and the source electrode of the eleventh NMOS tube is grounded; and the drain electrode of the twelfth NMOS tube is connected with the local complementary data line, and the grid electrode of the twelfth NMOS tube receives the local write signal.
19. The read-write conversion circuit of claim 5, wherein the local read-write unit further comprises: a precharge circuit connected between the local data line and the local complementary data line for precharging the local data line and the local complementary data line in response to a precharge control signal.
20. A memory, comprising: read-write conversion circuitry as claimed in any one of claims 1 to 19.
CN202010505672.3A 2020-06-05 2020-06-05 Read-write conversion circuit and memory Active CN113760174B (en)

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KR1020227022256A KR102865649B1 (en) 2020-06-05 2021-02-01 Read-write conversion circuit and memory
JP2022538927A JP7352741B2 (en) 2020-06-05 2021-02-01 Read and write conversion circuit and memory
PCT/CN2021/074702 WO2021244055A1 (en) 2020-06-05 2021-02-01 Read-write conversion circuit and memory
EP21818317.6A EP4002081A4 (en) 2020-06-05 2021-02-01 Read-write conversion circuit and memory
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