CN113746469A - Level shift circuit, power device and electrical equipment - Google Patents
Level shift circuit, power device and electrical equipment Download PDFInfo
- Publication number
- CN113746469A CN113746469A CN202110824714.4A CN202110824714A CN113746469A CN 113746469 A CN113746469 A CN 113746469A CN 202110824714 A CN202110824714 A CN 202110824714A CN 113746469 A CN113746469 A CN 113746469A
- Authority
- CN
- China
- Prior art keywords
- transistor
- pull
- voltage
- drain
- clamping device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
The application discloses a level shift circuit, a power device and electrical equipment. The level shift circuit comprises a cross-coupled transistor pair and a pair of clamping circuits, wherein the sources of the transistors in the cross-coupled transistor pair are connected with a voltage input end; each clamping circuit in the pair of clamping circuits connects the voltage input end with the grid electrode of each transistor in the transistor pair in a one-to-one correspondence mode, and is used for clamping the grid electrode voltage of the transistor at a set voltage which is smaller than the voltage provided by the voltage input end. The method and the device can solve the problem that the voltage applied to the grid electrode of at least part of transistors in the level shift circuit is approximately equal to the voltage value of the voltage input end.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a level shift circuit, a power device, and an electrical apparatus.
Background
In the existing level shift circuit, the Voltage applied to the gate of at least some transistors is higher and approximately equal to the Voltage value of the power supply Voltage input terminal, and in order to ensure that these transistors can work normally, their withstand Voltage (BV) needs to exceed the Voltage value of the Voltage input terminal. For this reason, the thickness of the gate oxide layer of the transistor is generally required to increase the withstand voltage BV of the transistor, but this reduces the transconductance, and the process is complicated and the cost is increased.
Disclosure of Invention
The main purpose of the present application is to provide a level shift circuit, a power device and an electrical apparatus, so as to solve the problem that the voltage applied to the gate of at least some transistors in the level shift circuit is similar to the voltage value of the voltage input terminal.
In order to solve the above problems, the present application adopts a technical solution that: a level shifting circuit is provided that includes a cross-coupled transistor pair and a pair of clamping circuits:
the source electrode of the transistor in the cross-coupled transistor pair is connected with the power supply voltage input end;
each clamping circuit of the pair of clamping circuits connects the voltage input terminal with the gate of each transistor of the pair of transistors in a one-to-one correspondence for clamping the gate voltage of the transistor of the pair of transistors at a set voltage, wherein the set voltage is less than the voltage provided by the voltage input terminal.
The clamping circuit comprises a clamping device, wherein a first end of the clamping device is connected with the voltage input end, and a second end of the clamping device is connected with the grid electrode of the transistor.
Wherein, the clamping device is a field effect tube;
the clamping circuit further comprises a constant voltage unit, and the constant voltage unit is connected with the grid electrode of the clamping device.
Wherein the constant voltage unit includes a first bias unit and a second bias unit,
the first biasing unit comprises a first transistor and a second transistor, and the second biasing unit comprises a third transistor, a fourth transistor and a resistor;
the source electrodes of the first transistor and the third transistor are connected with a voltage input end, the grid electrode of the first transistor is connected with the grid electrode of the third transistor, and the drain electrode of the third transistor is connected with the grid electrode of the third transistor and the drain electrode of the fourth transistor;
the drain electrode of the second transistor is connected with the drain electrode of the first transistor and the grid electrode of the second transistor, the source electrode of the second transistor is connected with the grounding voltage, the grid electrode of the second transistor is connected with the grid electrode of the fourth transistor, the source electrode of the fourth transistor is connected with the first end of the resistor, and the second end of the resistor is connected with the grounding voltage;
the width-length ratio of the fourth transistor is N times of the width-length ratio of the second transistor, and N is an integer greater than 1; the drain of the third transistor is also connected to the gate of the clamp device.
Wherein the clamping device is a Zener tube;
the clamping circuit comprises a current limiting unit which is connected to the second end of the clamping device.
Wherein the level shifting circuit comprises a first pull-down transistor and a second pull-down transistor, and the cross-coupled transistor pair comprises a first pull-up transistor and a second pull-up transistor;
the drain electrode of the first pull-up transistor is connected with the grid electrode of the second pull-up transistor and the drain electrode of the first pull-down transistor, and the source electrode of the first pull-down transistor is connected with the grounding voltage;
the drain electrode of the second pull-up transistor is connected with the grid electrode of the first pull-up transistor and the drain electrode of the second pull-down transistor, and the source electrode of the second pull-down transistor is connected with the grounding voltage;
the clamping circuit comprises a first clamping device and a second clamping device, wherein the first end of the first clamping device is connected to the voltage input end, the second end of the first clamping device is connected to the drain electrode of the second pull-up transistor, the first end of the second clamping device is connected to the voltage input end, and the second end of the second clamping device is connected to the drain electrode of the first pull-up transistor.
The level shift circuit further comprises an output transistor and a fifth transistor;
the grid electrode of the output transistor is connected to the drain electrode of the first pull-up transistor, the source electrode of the output transistor is connected to the voltage input end, the drain electrode of the output transistor is connected to the drain electrode of the fifth transistor, and the source electrode of the fifth transistor is connected to the grounding voltage.
The first clamping device and the second clamping device are Zener tubes;
the clamping circuit further comprises a first current limiting unit and a second current limiting unit, one end of the first current limiting unit is connected with the second end of the second clamping device and the drain electrode of the first pull-up transistor, the other end of the first current limiting unit is connected with the drain electrode of the first pull-down transistor, one end of the second current limiting unit is connected with the second end of the first clamping device and the drain electrode of the second pull-up transistor, and the other end of the second current limiting unit is connected with the drain electrode of the second pull-down transistor.
The level shift circuit further comprises an input unit and an inverter;
the input unit is connected to the grid electrode of the first pull-down transistor;
one end of the inverter is connected to the input unit, and the other end of the inverter is connected to the gate of the second pull-down transistor and the gate of the fifth transistor.
In order to solve the above problem, another technical solution adopted by the present application is: there is provided a power device comprising the level shift circuit described above.
In order to solve the above problem, the present application adopts another technical solution: an electrical apparatus is provided, which comprises the power device as described above.
The voltage applied to the grid electrodes of the transistors in the transistor pairs is less than or equal to a set voltage through the clamping circuits, so that the voltage applied to the grid electrodes of the transistors in the cross-coupled transistor pairs is lower than the voltage provided by the voltage input end.
Drawings
FIG. 1 is a schematic diagram of a level shift circuit;
FIG. 2 is a schematic diagram of another level shift circuit;
FIG. 3 is a schematic diagram of a level shift circuit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an embodiment of a level shift circuit according to the present application;
FIG. 5 is a schematic diagram of another embodiment of a level shifter circuit of the present application;
FIG. 6 is a schematic diagram of a level shift circuit according to another embodiment of the present application;
FIG. 7 is a schematic structural diagram of an embodiment of a power device of the present application;
fig. 8 is a schematic structural diagram of an embodiment of an electrical apparatus according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In addition, technical solutions between the various embodiments can be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
IN the six-transistor level shift circuit of fig. 1, the source terminals of the first pull-up transistor MP1 and the second pull-up transistor MP2 IN the cross-coupled transistor pair are connected to the voltage input terminal, and the first pull-down transistor MN1, the second pull-down transistor MN2 and the fifth transistor MN3 are electrically connected to the input unit IN; and the drain terminal of the output transistor MP3 is an output terminal for outputting the signal processed by the level shift circuit. Specifically, when the input signal of the input unit IN is high level 1, the first pull-down transistor MN1 is turned on, the second pull-down transistor MN2 and the fifth transistor MN3 are turned off, the second pull-up transistor MP2 is turned on, the first pull-up transistor MP1 is turned off, the output transistor MP3 is turned on, and the drain output of the output transistor MP3 is high. When the input signal of the input unit IN is at low level 0, the first pull-down transistor MN1 is turned off, the second pull-down transistor MN2 and the fifth transistor MN3 are turned on, the second pull-up transistor MP2 is turned off, the first pull-up transistor MP1 is turned on, the output transistor MP3 is turned off, and the drain output of the output transistor MP3 is low. During the use of the level shift circuit, the voltages applied to the gates of the first pull-up transistor MP1 and the second pull-up transistor MP2 are approximately VCC.
Similarly, IN the four-transistor level shift circuit shown IN fig. 2, the source terminals of the first pull-up transistor MP1 and the second pull-up transistor MP2 IN the cross-coupled transistor pair are both connected to the voltage input terminal, and the first pull-down transistor MN1 and the second pull-down transistor MN2 are both electrically connected to the input unit IN; and the drain terminal of the second pull-up transistor MP2 is an output terminal for outputting the signal processed by the level shift circuit. When the input signal of the input unit IN is at high level 1, the first pull-down transistor MN1 is turned on, the second pull-down transistor MN2 is turned off, the second pull-up transistor MP2 is turned on, the first pull-up transistor MP1 is turned off, the drain output of the second pull-up transistor MP2 is high, and the voltage applied to the gate of the first pull-up transistor MP1 is approximately VCC; when the input signal of the input unit IN is at low level 0, the first pull-down transistor MN1 is turned off, the second pull-down transistor MN2 is turned on, the second pull-up transistor MP2 is turned off, the first pull-up transistor MP1 is turned on, the drain output of the second pull-up transistor MP2 is low, and the voltage applied to the gate of the second pull-up transistor MP2 is approximately VCC.
In order to solve the problem that the voltage applied to the grid electrode of the transistor in the cross-coupled transistor pair is similar to VCC in the working process of the level shift circuit, the clamping circuit is arranged in the level shift circuit. The clamp circuit is connected to the gates of the transistors in the cross-coupled transistor pair. The voltage applied to the gate of the transistor in the transistor pair is less than or equal to the set voltage by the clamp circuit. The set voltage is less than the voltage provided by the voltage input terminal, so that the voltage applied to the gates of the transistors in the cross-coupled transistor pair is lower than the voltage provided by the voltage input terminal.
As shown in fig. 3, fig. 3 is a schematic structural diagram of an embodiment of a level shift circuit according to the present application. The level shift circuit of this embodiment includes a pair of cross-coupled transistors and a pair of clamp circuits.
The transistors in the cross-coupled transistor pair of the present application are illustrated as P-channel enhancement MOSFETs, having a gate, a source, and a drain. The first pull-up transistor MP1, the second pull-up transistor MP2, the output transistor MP3, the second field effect transistor MP5, the first field effect transistor MP4, the first transistor M1 and the third transistor M3, which will be described below, are also exemplified by P-channel enhancement MOSFETs, and may be replaced by other types of transistors or circuit elements with similar functions in practice, and the configuration relationship between the other elements is adjusted accordingly.
The source of the transistor in the cross-coupled transistor pair is connected to a voltage input terminal VCC, and the cross-coupled transistor pair can be turned on when a gate-source voltage Vgs is smaller than a certain value, and the voltage of the voltage input terminal VCC is connected to the level shift circuit.
Optionally, each clamp of a pair of clamps connects the input terminal to the gate of each transistor of the transistor pair in a one-to-one correspondence, thereby serving to clamp the gate voltage of the transistors of the cross-coupled transistor pair at a set voltage that is less than the voltage provided by the voltage input terminal.
Optionally, the set voltage may be less than or equal to a withstand voltage value of a transistor in the cross-coupled transistor pair, and the withstand voltage value of the transistor in the cross-coupled transistor pair is less than a voltage provided by the voltage input terminal VCC, so that the transistors in the cross-coupled transistor pair can be ensured to operate normally through the clamp circuit, and a decrease in transconductance due to the thickened gate oxide layer can be avoided.
Further, the cross-coupled transistor pair includes a first pull-up transistor MP1 and a second pull-up transistor MP 2.
The drain of the first pull-up transistor MP1 is connected to the gate of the second pull-up transistor MP2, and the potential difference between the source and the drain of the first pull-up transistor MP1 can be controlled by the clamp circuit, so that the voltage applied to the gate of the second pull-up transistor MP2 is lower than the set voltage when the first pull-up transistor MP1 is turned on.
Alternatively, the clamp circuit may include a second clamp device connected in parallel with the first pull-up transistor MP1 to limit the voltage at the drain of the first pull-up transistor MP1 by the second clamp device connected in parallel with the first pull-up transistor MP1 so that the voltage applied to the gate of the second pull-up transistor MP2 is lower than a set voltage.
Alternatively, as shown in fig. 4, the second clamping device may be a second field effect transistor MP 5. And the clamp circuit may further include a constant voltage unit 101. The gate of the second fet MP5 is connected to the constant voltage unit 101, and the constant voltage unit 101 keeps the gate voltage of the second fet MP5 constant, and the second fet MP5 is turned on, so that the second fet MP5 generates a certain voltage drop VDS5When the first pull-up transistor MP1 is turned on, the drain voltage of the first pull-up transistor MP1 is VCC-VDS5So that the gate applied voltage of the second pull-up transistor MP2 is lower than the set voltage.
Alternatively, the constant voltage unit 101 may include a first biasing unit. The first bias unit includes a first transistor M1 and a second transistor M2.
The constant voltage unit 101 may further include a second biasing unit. The second biasing unit includes a third transistor M3, a fourth transistor M4, and a resistor R1.
The source of the first transistor M1 is connected to the voltage input VCC, and the gate of the first transistor M1 is connected to the gate of the third transistor M3. The source of the third transistor M3 is connected to the voltage input VCC, and the drain of the third transistor M3 is connected to the drain of the fourth transistor M4 and the gate of the third transistor M3.
The drain of the second transistor M2 is connected to the drain of the first transistor M1, and the drain of the second transistor M2 is also connected to the gate of the second transistor M2. The source of the second transistor M2 is connected to the ground voltage GND. The gate of the second transistor M2 is connected to the gate of the fourth transistor M4. A source of the fourth transistor M4 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the ground voltage GND.
Wherein, the width-to-length ratio of the fourth transistor M4 is N times the width-to-length ratio of the second transistor M2. Wherein N is an integer greater than 1, for example, N can be 2 or 4, and the like. The gate of the third transistor M3 is also connected to the gate of the second clamp device and the gate of the first clamp device.
In other embodiments, as shown in fig. 5, the second clamping device may be a second zener D2. The clamp circuit may further include a first current limiting unit R1, the first current limiting unit R1 being connected to the drain of the first pull-up transistor MP 1. A certain voltage drop V is generated by the second Zener diode D2D2When the first pull-up transistor MP1 is turned on, the drain voltage of the first pull-up transistor MP1 is VCC-VD2So that the gate applied voltage of the second pull-up transistor MP2 is lower than the set voltage. The voltage drop of the second Zener diode D2 can be 0.5V-3V.
Alternatively, the first current limiting unit R1 may be a resistor.
In addition, the drain of the second pull-up transistor MP2 may be connected to the gate of the first pull-up transistor MP1, so that the potential difference between the source and the drain of the second pull-up transistor MP2 may be limited by the clamp circuit, so that the voltage applied to the gate of the first pull-up transistor MP1 is lower than the set voltage when the second pull-up transistor MP2 is turned on.
Further, the clamping circuit may further include a first clamping device connected in parallel with the second pull-up transistor MP2 to limit the voltage of the drain of the second pull-up transistor MP2 by the first clamping device connected in parallel with the second pull-up transistor MP2, so that the voltage applied to the gate of the first pull-up transistor MP1 is lower than the set voltage.
Alternatively, as shown in fig. 4, the clamp circuit may further include a constant voltage unit 101. And the first clamp device may be a first field effect transistor MP 4. The constant voltage unit 101 is connected to the gate of the first FET MP4, and the constant voltage unit 101 controls the gate of the first FET MP4The voltage is constant, and the first field effect transistor MP4 is in a conducting state, and the first field effect transistor MP4 generates a certain voltage drop VDS4When the second pull-up transistor MP2 is turned on, the drain voltage of the second pull-up transistor MP2 is VCC-VDS4So that the gate applied voltage of the first pull-up transistor MP1 is lower than the set voltage.
In other embodiments, as shown in fig. 5, the first clamping device may be a first zener D1. The clamp circuit may further include a second current limiting unit R2, the second current limiting unit R2 being connected to the drain of the second pull-up transistor MP 2. A certain voltage drop V is generated by the first zener diode D1D1When the second pull-up transistor MP2 is turned on, the drain voltage of the second pull-up transistor MP2 is VCC-VD1So that the gate applied voltage of the first pull-up transistor MP1 is lower than the set voltage.
With continued reference to fig. 4, the level shift circuit of the present embodiment may further include a first pull-down transistor MN1 and a second pull-down transistor MN 2.
The first pull-down transistor MN1 of the present application is an N-channel enhancement MOSFET, for example, having a gate, a source, and a drain. The second pull-down transistor MN2, the second transistor M2, the fourth transistor M4 and the fifth transistor MN3, which will be described below, are also exemplified as N-channel enhancement MOSFETs, and may be replaced with other types of transistors or circuit elements with similar functions in practice, and the configuration relationship between the other elements is adjusted accordingly.
The source of the first pull-down transistor MN1 is connected to the ground voltage GND. The drain of first pull-down transistor MN1 is connected to the drain of first pull-up transistor MP 1.
Alternatively, when the level shift circuit operates, the switching states of the first pull-down transistor MN1 and the first pull-up transistor MP1 are opposite; the first pull-down transistor MN1 is in a conducting state, the first pull-up transistor MP1 is in a blocking state, the first pull-down transistor MN1 and the second clamping device are connected in series between the voltage input terminal VCC and the ground voltage GND, the second clamping device generates a certain voltage drop, and the voltage of the end of the second clamping device connected to the drain of the first pull-up transistor MP1 is lower than the voltage value of the voltage input terminal VCC and lower than the conducting threshold voltage of the second pull-up transistor MP2, so that the second pull-up transistor MP2 is in a conducting state; the first pull-down transistor MN1 is switched to an off state, the first pull-up transistor MP1 is switched to an on state, and the drain voltage of the first pull-up transistor MP1 is equal to the difference between the voltage value of the voltage input terminal VCC and the voltage drop of the second clamping device, i.e., the voltage applied to the gate of the second pull-up transistor MP2 is equal to the difference between the voltage value of the voltage input terminal VCC and the voltage drop of the second clamping device, so that the voltage applied to the gate of the second pull-up transistor MP2 is lower than the set voltage when the first pull-up transistor MP1 is in the on state.
The source of the second pull-down transistor MN2 is used to access the ground voltage GND. The drain of the second pull-down transistor MN2 is connected to the drain of the second pull-up transistor MP 2.
Alternatively, when the level shift circuit operates, the switching states of the second pull-down transistor MN2 and the second pull-up transistor MP2 are opposite; the second pull-down transistor MN2 is in a conducting state, the second pull-up transistor MP2 is in a blocking state, the second pull-down transistor MN2 and the first clamp device are connected in series between the voltage input terminal VCC and the ground voltage GND, the first clamp device generates a certain voltage drop, and the voltage of the terminal of the first clamp device connected to the drain of the second pull-up transistor MP2 is lower than the voltage value of the voltage input terminal VCC and lower than the conducting threshold voltage of the first pull-up transistor MP1, so that the first pull-up transistor MP1 is in a conducting state; the second pull-down transistor MN2 is switched to an off state, the second pull-up transistor MP2 is switched to an on state, and the drain voltage of the second pull-up transistor MP2 is equal to the difference between the voltage value of the voltage input terminal VCC and the voltage drop of the first clamp device, i.e., the voltage applied to the gate of the first pull-up transistor MP1 is equal to the difference between the voltage value of the voltage input terminal VCC and the voltage drop of the first clamp device, so that the voltage applied to the gate of the first pull-up transistor MP1 is lower than the set voltage when the second pull-up transistor MP2 is in the on state.
In addition, the level shift circuit may further include a fifth transistor MN3 and an output transistor MP 3.
The source of the fifth transistor MN3 is for coupling to the ground voltage GND. The drain of the fifth transistor MN3 is connected to the drain of the output transistor MP3, and the drain of the output transistor MP3 is for output. The gate of the output transistor MP3 is connected to the drain of the first pull-up transistor MP 1. The source of the output transistor MP3 is connected to the voltage input terminal VCC. When the first pull-up transistor MP1, the second pull-up transistor MP2, the first pull-up transistor MP1 and the second pull-down transistor MN2 cooperate to make the output transistor MP3 in an off state and the fifth transistor MN3 in an on state, the drain output voltage of the output transistor MP3 is approximately equal to the ground voltage GND, i.e., the drain of the output transistor MP3 outputs a low level. When the first pull-up transistor MP1, the second pull-up transistor MP2, the first pull-up transistor MP1 and the second pull-down transistor MN2 cooperate to make the output transistor MP3 in an on state, and the fifth transistor MN3 is in an off state, the output voltage of the drain of the output transistor MP3 is approximately VCC, that is, the drain of the output transistor MP3 outputs a high level, because the gate of the output transistor MP3 is connected to the drain of the first pull-up transistor MP1, the gate of the second pull-up transistor MP2 connected to the drain of the first pull-up transistor MP1 is clamped to a set voltage by a clamp circuit, and the gate of the output transistor MP3 can also be clamped to the set voltage to ensure that the output transistor MP3 can normally operate, and the decrease of the transconductance of the output transistor MP3 due to the thickening of the gate oxide layer can be avoided.
Further, the level shift circuit may further include an input unit IN and an inverter INV 11.
IN one implementation, the input unit IN may be directly connected to the first terminal of the inverter INV11 and the gate of the first pull-down transistor MN 1. A second terminal of the inverter INV11 is connected to the gate of the second pull-down transistor MN2, and a second terminal of the inverter INV11 is further connected to the gate of the fifth transistor MN 3. IN this implementation, when the input unit IN outputs a high level, the first pull-down transistor MN1 is IN a turn-on state, the second pull-down transistor MN2 and the fifth transistor MN3 are IN a turn-off state, so that the first pull-up transistor MP1 is IN a turn-off state, and the second pull-up transistor MP2 and the output transistor MP3 are IN a turn-on state, so that the output of the drain of the output transistor MP3 is a high level. And when the input unit IN outputs a low level, the first pull-down transistor MN1 is IN an off state, the second pull-down transistor MN2 and the fifth transistor MN3 are IN an on state, the first pull-up transistor MP1 is IN an on state, the second pull-up transistor MP2 and the output transistor MP3 are IN an off state, and the drain of the output transistor MP3 outputs a low level.
IN another implementation, the input unit IN may be directly connected to the gate of the second pull-down transistor MN2, the gate of the fifth transistor MN3, and the first terminal of the inverter INV 11. A second terminal of the inverter INV11 is connected to the gate of the first pull-down transistor MN 1. IN this implementation, when the input unit IN outputs a high level, the first pull-down transistor MN1 is IN an off state, the second pull-down transistor MN2 and the fifth transistor MN3 are IN an on state, so that the first pull-up transistor MP1 is IN an on state, and the second pull-up transistor MP2 and the output transistor MP3 are IN an off state, so that the output of the drain of the output transistor MP3 is a low level. And when the input unit IN outputs a low level, the first pull-down transistor MN1 is IN an on state, the second pull-down transistor MN2 and the fifth transistor MN3 are IN an off state, the first pull-up transistor MP1 is IN an off state, the second pull-up transistor MP2 and the output transistor MP3 are IN an on state, and the drain of the output transistor MP3 outputs a high level.
For a visual explanation of the level shift circuit of the present application, the following embodiments are provided.
Example 1
As shown IN fig. 4, the level shift circuit includes a cross-coupled transistor pair, an output transistor MP3, an input unit IN, an inverter INV11, a pull-down transistor, a fifth transistor MN3, and a clamp circuit.
The pull-down transistors include a first pull-down transistor MN1 and a second pull-down transistor MN 2.
The cross-coupled transistor pair includes a first pull-up transistor MP1 and a second pull-up transistor MP 2.
The input unit IN may be directly connected to a first terminal of the inverter INV11 and a gate of the first pull-down transistor MN 1. A second terminal of the inverter INV11 is connected to the gate of the second pull-down transistor MN2, and a second terminal of the inverter INV11 is further connected to the gate of the fifth transistor MN 3.
The source of first pull-down transistor MN1 is used to access ground voltage GND. The drain of first pull-down transistor MN1 is connected to the drain of first pull-up transistor MP 1. The source of the first pull-up transistor MP1 is connected to the voltage input VCC.
The source of the second pull-down transistor MN2 is used to access the ground voltage GND. The drain of the second pull-down transistor MN2 is connected to the drain of the second pull-up transistor MP 2. The source of the second pull-up transistor MP2 is connected to the voltage input VCC.
The source of the fifth transistor MN3 is for coupling to the ground voltage GND. The drain of the fifth transistor MN3 is connected to the drain of the output transistor MP 3. The source of the output transistor MP3 is connected to the voltage input terminal VCC. Wherein the drain of the first pull-up transistor MP1 is connected to the gate of the second pull-up transistor MP2, and is also connected to the gate of the output transistor MP 3. In addition, the drain of the second pull-up transistor MP2 is connected to the gate of the first pull-up transistor MP 1.
The clamp circuit includes a second clamp device MP5, a first clamp device MP4, and a constant voltage unit 101.
The constant voltage unit 101 is connected to the gates of the second clamp device MP5 and the first clamp device MP4, and applies a constant voltage to the gates of the second clamp device MP5 and the first clamp device MP4, respectively.
The source of the first clamp device MP4 is connected to the voltage input VCC. The drain of the first clamp device MP4 is connected to the gate of the first pull-up transistor MP1, and the drain of the first clamp device MP4 is also connected to the drain of the second pull-up transistor MP 2.
The source of the second clamp MP5 is connected to the voltage input VCC. The drain of the second clamp device MP5 is connected to the gate of the second pull-up transistor MP2, the gate of the output transistor MP3, and the drain of the first pull-up transistor MP 1.
The constant voltage unit 101 may include a first biasing unit. The first bias unit includes a first transistor M1 and a second transistor M2.
The constant voltage unit 101 may further include a second biasing unit. The second biasing unit includes a third transistor M3, a fourth transistor M4, and a resistor R1.
The source of the first transistor M1 is connected to the voltage input VCC, and the gate of the first transistor M1 is connected to the gate of the third transistor M3. The source of the third transistor M3 is connected to the voltage input VCC, and the drain of the third transistor M3 is connected to the drain of the fourth transistor M4 and the gate of the third transistor M3.
The drain of the second transistor M2 is connected to the drain of the first transistor M1, and the drain of the second transistor M2 is also connected to the gate of the second transistor M2. The source of the second transistor M2 is connected to the ground voltage GND. The gate of the second transistor M2 is connected to the gate of the fourth transistor M4. A source of the fourth transistor M4 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the ground voltage GND.
Wherein, the width-to-length ratio of the fourth transistor M4 is N times the width-to-length ratio of the second transistor M2. The gate of the third transistor M3 is also connected to the gate of the second clamp device MP4 and the gate of the first clamp device MP 1.
Example 2
As shown IN fig. 5, the level shift circuit includes a cross-coupled transistor pair, an output transistor MP3, an input unit IN, an inverter INV11, a pull-down transistor, a fifth transistor MN3, and a clamp circuit.
The pull-down transistors include a first pull-down transistor MN1 and a second pull-down transistor MN 2.
The cross-coupled transistor pair includes a first pull-up transistor MP1 and a second pull-up transistor MP 2.
The input unit IN may be directly connected to a first terminal of the inverter INV11 and a gate of the first pull-down transistor MN 1. A second terminal of the inverter INV11 is connected to the gate of the second pull-down transistor MN2, and a second terminal of the inverter INV11 is further connected to the gate of the fifth transistor MN 3.
The source of first pull-down transistor MN1 is used to access ground voltage GND. The drain of first pull-down transistor MN1 is connected to the drain of first pull-up transistor MP 1. The source of the first pull-up transistor MP1 is connected to the voltage input VCC.
The source of the second pull-down transistor MN2 is used to access the ground voltage GND. The drain of the second pull-down transistor MN2 is connected to the drain of the second pull-up transistor MP 2. The source of the second pull-up transistor MP2 is connected to the voltage input VCC.
The source of the fifth transistor MN3 is for coupling to the ground voltage GND. The drain of the fifth transistor MN3 is connected to the drain of the output transistor MP 3. The source of the output transistor MP3 is connected to the voltage input terminal VCC. Wherein the drain of the first pull-up transistor MP1 is connected to the gate of the second pull-up transistor MP2, and is also connected to the gate of the output transistor MP 3. In addition, the drain of the second pull-up transistor MP2 is connected to the gate of the first pull-up transistor MP 1.
The clamping circuit comprises a first Zener diode D1, a second Zener diode D2, a first current limiting resistor R1 and a second current limiting resistor R2. A first terminal of the first zener D1 is connected to the voltage input terminal VCC, and a second terminal of the first zener D1 is connected to the drain of the second pull-up transistor MP 2. The first terminal of the second current limiting resistor R2 is connected to the second terminal of the first zener diode D1, and the first terminal of the second current limiting resistor R2 is further connected to the drain of the second pull-up transistor MP 2. A second terminal of the second current limiting resistor R2 is connected to the drain of the second pull-down transistor MN 2. A first terminal of the second zener diode D2 is connected to the voltage input terminal VCC, and a second terminal of the second zener diode D2 is connected to the drain of the first pull-up transistor MP 1. The first end of the first current limiting resistor R1 is connected to the second end of the second zener diode D2, and the first end of the first current limiting resistor R1 is further connected to the drain of the first pull-up transistor MP 1. A second terminal of the first current limiting resistor R1 is connected to the drain of a first pull-down transistor MN 1.
Example 3
As shown IN fig. 6, the level shift circuit includes a cross-coupled transistor pair, an input unit IN, an inverter INV11, a pull-down transistor, and a clamp circuit.
The cross-coupled transistor pair includes a first pull-up transistor MP1 and a second pull-up transistor MP 2.
The pull-down transistors include a first pull-down transistor MN1 and a second pull-down transistor MN 2.
The input unit IN may be directly connected to a first terminal of the inverter INV11 and a gate of the first pull-down transistor MN 1. The second terminal of the inverter INV11 is also connected to the gate of the second pull-down transistor MN 2.
The source of first pull-down transistor MN1 is used to access ground voltage GND. The drain of first pull-down transistor MN1 is connected to the drain of first pull-up transistor MP 1. The source of the first pull-up transistor MP1 is connected to the voltage input VCC.
The source of the second pull-down transistor MN2 is used to access the ground voltage GND. The drain of the second pull-down transistor MN2 is connected to the drain of the second pull-up transistor MP2, and the source of the second pull-up transistor MP2 is connected to the voltage input VCC. Wherein the drain of the first pull-up transistor MP1 is connected to the gate of the second pull-up transistor MP 2. The drain of the second pull-up transistor MP2 is connected to the gate of the first pull-up transistor MP 1.
The clamp circuit includes a first zener D1, a second current limiting unit R2, a second zener D2, and a first current limiting unit R1.
A first terminal of the first zener diode D1 is coupled to the voltage input terminal VCC. The second terminal of the first zener diode D1 is connected to the drain of the first pull-up transistor MP 1.
A first end of the first current limiting unit R1 is connected with a second end of the first zener tube D1. And the first terminal of the first current limiting unit R1 is also connected to the drain of the first pull-up transistor MP 1. A second terminal of the first current limiting unit R1 is connected to the drain of the first pull-down transistor MN 1.
A first terminal of the second zener diode D2 is connected to the voltage input terminal VCC. The second terminal of the second Zener diode D2 is connected to the drain of the second pull-up transistor MP 2.
A first end of the second current limiting unit R2 is connected to a second end of the second zener tube D2. The first terminal of the second current limiting unit R2 is also connected to the drain of the second pull-up transistor MP 2. The second terminal of the second current limiting unit R2 is connected to the drain of the second pull-down transistor MN 2.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a power device 10 according to an embodiment of the present disclosure. The power device 10 includes the level shift circuit 11 described above. The power device may be an IPM module or the like.
Referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of an electrical apparatus 20 according to the present application. The electrical apparatus 20 includes the above-described power device 21. The electrical appliance 20 may be a household appliance, such as a washing machine, a dishwasher, an electric rice cooker, an electric pressure cooker, an electric stewpan, or an oven.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (11)
1. A level shifting circuit, comprising:
a cross-coupled transistor pair, the sources of the transistors in the transistor pair being connected to a voltage input;
and each clamping circuit in the pair of clamping circuits connects the voltage input end with the grid electrode of each transistor in the transistor pair in a one-to-one correspondence mode, and is used for clamping the grid electrode voltage of the transistor at a set voltage, and the set voltage is smaller than the voltage provided by the voltage input end.
2. The level shifting circuit of claim 1,
the clamping circuit comprises a clamping device, wherein a first end of the clamping device is connected with the voltage input end, and a second end of the clamping device is connected with the grid electrode of the transistor.
3. The level shifting circuit of claim 2, wherein the clamping device is a field effect transistor;
the clamping circuit further comprises a constant voltage unit, and the constant voltage unit is connected with the grid electrode of the clamping device.
4. The level shift circuit of claim 3, wherein the constant voltage unit includes a first bias unit and a second bias unit,
the first biasing unit comprises a first transistor and a second transistor, and the second biasing unit comprises a third transistor, a fourth transistor and a resistor;
the sources of the first transistor and the third transistor are connected to the voltage input end, the gate of the first transistor is connected to the gate of the third transistor, and the drain of the third transistor is connected to the gate of the third transistor and the drain of the fourth transistor;
the drain electrode of the second transistor is connected with the drain electrode of the first transistor and the grid electrode of the second transistor, the source electrode of the second transistor is connected with the grounding voltage, the grid electrode of the second transistor is connected with the grid electrode of the fourth transistor, the source electrode of the fourth transistor is connected with the first end of the resistor, the second end of the resistor is connected with the grounding voltage,
the width-to-length ratio of the fourth transistor is N times of the width-to-length ratio of the second transistor, and N is an integer greater than 1;
the drain of the third transistor is also connected to the gate of the clamping device.
5. The level shifting circuit of claim 2,
the clamping device is a Zener tube;
the clamping circuit comprises a current limiting unit which is connected to the second end of the clamping device.
6. The level shifting circuit of claim 2, wherein the level shifting circuit comprises a first pull-down transistor and a second pull-down transistor, wherein the cross-coupled transistor pair comprises a first pull-up transistor and a second pull-up transistor;
the drain electrode of the first pull-up transistor is connected to the grid electrode of the second pull-up transistor and the drain electrode of the first pull-down transistor, and the source electrode of the first pull-down transistor is connected to the grounding voltage;
the drain electrode of the second pull-up transistor is connected with the grid electrode of the first pull-up transistor and the drain electrode of the second pull-down transistor, and the source electrode of the second pull-down transistor is connected with a grounding voltage;
the clamping circuit comprises a first clamping device and a second clamping device, wherein a first end of the first clamping device is connected to the voltage input end, a second end of the first clamping device is connected to the drain electrode of the second pull-up transistor, a first end of the second clamping device is connected to the voltage input end, and a second end of the second clamping device is connected to the drain electrode of the first pull-up transistor.
7. The level shift circuit according to claim 6, wherein the level shift circuit further comprises an output transistor and a fifth transistor;
the grid electrode of the output transistor is connected to the drain electrode of the first pull-up transistor, the source electrode of the output transistor is connected to the voltage input end, the drain electrode of the output transistor is connected to the drain electrode of the fifth transistor, and the source electrode of the fifth transistor is connected to the ground voltage.
8. The level shifting circuit of claim 7, wherein the first clamping device and the second clamping device are both Zener transistors,
the clamping circuit further comprises a first current limiting unit and a second current limiting unit, wherein one end of the first current limiting unit is connected with the second end of the second clamping device and the drain electrode of the first pull-up transistor, the other end of the first current limiting unit is connected with the drain electrode of the first pull-down transistor, one end of the second current limiting unit is connected with the second end of the first clamping device and the drain electrode of the second pull-up transistor, and the other end of the second current limiting unit is connected with the drain electrode of the second pull-down transistor.
9. The level shifting circuit of claim 7, further comprising:
an input unit connected to a gate of the first pull-down transistor;
and one end of the inverter is connected to the input unit, and the other end of the inverter is connected to the grid electrode of the second pull-down transistor and the grid electrode of the fifth transistor.
10. A power device characterized in that it comprises a level shifting circuit according to any of claims 1 to 9.
11. An electrical apparatus, characterized in that the electrical apparatus comprises a power device according to claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110824714.4A CN113746469A (en) | 2021-07-21 | 2021-07-21 | Level shift circuit, power device and electrical equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110824714.4A CN113746469A (en) | 2021-07-21 | 2021-07-21 | Level shift circuit, power device and electrical equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113746469A true CN113746469A (en) | 2021-12-03 |
Family
ID=78728901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110824714.4A Pending CN113746469A (en) | 2021-07-21 | 2021-07-21 | Level shift circuit, power device and electrical equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113746469A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000074289A (en) * | 1999-05-19 | 2000-12-15 | 김영환 | Level shifter for high voltage integrated circuits |
| US6201429B1 (en) * | 1999-05-20 | 2001-03-13 | Analog Microelectronics, Inc. | Clamped cascode level shifter circuit |
| JP2005204281A (en) * | 2003-12-18 | 2005-07-28 | Matsushita Electric Ind Co Ltd | Level shift circuit |
| US20100123478A1 (en) * | 2008-11-17 | 2010-05-20 | Sanken Electric Co., Ltd. | Level shift circuit |
| US20100201425A1 (en) * | 2009-02-10 | 2010-08-12 | Tzong-Yau Ku | Level shift circuit |
| US20110303988A1 (en) * | 2009-09-11 | 2011-12-15 | Elpida Memory, Inc. | Semiconductor device and level shift circuit using the same |
| US20130021085A1 (en) * | 2011-07-19 | 2013-01-24 | Lsi Corporation | Voltage Level Translator Circuit for Reducing Jitter |
| CN102904565A (en) * | 2012-10-09 | 2013-01-30 | 长安大学 | A Level Shift Circuit for Ultra-low Quiescent Current Driven by DC-DC |
| CN107896103A (en) * | 2017-12-21 | 2018-04-10 | 广东美的制冷设备有限公司 | Level built-up circuit and IC chip, air conditioner comprising it |
| CN108155903A (en) * | 2017-11-22 | 2018-06-12 | 中山大学 | High speed and high pressure level shifting circuit applied to GaN gate drivings |
| CN112073054A (en) * | 2019-06-10 | 2020-12-11 | 上海韦尔半导体股份有限公司 | Level shifter |
-
2021
- 2021-07-21 CN CN202110824714.4A patent/CN113746469A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000074289A (en) * | 1999-05-19 | 2000-12-15 | 김영환 | Level shifter for high voltage integrated circuits |
| US6201429B1 (en) * | 1999-05-20 | 2001-03-13 | Analog Microelectronics, Inc. | Clamped cascode level shifter circuit |
| JP2005204281A (en) * | 2003-12-18 | 2005-07-28 | Matsushita Electric Ind Co Ltd | Level shift circuit |
| US20100123478A1 (en) * | 2008-11-17 | 2010-05-20 | Sanken Electric Co., Ltd. | Level shift circuit |
| US20100201425A1 (en) * | 2009-02-10 | 2010-08-12 | Tzong-Yau Ku | Level shift circuit |
| US20110303988A1 (en) * | 2009-09-11 | 2011-12-15 | Elpida Memory, Inc. | Semiconductor device and level shift circuit using the same |
| US20130021085A1 (en) * | 2011-07-19 | 2013-01-24 | Lsi Corporation | Voltage Level Translator Circuit for Reducing Jitter |
| CN102904565A (en) * | 2012-10-09 | 2013-01-30 | 长安大学 | A Level Shift Circuit for Ultra-low Quiescent Current Driven by DC-DC |
| CN108155903A (en) * | 2017-11-22 | 2018-06-12 | 中山大学 | High speed and high pressure level shifting circuit applied to GaN gate drivings |
| CN107896103A (en) * | 2017-12-21 | 2018-04-10 | 广东美的制冷设备有限公司 | Level built-up circuit and IC chip, air conditioner comprising it |
| CN112073054A (en) * | 2019-06-10 | 2020-12-11 | 上海韦尔半导体股份有限公司 | Level shifter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101826794B (en) | Reverse current prevention circuit and power supply switching apparatus | |
| US8385036B2 (en) | System and method for negative voltage protection | |
| US7034573B1 (en) | Level shifter without DC current flow | |
| CN108123708B (en) | Pull-up circuit for IO circuit | |
| CN107733404B (en) | Current-limiting detection and protection circuit for NMOS load switch | |
| US20100085080A1 (en) | Electronic device with a high voltage tolerant unit | |
| US9698774B2 (en) | 20V to 50V high current ASIC PIN diode driver | |
| CN100574030C (en) | Leakage current protection circuit | |
| US10574224B2 (en) | Drive circuit of transistor | |
| EP0095767A2 (en) | Output circuit | |
| CN113746469A (en) | Level shift circuit, power device and electrical equipment | |
| JPS6077520A (en) | Control circuit of drive circuit | |
| US20100117690A1 (en) | Semiconductor device | |
| US8907719B2 (en) | IC circuit | |
| CN108809296A (en) | High-pressure level shift circuit and driving device | |
| CN218183335U (en) | Signal conversion circuit | |
| CN107894530A (en) | Negative voltage detection circuit and motor driver | |
| US7239176B2 (en) | Voltage tolerant protection circuit for input buffer | |
| CN110829820A (en) | Driving device for totem pole circuit | |
| CN115085698B (en) | Fully differential level shifter | |
| CN112737552B (en) | Signal transmission circuit | |
| KR19990081046A (en) | Voltage level shifter circuit | |
| CN211296707U (en) | Cross-voltage-domain selectable built-in pull-up resistor multiplexing system | |
| US6501298B1 (en) | Level-shifting circuitry having “low” output during disable mode | |
| CN110932716A (en) | Cross-voltage-domain selectable built-in pull-up resistor multiplexing system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211203 |
|
| RJ01 | Rejection of invention patent application after publication |