CN113742176A - Fault prediction method and device and electronic equipment - Google Patents
Fault prediction method and device and electronic equipment Download PDFInfo
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Abstract
本申请提供了一种故障预测方法，包括：监测所述目标存储芯片，记录发生擦除的时间以及次数；基于所述发生擦除的时间以及次数满足预设的故障条件，生成告警信息，以预警所述目标存储芯片处于危险状态。本方案中，通过实时检测目标存储芯片每次发生擦除的时间和发生的次数，掌握该目标存储芯片的情况，在该发生擦除的时间以及次数满足预设的故障条件时，生成告警信息，预警用户该目标存储芯片处于危险状态，以使得用户基于该预警进行操作，如关闭电源停止该目标存储芯片被继续擦写，达到保护目标存储芯片的目的。
The present application provides a fault prediction method, including: monitoring the target memory chip, recording the time and number of erasures; Warning that the target memory chip is in a dangerous state. In this solution, the situation of the target memory chip is grasped by detecting the erasure time and the number of occurrences of the target memory chip in real time, and an alarm message is generated when the erasure time and the number of times meet the preset fault conditions. , to warn the user that the target memory chip is in a dangerous state, so that the user can perform operations based on the warning, such as turning off the power to stop the target memory chip from continuing to be erased and written, so as to achieve the purpose of protecting the target memory chip.
Description
Technical Field
The present application relates to the field of information processing, and in particular, to a failure prediction method, an apparatus, and an electronic device.
Background
flash (coded flash memory) chips are very widely used memory materials, which can rapidly store and erase data. Flash is generally designed with a design upper limit of erase (erase), and when the erase frequency reaches the design upper limit, the Flash chip will be damaged after reaching the service life.
However, when some programs or other functions in the device are running, the erasing frequency of a part of the memory on the flash chip is accelerated, which easily causes the flash chip to reach the design upper limit, so that the flash chip is damaged when reaching the service life, and the system may not be booted.
Disclosure of Invention
In view of the above, the present application provides a failure prediction method, which includes:
a method of fault prediction, comprising:
monitoring the target memory chip, and recording the time and the times of erasing;
and generating alarm information based on the time and the times of erasing meeting the preset fault condition so as to early warn that the target memory chip is in a dangerous state.
Optionally, the method for judging that the time and the number of times of erasing meet the preset fault condition includes:
analyzing and obtaining an average cycle of erasing the target memory chip in a preset time period based on the time and the times of erasing the target memory chip, wherein the preset time period comprises at least two average cycles;
judging whether the times and the average period meet preset fault conditions or not;
and judging that the erasing information meets the preset fault condition based on the number of times and the average period meeting the preset fault condition.
Optionally, the method for judging whether the number of times and the average period satisfy the preset fault condition includes:
judging whether the times are larger than a preset first time threshold value or not to obtain a first judgment result;
representing that the times are greater than a preset first time threshold value based on a first judgment result, and judging whether the average period is less than a preset first period threshold value to obtain a second judgment result;
and representing that the average period is smaller than a preset first period threshold value based on the second judgment result, and judging that the erasing information meets a preset fault condition.
Optionally, in the method, the preset number of times threshold includes at least two number of times thresholds, and the preset period threshold includes at least two period thresholds;
wherein, after the representing that the average period is smaller than the preset first period threshold value based on the second determination result, the method further includes:
analyzing and obtaining the erasing interval time of the target memory chip within a preset time period based on the erasing time of the target memory chip;
judging whether the erasing interval time of the target storage chip in the preset time period meets a preset fixed period condition or not to obtain a third judgment result;
representing that the erasing interval time of the target memory chip in the preset time period meets a preset fixed period condition based on the third judgment result, and judging that the erasing information meets a preset fault condition;
representing that the erasing interval time of the target memory chip in the preset time period does not meet a preset fixed period condition based on the third judgment result, judging whether the times are greater than a preset second time threshold value or not, and obtaining a fourth judgment result, wherein the second time threshold value is greater than the first time threshold value;
representing that the times are greater than a preset second time threshold value based on a fourth judgment result, and judging whether the average period is smaller than a preset second period threshold value or not to obtain a fifth judgment result, wherein the second period threshold value is greater than the first period threshold value;
and representing that the average period is smaller than a preset second period threshold value based on the fifth judgment result, and judging that the erasing information meets a preset fault condition.
Optionally, in the method, the generating warning information to warn that the target memory chip is in a dangerous state includes:
and generating alarm information, and sending the alarm information to a substrate management controller, so that the substrate management controller adds the alarm information in webpage configuration information, and alarms on the webpage.
Optionally, in the method, the generating warning information to warn that the target memory chip is in a dangerous state includes:
and generating alarm information and sending the alarm information to an operating system so that the operating system outputs display content in a display screen by configuring extensible firmware interface parameters, wherein the display content is used for early warning that the target storage chip is in a dangerous state.
A failure prediction apparatus comprising:
the monitoring module is used for monitoring the target memory chip and recording the time and the times of erasing;
and the early warning module is used for generating warning information based on the condition that the erasing time and times meet the preset fault condition so as to early warn that the target storage chip is in a dangerous state.
Optionally, the above apparatus further includes:
the analysis module is used for analyzing and obtaining the average cycle of the target memory chip in a preset time period based on the time and the times of erasing of the target memory chip, wherein the preset time period comprises at least two average cycles; judging whether the times and the average period meet preset fault conditions or not; and judging that the erasing information meets the preset fault condition based on the number of times and the average period meeting the preset fault condition.
An electronic device, comprising: a memory, a processor;
wherein, the memory stores a processing program;
the processor is configured to load and execute the processing program stored in the memory to implement the steps of the failure prediction method according to any one of the above.
A readable storage medium having stored thereon a computer program for being invoked and executed by a processor for carrying out the steps of the failure prediction method according to any one of the preceding claims.
As can be seen from the above technical solutions, the present application provides a failure prediction method, including: monitoring the target memory chip, and recording the time and the times of erasing; and generating alarm information based on the time and the times of erasing meeting the preset fault condition so as to early warn that the target memory chip is in a dangerous state. According to the scheme, the situation of the target memory chip is mastered by detecting the erasing time and the erasing frequency of the target memory chip in real time, when the erasing time and the erasing frequency meet preset fault conditions, warning information is generated, and a user is warned that the target memory chip is in a dangerous state, so that the user can operate based on the warning, if the power supply is turned off, the target memory chip is stopped to be continuously erased, and the purpose of protecting the target memory chip is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of an embodiment 1 of a fault prediction method provided in the present application;
fig. 2 is a flowchart of an embodiment 2 of a fault prediction method provided in the present application;
fig. 3 is a flowchart of embodiment 3 of a fault prediction method provided in the present application;
fig. 4 is a flowchart of an embodiment 4 of a fault prediction method provided in the present application;
fig. 5 is a flowchart of an embodiment 5 of a fault prediction method provided in the present application;
fig. 6 is a flowchart of an embodiment 6 of a fault prediction method provided in the present application;
fig. 7 is a schematic structural diagram of an embodiment 1 of a failure prediction apparatus provided in the present application;
fig. 8 is a schematic structural diagram of a failure prediction apparatus according to embodiment 2 of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1, a flowchart of an embodiment 1 of a failure prediction method provided by the present application is applied to an electronic device, and the method includes the following steps:
step S101: monitoring the target memory chip, and recording the time and the times of erasing;
the time and the times of erasing the target memory chip are recorded by monitoring software.
Specifically, the time when the erasure occurs may be a specific time.
Wherein, every time an erasure occurs, the erasure time is recorded and the number of times is accumulated.
Step S102: and generating alarm information based on the time and the times of erasing meeting the preset fault condition so as to early warn that the target memory chip is in a dangerous state.
If the time and the times based on the erasure meet the preset fault conditions, alarm information is generated to remind a user that the target memory chip is in a dangerous state.
It should be noted that, in the present application, the situation of the target memory chip is grasped by detecting the time and the number of times of occurrence of each erasure of the target memory chip in real time, and an alarm is given when the target memory chip is in a dangerous state, so that a user can quickly know the situation of the target memory chip.
In summary, the failure prediction method provided in this embodiment includes: monitoring the target memory chip, and recording the time and the times of erasing; and generating alarm information based on the time and the times of erasing meeting the preset fault condition so as to early warn that the target memory chip is in a dangerous state. According to the scheme, the situation of the target memory chip is mastered by detecting the erasing time and the erasing frequency of the target memory chip in real time, when the erasing time and the erasing frequency meet preset fault conditions, warning information is generated, and a user is warned that the target memory chip is in a dangerous state, so that the user can operate based on the warning, if the power supply is turned off, the target memory chip is stopped to be continuously erased, and the purpose of protecting the target memory chip is achieved.
As shown in fig. 2, a flowchart of embodiment 2 of a fault prediction method provided in the present application is provided, where the method includes the following steps:
step S201: monitoring the target memory chip, and recording the time and the times of erasing;
step S201 is the same as step S101 in embodiment 1, and details are not described in this embodiment.
Step S202: analyzing and obtaining an average period of erasing the target memory chip within a preset time period based on the time and the times of erasing the target memory chip;
wherein the preset time period comprises at least two average cycles.
The method comprises the steps of obtaining the erasing times of a target storage chip according to a preset time period, wherein the preset time period can be obtained by selecting a certain erasing as a first analysis erasing, selecting a subsequent certain erasing as a last analysis erasing and calculating the time difference between the first analysis erasing and the last analysis erasing.
For example, if the time for the first analysis erase is 01:20:25 and the time for the last analysis erase is 01:25:25, the calculated preset time period is 5 minutes.
Specifically, the number of times of erasing of the target memory chip in the preset time period is determined, and if the last analysis erasing is 10 times and the first analysis erasing is 2 times, the number of times of erasing is calculated to be 8 times.
Then, the average period can be obtained by calculating based on the duration of the preset time period and the erasing times in the time period.
Specifically, the preset time period is 5 minutes, and the number of times of erasing is 8, then the average period is calculated as follows: 5 minutes/8 times 37.5 seconds/time, i.e. the average period is 37.5 seconds.
In a specific implementation, the preset time period may be randomly selected, or may be selected according to a set time threshold, and the preset time period may be calculated within the preset time threshold.
The time threshold may be 5-10 minutes, 2-3 minutes, 30-35 minutes or other thresholds, which are not limited in this application.
Step S203: judging whether the times and the average period meet preset fault conditions or not;
if the number of times and the average period satisfy the preset fault condition, it is determined that the erasure information satisfies the preset fault condition, and step S204 is executed.
The electronic device is also preset with a fault condition, and the fault condition is respectively related to the times and the average period.
Specifically, the number of times of erasing is large, and the frequency of erasing is high, it can be considered that the target memory chip is frequently erased and fails.
For example, if the number of times is greater than the number threshold and the average period is less than the period threshold, the preset fault condition is satisfied.
Step S204: and generating alarm information to warn that the target storage chip is in a dangerous state.
Step S204 is the same as step S102 in embodiment 1, and details are not described in this embodiment.
In summary, in the method for predicting a failure provided in this embodiment, the determining that the time and the number of times of erasing meet the preset failure condition includes: analyzing and obtaining the average period of the target memory chip in a preset time period based on the time and the times of erasing the target memory chip, wherein the preset time period comprises at least two average periods; judging whether the times and the average period meet preset fault conditions or not; and judging that the erasing information meets the preset fault condition based on the number of times and the average period meeting the preset fault condition. In the scheme, whether a fault occurs is judged based on the number of times of erasing in a period of time and the average period of erasing in the period of time, the fault can be judged only by simple calculation, and the data processing amount is small.
As shown in fig. 3, a flowchart of embodiment 3 of a fault prediction method provided in the present application is provided, where the method includes the following steps:
step S301: monitoring the target memory chip, and recording the time and the times of erasing;
step S302: analyzing and obtaining an average cycle of erasing the target memory chip in a preset time period based on the time and the times of erasing the target memory chip, wherein the preset time period comprises at least two average cycles;
steps S301 to 302 are the same as steps S201 to 202 in embodiment 2, and are not described in detail in this embodiment.
Step S303: judging whether the times are greater than a preset first time threshold value or not;
if the number of times of erasing the target memory chip in the preset time period is greater than the first time threshold value, the target memory chip is erased for a plurality of times in the time period.
The first time threshold value may be a small value, such as 100 times or 50 times. In order to quickly find out the failure situation when a large number of erasures occur.
For example, in the preset time period, only 10 times of erasing occurs, and if the number of erasing is less than the first threshold value for 100 times, it may be determined that the target memory chip is normal in the time period, and no alarm is needed; if the number of times of erasing is 110 times in the preset time period, which is greater than the first threshold value of 100 times, the target memory chip may fail, and step S304 is triggered.
In order to improve the accuracy of the determination, when the number of times of erasing the target memory chip in the preset time period is greater than the first time threshold, step S304 is triggered.
Step S304: judging whether the average period is smaller than a preset first period threshold value or not;
and judging that the erasing information meets a preset fault condition based on the second judgment result representing that the average period is smaller than a preset first period threshold value.
The first cycle threshold is an average cycle critical value of the memory chip that is erased normally, such as 1000 seconds, 500 seconds, and the like, and the value may be set by a technician according to historical experience.
For example, in the preset time period, 110 times of erasing occurs, which is greater than the first time threshold value by 100 times, and the average period is 5 seconds and is less than the first period threshold value by 1000 seconds, it is determined that the target memory chip is frequently erased, step S305 is triggered, and an alarm is given.
If the average period is smaller than the first period threshold, it indicates that the target memory chip is frequently erased in the preset time period, and the target memory chip is in a fault condition.
Therefore, if the average period is less than the preset first period threshold, step S305 is triggered.
It should be noted that, in the present application, specific values of the first time threshold and the first period threshold are not limited.
Step S305: and generating alarm information to warn that the target storage chip is in a dangerous state.
Step S305 is the same as step S205 in embodiment 2, and is not described in detail in this embodiment.
In summary, in the fault prediction method provided in this embodiment, determining whether the number of times and the average period satisfy the preset fault condition includes: judging whether the times are larger than a preset first time threshold value or not to obtain a first judgment result; representing that the times are greater than a preset first time threshold value based on a first judgment result, and judging whether the average period is less than a preset first period threshold value to obtain a second judgment result; and representing that the average period is smaller than a preset first period threshold value based on the second judgment result, and judging that the erasing information meets a preset fault condition. In the scheme, based on the number of times of erasing the target memory chip in the preset time period and the average erasing period, the target memory chip is judged respectively, the condition that the target memory chip is frequently erased in the time period is determined, the target memory chip is in a fault condition, early warning is needed, only simple data calculation is needed, and the data processing amount is small.
As shown in fig. 4, a flowchart of embodiment 4 of a fault prediction method provided in the present application is provided, where the method includes the following steps:
step S401: monitoring the target memory chip, and recording the time and the times of erasing;
step S402: analyzing and obtaining the average period of the target memory chip in a preset time period based on the time and the times of erasing the target memory chip, wherein the preset time period comprises at least two average periods;
step S403: judging whether the times are greater than a preset first time threshold value or not;
when the number of times of erasing the target memory chip in the preset time period is greater than the first time threshold, step S404 is triggered.
Step S404: judging whether the average period is smaller than a preset first period threshold value or not;
if the average period is smaller than the preset first period threshold, step S405 is triggered.
Steps S401 to 404 are the same as steps S401 to 404 in embodiment 3, and are not described in detail in this embodiment.
Step S405: analyzing and obtaining the erasing interval time of the target memory chip within a preset time period based on the erasing time of the target memory chip;
and analyzing and determining the interval time of the erasure based on each time of the erasure of the target memory chip in the preset time period.
Specifically, the erasing time interval is obtained by subtracting the erasing time intervals of any two times, and the erasing time intervals of the target memory chip in the preset time period are obtained by sequentially subtracting the erasing time intervals of two adjacent times in the preset time period.
As an example, where N is an integer greater than 1, the N-1 th erasure occurs at 01:20:21, the N erasure occurs at 01:21:00, and the N +1 th erasure occurs at 01:21:05, two erasure interval times are calculated: 49 seconds and 5 seconds.
Step S406: judging whether the erasing interval time of the target memory chip meets a preset fixed period condition or not;
the preset fixed period condition means that all the interval times are the same, and the memory chip is erased in a fixed period.
It should be noted that when the software is set incorrectly, the software may frequently erase the memory chip at a fixed frequency/period due to incompatibility between the software and the target memory chip or other problems, and the system may quickly enter a dangerous state according to the trend.
Due to the erasing operation of the memory chip caused by the software setting error, the error is characterized by very fast erasing frequency and occurs in a fixed period (the time interval between two times is the same). The method has the advantages that the growth speed is very high, the potential safety hazard is high, but the potential safety hazard is well confirmed, so that the method adopts the setting of a small erasing frequency and an average period for judgment.
Therefore, in this embodiment, whether the erasure information satisfies the failure condition is determined by determining whether the erasure information occurs frequently in the predetermined period of time and the memory chips are erased at a fixed cycle.
If the erase frequently occurred within the preset time period is not performed in a fixed cycle, it may be that the increase is too fast due to the flash test within a time period, and the monitoring is continued, and step S407 is performed.
If it is further determined that the erasing interval time of the target memory chip within the preset time period satisfies the preset fixed cycle condition, it is determined that the erasing information satisfies the preset fault condition, and step S409 is executed;
if the further judgment is made, the erasing interval time of the target memory chip in the preset time period does not meet the preset fixed cycle condition, the step S407 is executed.
Step S407: judging whether the times are larger than a preset second time threshold value or not;
wherein the second nonce threshold is greater than the first nonce threshold;
wherein, if the number of times is greater than the preset second number threshold, the step S408 is executed.
It should be noted that if the erasing of the target memory chip is not performed according to a fixed cycle, the erasing operation may be increased too fast due to a targeted flash test, which may be performed only for a period of time, but the memory chip may also be failed due to too many erased memory chips.
The targeted flash test is characterized by a fast erase and write frequency, but not a long duration. The total number of final erasures is also safe. A slightly larger number threshold and period threshold may be set for determination.
Therefore, the determination is performed again based on a larger number threshold, if the number of times of erasing the target memory chip is greater than the second number threshold, it is characterized that a larger number of times of erasing occurs, and for a fault hidden trouble of the target memory chip, step S408 is executed to further determine whether an alarm is required.
If the number of times of erasing the target memory chip is not more than the second time threshold value, the occurrence of erasing is represented to be in an allowable range, and the erasing of the target memory chip can be continuously counted and judged.
The second threshold value may be a larger value, such as 1000 times or 2000 times. In order to find out this situation in time when a large number of erasures occur due to the flash test.
Step S408: judging whether the average period is smaller than a preset second period threshold value or not;
wherein the second cycle threshold is greater than the first cycle threshold.
Wherein, the average period is smaller than a preset second period threshold, and step S409 is executed when it is determined that the erasure information satisfies a preset fault condition.
When a large number of target memory chips are erased due to the flash test, the erasing occurring in the time period is judged, and whether the average erasing period is smaller than the threshold of the second period is determined, so as to determine whether the frequency of erasing the target memory chips is too fast, and at this time, the system may be in a dangerous state.
The second period threshold is greater than the first period threshold, and may be a larger value, such as 10 ten thousand seconds, 1 ten thousand seconds, and the like.
It should be noted that, by setting different times threshold values and cycle threshold values, a large number of erasures caused by different reasons can be judged, and different methods are adopted for processing, so that the accuracy of fault prediction is improved.
In specific implementation, other times threshold values and cycle threshold values can be set according to actual conditions to determine a large number of erasures caused by more reasons, and then corresponding processing is performed.
Step S409: and generating alarm information to warn that the target storage chip is in a dangerous state.
Step S409 is the same as step S305 in embodiment 3, and is not described in detail in this embodiment.
In summary, the method for predicting a fault provided in this embodiment further includes: analyzing and obtaining the erasing interval time of the target memory chip within a preset time period based on the erasing time of the target memory chip; judging whether the erasing interval time of the target storage chip in the preset time period meets a preset fixed period condition or not to obtain a third judgment result; representing that the erasing interval time of the target memory chip in the preset time period meets a preset fixed period condition based on the third judgment result, and judging that the erasing information meets a preset fault condition; representing that the erasing interval time of the target memory chip in the preset time period does not meet a preset fixed period condition based on the third judgment result, judging whether the times are greater than a preset second time threshold value or not, and obtaining a fourth judgment result, wherein the second time threshold value is greater than the first time threshold value; representing that the times are greater than a preset second time threshold value based on a fourth judgment result, and judging whether the average period is smaller than a preset second period threshold value or not to obtain a fifth judgment result, wherein the second period threshold value is greater than the first period threshold value; and representing that the average period is smaller than a preset second period threshold value based on the fifth judgment result, and judging that the erasing information meets a preset fault condition. In the scheme, whether the erasure of the target storage chip is caused by the software design bug or the flash test is determined according to whether the erasure of the target storage chip in the preset time period is the erasure of the fixed period, and an alarm is given when a large amount of erasures caused by the software bug design are erased; when a large amount of erasures are caused by the flash test, when the erasing times are larger than the second time threshold value and the average period is smaller than the second time period threshold value, alarming is carried out, a large amount of erasures caused by different reasons are judged, different modes are adopted for processing, and the accuracy of fault prediction is improved.
As shown in fig. 5, a flowchart of embodiment 5 of a failure prediction method provided in the present application is provided, where the method includes the following steps:
step S501: monitoring the target memory chip, and recording the time and the times of erasing;
step S501 is the same as step S101 in embodiment 1, and details are not described in this embodiment.
Step S502: generating alarm information based on the time and the times of erasing meeting the preset fault condition;
when the time and the times of erasing meet preset fault conditions, alarm information is generated to give an alarm prompt.
The alarm information may only include an alarm instruction, or may preset a corresponding relationship between the alarm information and the determination condition.
For example, the memory chip is frequently erased in a fixed period within a preset time period to determine that the erasure information meets the fault condition, and first warning information is generated to realize that the follow-up prompt is the fault caused by the software setting error.
For example, the memory chip is frequently erased in an unfixed period within a preset time period to determine that the erasure information meets the fault condition, and second alarm information is generated to realize that the follow-up prompt is a fault caused by the flash test.
The method for prompting by the substrate control manager is adopted in the application.
Step S503: and sending the alarm information to a substrate management controller so that the substrate management controller adds the alarm information in webpage configuration information to alarm on the webpage.
The baseboard management controller is correspondingly provided with a web page (web) interface, and relevant information on the baseboard can be displayed in the web page.
After the alarm information is sent to the baseboard management controller, the baseboard management controller responds to the alarm information, and the alarm information is added to the configuration information of the webpage page, so that alarm content is displayed on the webpage page.
And when the alarm information is an alarm instruction, prompting an alarm on a webpage based on the alarm instruction.
For example, a page of a web page displays that "the memory chip is frequently erased, the system has a fault hidden trouble, and shutdown and power off are recommended".
When the alarm information is the first alarm information or the second alarm information, the alarm prompted on the webpage based on the alarm information may carry an alarm generation reason.
For another example, when it is determined that the warning information is generated when a large amount of erasure is caused by the flash test, the generated warning information includes corresponding information, and a page of the baseboard management controller displays that "the flash test causes frequent erasure of the memory chip, the system has a hidden trouble, and shutdown and power off are recommended".
Therefore, a user of the electronic equipment can see the content displayed in the webpage, shut down and power off can be prompted according to the content, the target memory chip is stopped from being continuously erased and written, and the purpose of protecting the target memory chip is achieved. The technical engineer may also be contacted to further identify and remove the fault potential.
It should be noted that, in the present application, the web page may prompt that the system has a fault, and the specific prompt content may be selected according to an actual situation, and is not limited to the example in this embodiment.
In summary, in the failure prediction method provided in this embodiment, the generating of the warning information to warn that the target memory chip is in a dangerous state includes: and generating alarm information, and sending the alarm information to a substrate management controller, so that the substrate management controller adds the alarm information in webpage configuration information, and alarms on the webpage. According to the scheme, the alarm information is displayed on the webpage of the substrate management controller, so that a user can know that the current target storage chip is in a dangerous state based on the webpage display content, and corresponding measures are taken for protection.
As shown in fig. 6, a flowchart of embodiment 6 of a failure prediction method provided by the present application includes the following steps:
step S601: monitoring the target memory chip, and recording the time and the times of erasing;
step S601 is the same as step S101 in embodiment 1, and details are not described in this embodiment.
Step S602: generating alarm information based on the time and the times of erasing meeting the preset fault condition;
when the time and the times of erasing meet preset fault conditions, alarm information is generated to give an alarm prompt.
In the application, an operating system is adopted for prompting.
The alarm information may only include an alarm instruction, or may preset a corresponding relationship between the alarm information and the determination condition.
For example, the memory chip is frequently erased in a fixed period within a preset time period to determine that the erasure information meets the fault condition, and first warning information is generated to realize that the follow-up prompt is the fault caused by the software setting error.
For example, the memory chip is frequently erased in an unfixed period within a preset time period to determine that the erasure information meets the fault condition, and second alarm information is generated to realize that the follow-up prompt is a fault caused by the flash test.
Step S603: and sending the alarm information to an operating system so that the operating system outputs display content in a display screen by configuring extensible firmware interface parameters, wherein the display content is used for early warning that the target storage chip is in a dangerous state.
And sending the alarm information of the target storage chip to a display screen by configuring the extensible firmware interface parameters in the operating system, so that the display screen outputs display contents based on the alarm information.
And when the alarm information is an alarm instruction, prompting an alarm on a display screen based on the alarm instruction.
For example, a display screen displays that 'the memory chip is frequently erased, the system has a fault hidden trouble, and shutdown and power off are recommended'.
When the alarm information is the first alarm information or the second alarm information, the alarm prompted on the display screen based on the alarm information may carry an alarm generation reason.
For another example, when it is determined that the warning information is generated when a large amount of erasure is caused by the flash test, the generated warning information includes corresponding information, and "the flash test causes frequent erasure of the memory chip, the system has a fault hidden trouble, and shutdown and power off are recommended" is displayed in the display screen.
Therefore, a user of the electronic equipment can see the content displayed in the display screen, shutdown and power off can be prompted according to the content, the target memory chip is stopped from being continuously erased and written, and the purpose of protecting the target memory chip is achieved. The technical engineer may also be contacted to further identify and remove the fault potential.
It should be noted that, in the present application, the display screen is used to prompt that the system has a fault, and the specific prompt content may be selected according to the actual situation, and is not limited to the example in this embodiment.
In summary, in the failure prediction method provided in this embodiment, the generating of the warning information to warn that the target memory chip is in a dangerous state includes: and generating alarm information and sending the alarm information to an operating system so that the operating system outputs display content in a display screen by configuring extensible firmware interface parameters, wherein the display content is used for early warning that the target storage chip is in a dangerous state. According to the scheme, the alarm information is displayed on the webpage of the substrate management controller, so that a user can know that the current target storage chip is in a dangerous state based on the webpage display content, and corresponding measures are taken for protection.
Corresponding to the embodiment of the fault prediction method provided by the application, the application also provides an embodiment of a device applying the fault prediction method.
Fig. 7 is a schematic structural diagram of an embodiment 1 of a failure prediction apparatus provided by the present application, where the apparatus includes the following structures: a monitoring module 701 and an early warning module 702;
the monitoring module 701 is configured to monitor the target memory chip, and record the time and the number of times of erasing;
the early warning module 702 is configured to generate warning information based on that the time and the number of times of occurrence of erasing meet a preset fault condition, so as to early warn that the target memory chip is in a dangerous state.
Optionally, the early warning module is specifically configured to:
and generating alarm information, and sending the alarm information to a substrate management controller, so that the substrate management controller adds the alarm information in webpage configuration information, and the alarm information is displayed on the webpage.
Optionally, the early warning module is specifically configured to:
and generating alarm information and sending the alarm information to an operating system so that the operating system outputs display content in a display screen by configuring extensible firmware interface parameters, wherein the display content is used for early warning that the target storage chip is in a dangerous state.
The functions of each component structure of the fault prediction apparatus refer to the explanation of the method embodiment, which is not described in detail in this embodiment.
In summary, according to the failure prediction apparatus provided in this embodiment, the situation of the target memory chip is grasped by detecting the time and the number of times of occurrence of each erasure of the target memory chip in real time, and when the time and the number of times of occurrence of the erasure meet the preset failure condition, an alarm message is generated to warn the user that the target memory chip is in a dangerous state, so that the user performs an operation based on the warning, and if the power supply is turned off, the target memory chip is stopped from being erased continuously, thereby achieving the purpose of protecting the target memory chip.
Fig. 8 is a schematic structural diagram of an embodiment 2 of an electronic device provided in the present application, where the electronic device includes the following structure: a monitoring module 801, an analysis module 802 and an early warning module 803;
the structural functions of the monitoring module 801 and the early warning module 803 are the same as those of the corresponding structure in embodiment 1, and are not described in detail in this embodiment.
The analysis module 802 is configured to analyze, based on the time and the number of times that the target memory chip is erased, an average cycle of the target memory chip within a preset time period, where the preset time period includes at least two average cycles; judging whether the times and the average period meet preset fault conditions or not; and judging that the erasing information meets the preset fault condition based on the number of times and the average period meeting the preset fault condition.
Optionally, the analysis module is configured to:
judging whether the times are larger than a preset first time threshold value or not to obtain a first judgment result;
representing that the times are greater than a preset first time threshold value based on a first judgment result, and judging whether the average period is less than a preset first period threshold value to obtain a second judgment result;
and representing that the average period is smaller than a preset first period threshold value based on the second judgment result, and judging that the erasing information meets a preset fault condition.
Optionally, the preset number threshold includes at least two number thresholds, and the preset cycle threshold includes at least two cycle thresholds;
wherein, optionally, the analysis module is further configured to:
analyzing and obtaining the erasing interval time of the target memory chip within a preset time period based on the erasing time of the target memory chip;
judging whether the erasing interval time of the target storage chip in the preset time period meets a preset fixed period condition or not to obtain a third judgment result;
representing that the erasing interval time of the target memory chip in the preset time period meets a preset fixed period condition based on the third judgment result, and judging that the erasing information meets a preset fault condition;
representing that the erasing interval time of the target memory chip in the preset time period does not meet a preset fixed period condition based on the third judgment result, judging whether the times are greater than a preset second time threshold value or not, and obtaining a fourth judgment result, wherein the second time threshold value is greater than the first time threshold value;
representing that the times are greater than a preset second time threshold value based on a fourth judgment result, and judging whether the average period is smaller than a preset second period threshold value or not to obtain a fifth judgment result, wherein the second period threshold value is greater than the first period threshold value;
and representing that the average period is smaller than a preset second period threshold value based on the fifth judgment result, and judging that the erasing information meets a preset fault condition.
It should be noted that, in a specific implementation, the function of the analysis module may be implemented by a register and a logic gate, where the register counts information such as times and periods, and determines whether the judgment condition is satisfied by determining whether the judgment of the logic gate exceeds a preset threshold.
The functions of each component structure of the fault prediction apparatus refer to the explanation of the method embodiment, which is not described in detail in this embodiment.
In summary, the failure prediction apparatus provided in this embodiment determines whether a failure occurs based on the number of times of erasing within a period of time and the average period of erasing within the period of time, and can determine that the failure occurs only by performing simple calculation, so that the data processing amount is small.
Corresponding to the embodiment of the fault prediction method provided by the application, the application also provides the electronic equipment and the readable storage medium corresponding to the fault prediction method.
Wherein, this electronic equipment includes: a memory, a processor;
wherein, the memory stores a processing program;
the processor is configured to load and execute the processing program stored in the memory to implement the steps of the failure prediction method according to any one of the above.
Wherein, the memory stores a processing program;
the processor is configured to load and execute the processing program stored in the memory to implement the steps of the failure prediction method according to any one of the above.
Specifically, the method for realizing the fault prediction of the electronic device may be implemented by referring to the embodiment of the fault prediction method.
Wherein the readable storage medium has stored thereon a computer program which is called up and executed by a processor for implementing the steps of the failure prediction method according to any one of the preceding claims.
Specifically, the computer program stored in the readable storage medium executes the fault prediction method, and reference may be made to the foregoing fault prediction method embodiments.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the device provided by the embodiment, the description is relatively simple because the device corresponds to the method provided by the embodiment, and the relevant points can be referred to the method part for description.
The previous description of the provided embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features provided herein.
Claims (10)
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114697203A (en) * | 2022-03-31 | 2022-07-01 | 浙江省通信产业服务有限公司 | Network fault pre-judging method and device, electronic equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7356442B1 (en) * | 2006-10-05 | 2008-04-08 | International Business Machines Corporation | End of life prediction of flash memory |
| CN101752008A (en) * | 2008-12-05 | 2010-06-23 | 财团法人工业技术研究院 | Method for testing reliability of solid storage medium |
| CN105183386A (en) * | 2015-09-14 | 2015-12-23 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN108766496A (en) * | 2018-05-23 | 2018-11-06 | 武汉忆数存储技术有限公司 | A kind of method and device in online dynamic prediction flash chip service life |
| CN109584939A (en) * | 2018-11-30 | 2019-04-05 | 华立科技股份有限公司 | The method for avoiding nonvolatile storage excessively erasable |
-
2021
- 2021-09-03 CN CN202111033395.1A patent/CN113742176B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7356442B1 (en) * | 2006-10-05 | 2008-04-08 | International Business Machines Corporation | End of life prediction of flash memory |
| CN101752008A (en) * | 2008-12-05 | 2010-06-23 | 财团法人工业技术研究院 | Method for testing reliability of solid storage medium |
| CN105183386A (en) * | 2015-09-14 | 2015-12-23 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN108766496A (en) * | 2018-05-23 | 2018-11-06 | 武汉忆数存储技术有限公司 | A kind of method and device in online dynamic prediction flash chip service life |
| CN109584939A (en) * | 2018-11-30 | 2019-04-05 | 华立科技股份有限公司 | The method for avoiding nonvolatile storage excessively erasable |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114697203A (en) * | 2022-03-31 | 2022-07-01 | 浙江省通信产业服务有限公司 | Network fault pre-judging method and device, electronic equipment and storage medium |
| CN114697203B (en) * | 2022-03-31 | 2023-07-25 | 浙江省通信产业服务有限公司 | Network fault pre-judging method and device, electronic equipment and storage medium |
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