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CN113725169B - 倒装芯片封装单元及相关封装方法 - Google Patents

倒装芯片封装单元及相关封装方法 Download PDF

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Publication number
CN113725169B
CN113725169B CN202110435460.7A CN202110435460A CN113725169B CN 113725169 B CN113725169 B CN 113725169B CN 202110435460 A CN202110435460 A CN 202110435460A CN 113725169 B CN113725169 B CN 113725169B
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China
Prior art keywords
integrated circuit
wafer
chip
film layer
flip
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CN202110435460.7A
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CN113725169A (zh
Inventor
蒲应江
蒋航
郭秀宏
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Priority to CN202110435460.7A priority Critical patent/CN113725169B/zh
Priority to CN202410765710.7A priority patent/CN118712146A/zh
Publication of CN113725169A publication Critical patent/CN113725169A/zh
Priority to US17/712,323 priority patent/US12266583B2/en
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Publication of CN113725169B publication Critical patent/CN113725169B/zh
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Abstract

提出了一种倒装芯片封装单元及制作倒装芯片封装单元的封装方法。该倒装芯片封装单元可以包括：集成电路晶片，具有晶片第一表面和与该晶片第一表面相对的晶片第二表面，该晶片第一表面上制作有多个金属柱；绕线基板，其具有基板第一表面和与该基板第一表面相对的基板第二表面，所述集成电路晶片的晶片第一表面朝向该基板第二表面焊接于该绕线基板上；底部填充材料，填充该集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙；以及背面保护膜，直接黏贴于该集成电路晶片的晶片第二表面，该背面保护膜包括一层或多层粘合剂薄膜，其可以与晶片背面贴合良好、经UV光照固化后不易变型、不易脱落，同时兼顾晶片背面保护和晶片散热需求。

Description

倒装芯片封装单元及相关封装方法
技术领域
本公开的实施例涉及集成电路，特别地，涉及用于倒装芯片的封装结构及封装方法。
背景技术
将制作有集成电路的晶片进行倒装封装是集成电路封装方式的一种。对于需要处理较大功率的集成电路晶片，散热性能是需要重点考虑的一个设计指标。目前将集成电路晶片进行倒装封装时，采用将晶片用塑封材料包裹后再将晶片背面的塑封材料去除以将晶片背面裸露的方式以改善散热效果，然而晶片背面裸露则在储存或运输过程中受损的风险增加。
发明内容
本公开一方面提出了一种集成电路芯片(IC)封装结构，可以包括：集成电路晶片，具有晶片第一表面和与该晶片第一表面相对的晶片第二表面，该晶片第一表面上制作有多个金属柱；绕线基板，其具有基板第一表面和与该基板第一表面相对的基板第二表面，所述集成电路晶片的晶片第一表面朝向该基板第二表面焊接于该绕线基板上；底部填充材料，填充该集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙；以及背面保护膜，直接黏贴于该集成电路晶片的晶片第二表面，该背面保护膜包括一层或多层粘合剂薄膜。
本公开另一方面提出了一种制作倒装芯片封装单元的封装方法，可以包括：步骤S1，提供至少包括胶带基层和粘合膜层的粘合胶带，其中所述粘合膜层具有粘合层第一表面和与该粘合层第一表面相对的粘合层第二表面，并且包括一层或多层粘合剂薄膜；步骤S2，在所述胶带基层上安装中空的支撑框架，使所述粘合膜层被框于支撑框架的中空部分之中；步骤S3，将制作有多个集成电路单元的晶圆安装于所述粘合膜层的粘合层第二表面上，使该晶圆的背面与所述粘合层第二表面粘合，其中该晶圆的正面上针对每个集成电路单元制作有多个金属柱；步骤S4，对所述晶圆行切割，从晶圆的正面沿各集成电路单元的预设好的边界纵向切割直至切入所述胶带基层一设定深度，使各集成电路单元分离，形成多个相互分立的倒装集成电路晶片，每个倒装集成电路晶片的第一表面上制作有所述多个金属柱；步骤S5，透过所述胶带基层对所述粘合膜层进行紫外线(UV)照射；步骤S6，将每颗倒装集成电路晶片连同粘合于其晶片第二表面的粘合膜层摘起，制得分立的倒装集成电路晶片，所述粘合膜层用作每个倒装集成电路晶片的背面保护膜层。
根据本公开的一个实施例该封装方法可以进一步包括：步骤S7，提供绕线基板，其具有基板第一表面和与该基板第一表面相对的第二表面,将每个倒装集成电路晶片的晶片第一表面朝向所述基板第二表面焊接于该绕线基板上，相邻的两个倒装集成电路晶片之间间隔第一横向距离；步骤S8，在每个倒装集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙注入底部填充材料形成每个倒装集成电路晶片的底部填充材料；以及步骤S9，采用切割工艺将步骤S8之后制得的封装结构分割成多个独立的倒装芯片封装单元，每个倒装芯片封装单元中可以包括至少一个倒装集成电路晶片。
本公开的各实施例教示的芯片封装单元包括黏贴于倒装集成电路晶片背面的背面保护膜，其可以与晶片背面贴合良好、经UV光照固化后不易变型、不易脱落，同时兼顾晶片背面保护和晶片散热需求。
附图说明
下面的附图有助于更好地理解接下来对本公开实施例的描述。为简明起见，不同附图中相同或类似的组件或结构采用相同的附图标记。
图1示意出了根据本公开一实施例的倒装芯片封装单元100的局部纵向 (Z轴方向)剖面图。
图2A至2I示意出了根据本公开一实施例的制作倒装芯片封装单元的晶圆级封装方法中部分阶段的剖面流程示意图。
具体实施方式
在下面对本公开的详细描述中，为了更好地理解本公开的实施例，描述了大量的电路、元件、方法等的具体细节。本领域技术人员将理解，即使缺少一些细节，本公开同样可以实施。为清晰明了地阐述本公开，一些为本领域技术人员所熟知的细节在此不再赘述。
图1示意出了根据本公开一实施例的倒装芯片封装单元100的局部纵向 (Z轴方向)剖面图。图1可以看作是在相互垂直的X轴、Y轴和Z轴定义的垂直坐标系中示意出了该倒装芯片封装单元100在X-Y平面上的剖面图。如图1的示例，该倒装芯片封装单元100可以包括至少一个被封装于其中的集成电路晶片102，在图1示意的例子中的剖面图展现了包括一个集成电路晶片102。本领域的技术人员应该理解，在其它实施例中可以包括两个及以上的集成电路晶片102。不同实施例的封装结构100中所封装的集成电路芯晶片102的个数以及排布或堆叠方式可以不同，各集成电路晶片102的尺寸及所实现的电路功能可以相同也可以不同，根据各封装结构100所要实现的具体电路功能而定，本申请不做赘述。
每个集成电路晶片102可以包括制作有集成电路的衬底103。本领域的技术人员应该理解衬底103可以包括硅(Si)等半导体材料，锗硅(SiGe) 等化合物半导体材料，或者绝缘体上硅(SOI)等其他形式的衬底。集成电路晶片102具有第一表面，例如可以被提及为正面(图1中标记为102T)，和与该第一表面102T相对的第二表面，例如可以被提及为背面(图1中标记为102B)。该第一表面102T上制作有多个金属柱(例如铜柱)105，可以用于将制作于衬底103中的集成电路的节点/端子(有源区，例如晶体管的源极/发射极、漏极/吸收极、栅极/基极等)引出，以便于耦接至集成电路晶片102外部的电路。每个集成电路晶片102可以被提及为倒装晶片，其将以正面102T朝下的方式焊接于基板或PCB板上，通过所述多个金属柱105以及所述基板或PCB板与其它外部电路进行电气耦接或信号交换。
根据本公开的一个实施例，倒装芯片封装单元100可以进一步包括绕线基板107，具有第一表面107T和与该第一表面107T相对的第二表面107B, 可以将每个集成电路晶片102的第一表面102T朝向该绕线基板107的第二表面107B焊接于该绕线基板107上。例如每个集成电路晶片102的多个金属柱105可以通过焊接材料106焊接于绕线基板107的第二表面107B上。该绕线基板107可以包括一层或多层层间介电层和再布线金属层，本公开不做赘述。比如，参考1示意的例子，对应于每个集成电路晶片102该绕线基板107可以包括电连接至所述多个金属柱105的再布线金属层(例如第一再布线金属层1072)。再布线金属层可以包括，例如第一再布线金属层1072，穿过第一层间介电层1071与该多个金属柱105互相电气连接。在一些实施例中，再布线金属层还可以进一步包括例如第二再布线金属层1074，穿过第二层间介电层1073与所述第一再布线金属层1072相互电气连接。在一些实施例中，再布线金属层还可以进一步包括例如第三再布线金属层1076，与所述第二再布线层1074电气连接。本领域的技术人员应该理解，第一层间介电层 1071、第二层间介电层1073可以包含相同的介电材料，也可以包含不同的介电材料。
根据本公开的一个实施例，可以采用底部填充材料104填充每个集成电路晶片102的第一表面102T与绕线基板107之间的间隙。该底部填充材料 104可以采用流动性、填充性和稳定性比传统塑封材料(例如：环氧树脂模塑料等)高的绝缘材料，例如NAMICS 8410-302、LOCTITE ECCOBOND UF 8830S等。在一个实施例中，该底部填充材料104仅填充集成电路晶片102 的第一表面102T上的多个金属柱(例如铜柱)105(包括相应焊料106)之间的空隙以起到保护该多个金属柱105的作用。在一个实施例中，该底部填充材料104进一步纵向爬升至包裹每个集成电路晶片102的侧面102S的一部分。纵向指平行于Y轴的方向。因此，集成电路晶片102的侧面102S的大部分及其第二表面102B均未受该底部填充材料104包裹/覆盖，从而有助于更好地散热。在一个实施例中底部填充材料104自集成电路晶片102的两个侧面102S双侧地向外呈梯形状突出，底部填充材料104的侧壁104S与集成电路晶片102的侧面102S相交形成一角度α。在一个实施例中该角度α大于0度且小于90度。在一个实施例中该角度α大于0度且小于45度。在一个实施例中该角度α大于0度且小于等于30度。这样底部填充材料104不仅可以更好地起到保护该多个金属柱105的作用，而且可以更好地抓持、固定集成电路晶片102。
根据本公开的一个实施例，可以在裸露的集成电路晶片102的第二表面 102B上贴附背面保护膜101。该背面保护膜101可以包括一层或多层可延展性、黏性和UV敏感性较好的粘合剂薄膜，该背面保护膜101的第一表面S1 与集成电路晶片102的第二表面102B直接接触并粘合。该背面保护膜101 主要用于对集成电路晶片102的背面102B进行物理保护、防损伤、防静电、隔潮等等，避免其在后面的芯片测试，芯片抓取，以及SMT上PCB板过程中遭受损伤。该背面保护膜101的与其第一表面S1相对的第二表面S2上不再制作任何其它材料层。根据本公开的一个实施例，UV敏感性指该背面保护膜101在UV光照前后会发生特性变更，比如：从非固态变为固态、与晶片102之间的黏性不降低，且这一变化不可逆。根据本公开的一个实施例，该背面保护膜101的厚度T1小于100μm，例如在一个实施例中T1可以在 20μm到100μm的范围。在一个实施例中，该背面保护膜101的厚度T1可以在25μm到80μm的范围。在一个实施例中，该背面保护膜101的厚度T1可以在25μm到50μm的范围。根据本公开的一个实施例，该背面保护膜的导热率可以在0.5W/(m·K)到10W/(m·K)的范围。在一个实施例中，该背面保护膜101的导热率可以在0.5W(m·K)到2W/(m·K)的范围。该背面保护膜101具有热膨胀系数(CTE)、收缩率、弹性模量等特性参数与集成电路晶片102的第二表面102B的材质相匹配的特性。所谓相匹配可以指经过UV 光照、烘烤等等后续工艺步骤后该背面保护膜101与集成电路晶片102之间的收缩、形变等引起的翘曲在应用允许的范围内。在图1的例子中集成电路晶片102的第二表面102B的材质事实上也就是该集成电路晶片102的衬底 103的材质(比如硅(Si)等半导体材料，锗硅(SiGe)等化合物半导体材料)。根据本公开的一个实施例，该背面保护膜101的热膨胀系数(CTE) 可以是5-200的范围，在一个例子中其CTE可以是34。根据本公开的一个实施例，该背面保护膜101的收缩率可以在0.1％-0.6％的范围，在一个例子中其收缩率可以为0.28％。该背面保护膜101还具有不易吸潮的特性，其潮湿敏感等级为一级。该背面保护膜101可以采用任何合适地能够满足上述特性且可以保护集成电路晶片102的背面102B的粘合剂薄膜，其可以与晶片背面102B贴合良好、经UV光照固化后不易变型、不易脱落。诸如传统用于将非倒装晶片黏贴于基板或PCB板的粘合剂中满足以上特性需求的粘合剂薄膜均可用作本公开各实施例所提及的倒装集成电路晶片102的所述背面保护膜101。非倒装晶片指晶片正面制作有集成电路有源区(例如晶体管的源极/发射极、漏极/吸收极、栅极/基极等)、晶片正面朝上背面朝下粘合于基板或PCB板上、采用金属键合线(bonding wire)将集成电路有源区连接至基板或PCB板的晶片。
根据本公开的一个实施例该背面保护膜101可以采用预制好的粘合胶带 (tapeadhesive)201，诸如目前市场上可购买的Lintec Corporation公司生产的AdwillLC2824H、日本Nitto公司生产的wafer protection film WP-571E-P等等。这类粘合胶带通常可以包括胶带基层(tape base layer)和粘合膜层 (adhesive film)。将该粘合胶带的粘合膜层直接贴附于集成电路晶片102 的第二表面102B上并在后续工艺步骤中将所述胶带基层与所述粘合膜层分离，然后“撕掉”所述胶带基层，则所述粘合膜层留下来作为所述背面保护膜 101贴附于集成电路晶片102的背面102B上。因而，该背面保护膜101不同于传统的塑封材料(molding compound,例如：环氧树脂模塑料等)或者银胶 (epoxy)，其厚度T1小于100μm，可以同时兼顾晶片背面保护和晶片散热需求。相反，传统塑封材料需要采用压力整体包封(over molding)的工艺，因而会将集成电路晶片102的背面102B和四周全部包裹填充起来，而且其韧性差，覆盖于晶片102背面102B上的厚度通常需要大于100μm(通常若小于100μm则极大可能会产生塑封材料开裂、进而导致晶片开裂等质量与可靠性问题)，因而导致晶片102散热性能较差而无法满足应用需求。正如背景技术部分所提及，要满足较大功率的集成电路晶片对散热性能的需求，则需要去除晶片背面的塑封材料而导致晶片背面容易受损，工艺成本增加不说，很难同时兼顾可靠性、晶片保护和散热等需求。
图2A至2I示意出了根据本公开一实施例的制作倒装芯片封装单元(例如以上根据图1所描述各实施例提及的倒装芯片封装单元100)的晶圆级封装方法中部分阶段的剖面流程示意图。
参考图2A的示意，在步骤S1，提供粘合胶带(tape adhesive)201。在 2A的例子中示意为该粘合胶带201包括胶带基层(tape base layer)101B、粘合膜层101和胶带覆层101A，其通常是成卷销售的。胶带基层101B通常也可以称为胶带承载层，其具有基层第一表面B1和与该基层第一表面B1相对的基层第二表面B2，主要用于在后续切割工艺步骤中提供支撑作用。根据本公开的一个实施例该胶带基层101B具有较强的UV透光性(即：UV光可以穿过该胶带基层101B)，其厚度T2在50μm到300μm的范围(例如在一个例子中其厚度为100μm)。该胶带基层101B还具有较好的柔韧性，其被半切割(所谓半切割指如图2D步骤所描述的切入该胶带基层101B的深度h小于其厚度T2)后不会漏水且具有较强的承载能力。所述粘合膜层101 具有粘合层第一表面S1和与该粘合层第一表面S1相对的粘合层第二表面 S2，该粘合膜层101制作于所述胶带基层101B的基层第二表面B2上，其粘合层第一表面S1与所述基层第二表面B2贴合。该粘合膜层101具有较好的可延展性、黏性和UV敏感性，其可以包括一层或多层粘合剂薄膜，其热膨胀系数CTE、收缩率、弹性模量等特性参数与步骤S3中晶圆203的背面材质(比如硅(Si)等半导体材料，锗硅(SiGe)等化合物半导体材料)相匹配，其在UV光照前后会发生特性变更，比如：在UV光照后从非固态变为固态、与晶圆203之间的黏性不会降低、但与所述胶带基层101B之间的黏性快速减弱等，且这一变化不可逆。所谓相匹配可以指经过UV光照、烘烤等等后续工艺步骤后该粘合膜层101与晶圆203之间的收缩、形变等引起的翘曲在应用允许的范围内。根据本公开的一个实施例，该粘合膜层101的导热率可以在0.5W/(m·K)到10W/(m·K)的范围。在一个实施例中，该该粘合膜层101的导热率可以在0.5(m·K)到2W/(m·K)的范围。在一个实施例中，该粘合膜层101的热膨胀系数CTE可以是5-200的范围,在一个例子中其CTE可以是34，其收缩率可以在0.1％-0.6％的范围,在一个例子中其收缩率可以为0.28％。在一个实施例中，该粘合膜层101还具有不易吸潮的特性，其潮湿敏感等级为一级。根据本公开的一个实施例，该粘合膜层101的厚度 T1小于100μm，例如在一个实施例中T1可以在20μm到100μm的范围。在一个实施例中，该粘合膜层101的厚度T1可以在25μm到80μm的范围。在一个实施例中，该粘合膜层101的厚度T1可以在25μm到50μm的范围。所述胶带覆层101A是可选层，具有UV光阻挡性，主要用于对所述粘合膜层101进行保护比如防止其受损、被污染、储存过程中被UV光照等等，并且用于在该粘合胶带201被卷成卷时起到将所述胶带基层101B的基层第一表面B1和粘合膜层101的粘合层第二表面S2隔离开的作用，以便成卷的粘合胶带(tape adhesive)201在使用时容易展开，且在展开过程中所述胶带基层101B的基层第一表面B1和所述粘合膜层101的粘合层第二表面S2不会黏连撕不开。
接下来参考图2B的示意，在步骤S2，将所述胶带覆层101A去除(在所述粘合胶带不包括该胶带覆层101A的实施例中无需做去除胶带覆层的步骤)，并安装支撑框架202在胶带基层101B上。该支撑框架202是中空的，由于图2B示意的为X-Y平面上的剖面图，因而左右两边示意出了框架的切面部分。本领域的技术人员可以理解，该支撑框架202在X-Z平面上的视图可以是矩形或多边形或圆形等几何形状的中空环。粘合膜层101被框于支撑框架202的中空部分之中。
接下来参考图2C，在步骤S3，将制作有多个集成电路单元102的晶圆 203安装于所述粘合膜层101的粘合层第二表面S2上，使该晶圆203的背面 203B与所述粘合层第二表面S2粘合。例如，可以在温度为50℃至90℃(或者65℃至75℃)的范围内以大约0.3MPa的压力、10mm/s-50mm/s的速度来粘合。本领域的技术人员应该理解，粘合膜层101的形状、大小可以根据晶圆203的形状、大小、数量等合理预制，本申请不做限定。在图2A的例子中，以虚线示意出了各集成电路单元102之间的边界。在该晶圆203的正面 203T上针对每个集成电路单元102制作有多个金属柱(例如铜柱)105，该晶圆203的正面203T与其背面203B相对。通常还可以对安装好晶圆203的整体进行烘烤使粘合膜层101的粘合层第二表面S2与晶圆203的背面203B 更好地黏合在一起。烘烤温度范围可以在60℃至100℃(典型地可以选择75℃至100℃或者80℃)。烘烤时间可以在1小时到2小时的范围。
接下来参考图2D的示意，在步骤S4，对晶圆203进行切割，从晶圆203 的正面203T沿各集成电路单元102的预设好的边界纵向(沿Y轴平行的方向)切割直至切入所述胶带基层101B一设定深度h，将各集成电路单元102 相互分离，形成多个相互分立的集成电路晶片102，每个集成电路晶片102 的第一表面102T(也可以提及为晶片正面)上制作有所述多个金属柱(例如铜柱)105。每个集成电路晶片102可以包括倒装芯片/晶片。每个集成电路晶片102还具有与其第一表面102T相对的第二表面102B(也可以提及为晶片背面)。所述设定深度h小于所述胶带基层101B的厚度T2，即：h<T2。在一个实施例中，所述设定深度h可以是所述胶带基层厚度T2的1/3至1/2 的范围，即：T2/3≤h≤T2/2。
接下来参考图2E的示意，在步骤S5，从所述胶带基层101B的第一表面B1透过该胶带基层101B对所述粘合膜层101进行紫外线(UV)照射以使所述粘合膜层101固化并且与集成电路晶片102之间的黏性不变但与所述胶带基层101B之间的黏性快速降低。例如，可以采用50mJ/cm2-5000mJ/cm2的UV光源进行照射。在一个例子中，可以采用300mJ/cm2的UV光源进行照射。根据本公开的一个实施例，UV照射时长大约在30秒到5分钟的范围。在一个例子中，UV照射时长大约在1分钟到2分钟的范围。
接下来参考图2F，在步骤S6，经UV照射后所述粘合膜层101与集成电路晶片102之间的黏性不变黏合良好，但其与所述胶带基层101B之间的黏性快速降低、黏合减弱、易于分离，则可将每颗集成电路晶片102连同粘合于其晶片第二表面(背面)102B的粘合膜层101摘起(pick up)，至此制得分立的倒装集成电路晶片102。所述粘合膜层101便用作每个集成电路晶片102的所述背面保护膜层101，即：每个倒装集成电路晶片102的第二表面(背面)102B上具有背面保护膜层101，用于对集成电路晶片102的背面 102B进行物理保护、防损伤、防静电、隔潮等等，同时满足晶片散热需求。
接下来参考图2G，在步骤S7，提供绕线基板107，该绕线基板107具有基板第一表面107T和与该基板第一表面107T相对的基板第二表面107B, 将每个集成电路晶片102的第一表面102T朝向该绕线基板107的第二表面 107B焊接于该绕线基板107上。在一个实施例中，每相邻的两个集成电路晶片102之间间隔第一横向距离d1。横向指沿X轴方向的测量。该绕线基板 107可以是预制的，且针对每个集成电路晶片102制作有与每个集成电路单元102相对应的已构图的多层层间介电层(例如返回参考图1例子示意的第一层间介电层1071、第二层间介电层1073)和多层再布线金属层(例如返回图1例子示意的第一再布线金属层1072、第二再布线金属层1074、第三再布线层1076等)。图2C的例子中虽未出该绕线基板107的更多细节，然本领域的技术人员应该可以参考图1的示意进行理解。
以上步骤S6和步骤S7可以采用标准的摘起和安装设备(pick and placeequipment)例如倒装芯片焊接机(比如：datacom8800或者ESEC2100等等) 完成。
接下来参考图2H的示意，在步骤S8，在每个集成电路晶片102的第一表面102T与绕线基板107的第二表面107B之间的间隙注入底部填充材料 104形成每个集成电路晶片102的底部填充材料。在一个实施例中，该底部填充材料104仅填充每个集成电路晶片102的第一表面102T与绕线基板107 的第二表面107B之间的多个金属柱(例如铜柱)105(包括相应焊料)之间的空隙以起到保护该多个金属柱105的作用。在一个实施例中，注入底部填充材料的过程中使该底部填充材料104进一步纵向爬升至包裹每个集成电路晶片102的侧面102S的一部分。纵向指平行于Y轴的方向。在一个实施例中，每个集成电路晶片102的底部填充材料104自集成电路晶片102的两个侧面102S双侧地向外呈梯形状突出，每个集成电路晶片102的底部填充材料104的侧壁104S与该集成电路晶片102的侧面102S相交形成一角度α。在一个实施例中该角度α大于0度且小于90度。在一个实施例中该角度α大于0度且小于45度。在一个实施例中该角度α大于0度且小于等于30度。图2D以其中一个集成电路晶片102为例进行了示意。在一个实施例中，每个集成电路晶片102的底部填充材料104与与之相邻的集成电路晶片102的底部填充材料104之间间隔第二横向距离d2，该第二横向距离d2小于所述第一横向距离d1。该第二横向距离d2指沿与X轴方向平行的方向上测量两个相邻的底部填充材料104之间的最短距离。在一个实施例中，该第二横向距离d2在大于200μm小于等于5000μm的范围。在一个实施例中，该第二横向距离d2在大于200μm小于等于3000μm的范围。在一个实施例中，该第二横向距离d2在大于200μm小于等于1000μm的范围。在一个实施例中，所述第一横向距离d1与所述第二横向距离d2的差值(d1-d2)在大于200μ m小于等于1000μm的范围。
接下来参考图2I的示意，在步骤S9，采用切割工艺将图2H示意的封装结构分割成多个独立的倒装芯片封装单元100。每个倒装芯片封装单元100 中可以包括至少一个集成电路晶片102，其更详细的结构描述可以参见图1 各实施例的描述。本领域的技术人员应该理解在以上步骤S1～S9任两个步骤之间还可以根据制作工艺流程所需包括其它工艺步骤，本申请并不赘述。
本公开提供一种倒装芯片封装单元及相关的晶圆级封装方法，虽然详细介绍了本公开的一些实施例，然而应该理解，这些实施例仅用于示例性的说明，并不用于限定本公开的范围。其它可行的选择性实施例可以通过阅读本公开被本技术领域的普通技术人员所了解。

Claims (19)

1.一种制作倒装芯片封装单元的封装方法，包括：
步骤S1，提供至少包括胶带基层和粘合膜层的粘合胶带，其中所述粘合膜层具有粘合层第一表面和与该粘合层第一表面相对的粘合层第二表面，并且包括一层粘合剂薄膜，其具有可延展性、黏性和UV敏感性，并且不同于塑封材料或环氧树脂；
步骤S2，在所述胶带基层上安装中空的支撑框架，使所述粘合膜层被框于支撑框架的中空部分之中；
步骤S3，将制作有多个集成电路单元的晶圆安装于所述粘合膜层的粘合层第二表面上，使该晶圆的背面与所述粘合层第二表面粘合，其中该晶圆的正面上针对每个集成电路单元制作有多个金属柱；
步骤S4，对所述晶圆行切割，从晶圆的正面沿各集成电路单元的预设好的边界纵向切割直至切入所述胶带基层一设定深度，使各集成电路单元分离，形成多个相互分立的倒装集成电路晶片，每个倒装集成电路晶片的第一表面上制作有所述多个金属柱；
步骤S5，透过所述胶带基层对所述粘合膜层进行紫外线(UV)照射；
步骤S6，将每颗倒装集成电路晶片连同粘合于其晶片第二表面的粘合膜层摘起，制得分立的倒装集成电路晶片，所述粘合膜层用作每个倒装集成电路晶片的背面保护膜层，该背面保护膜层上不再制作任何其它材料层、且不用于将该集成电路晶片粘结于基板或PCB板；
步骤S7，提供绕线基板，其具有基板第一表面和与该基板第一表面相对的第二表面,将每个倒装集成电路晶片的晶片第一表面朝向所述基板第二表面焊接于该绕线基板上，相邻的两个倒装集成电路晶片之间间隔第一横向距离；
步骤S8，在每个倒装集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙注入底部填充材料形成每个倒装集成电路晶片的底部填充材料；以及
步骤S9，采用切割工艺将步骤S8之后制得的封装结构分割成多个独立的倒装芯片封装单元，每个倒装芯片封装单元中包括至少一个倒装集成电路晶片。
2.如权利要求1所述的封装方法，其中所述UV敏感性指该粘合膜层在UV光照射前后发生特性变更，所述特性变更至少包括该粘合膜层从非固态变为固态且与所述集成电路晶片之间的黏性不变但与所述胶带基层之间的黏性快速降低。
3.如权利要求1所述的封装方法，其中所述粘合膜层的热膨胀系数、收缩率和弹性模量与所述晶圆的背面材质相匹配。
4.如权利要求1所述的封装方法，其中所述粘合膜层的热膨胀系数在5-200的范围。
5.如权利要求2所述的封装方法，其中所述粘合膜层的收缩率在0.1％-0.6％的范围。
6.如权利要求1所述的封装方法，其中所述粘合膜层的厚度在20μm到100μm的范围。
7.如权利要求1所述的封装方法，其中所述粘合膜层的厚度在25μm到80μm的范围。
8.如权利要求1所述的封装方法，其中所述粘合膜层的厚度在25μm到50μm的范围。
9.如权利要求1所述的封装方法，其中所述粘合膜层的导热率在0.5W/(m·K)到10W/(m·K)的范围。
10.如权利要求1所述的封装方法，其中所述粘合膜层的导热率在0.5W/(m·K)到2W/(m·K)的范围。
11.如权利要求1所述的封装方法，其中在步骤S3，使所述粘合层第二表面与所述晶圆的背面在温度为50℃至90℃的范围内以0.3MPa的压力、10mm/s-50mm/s的速度来粘合。
12.如权利要求1所述的封装方法，其中在步骤S3，安装好晶圆后进一步在60℃至100℃的温度范围烘烤1小时到2小时。
13.如权利要求1所述的封装方法，其中所述设定深度小于所述胶带基层的厚度。
14.如权利要求1所述的封装方法，其中所述设定深度大于等于所述胶带基层厚度的1/3且小于等于所述胶带基层厚度的1/2。
15.如权利要求1所述的封装方法，其中在步骤S5，采用50mJ/cm2-5000mJ/cm2的UV光源进行照射，照射时长为30秒到5分钟的范围。
16.如权利要求1所述的封装方法，其中在步骤S8使每个倒装集成电路晶片的底部填充材料进一步纵向爬升至包裹每个倒装集成电路晶片的侧面的一部分。
17.如权利要求16所述的封装方法，其中每个倒装集成电路晶片的底部填充材料的侧壁与该倒装集成电路晶片的晶片侧面相交形成一角度。
18.如权利要求17所述的封装方法，其中所述角度大于0度且小于45度。
19.如权利要求17所述的封装方法，其中所述角度大于0度且小于等于30度。
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