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CN113725095B - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN113725095B
CN113725095B CN202010230903.4A CN202010230903A CN113725095B CN 113725095 B CN113725095 B CN 113725095B CN 202010230903 A CN202010230903 A CN 202010230903A CN 113725095 B CN113725095 B CN 113725095B
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die
packaged
protection layer
protective layer
layer
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CN113725095A (en
Inventor
周辉星
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to CN202010230903.4A priority Critical patent/CN113725095B/en
Priority to PCT/CN2020/134322 priority patent/WO2021189942A1/en
Publication of CN113725095A publication Critical patent/CN113725095A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: forming a first protection layer on the front surface of the first die to be packaged; forming a second protection layer on the front surface of the second bare chip to be packaged, and laminating and fixing the first bare chip to be packaged, the front surface of which is provided with the first protection layer, on the front surface of the second bare chip to be packaged through the second protection layer, wherein the surface of the second protection layer, which is far away from the second bare chip to be packaged, is flush with the surface of the first protection layer, which is far away from the first bare chip to be packaged; mounting the stacked first die to be packaged and the stacked second die to be packaged on a carrier plate, wherein the back surfaces of the first die to be packaged and the second die to be packaged are upward, and the front surfaces of the first die to be packaged and the second die to be packaged are toward the carrier plate; and forming an encapsulation layer, wherein the encapsulation layer is formed on the back surface of the second die to be encapsulated and the exposed carrier plate. The semiconductor packaging structure has the advantages of small volume and compact structure, and is suitable for small-sized light-weight electronic equipment.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor packaging method and a semiconductor packaging structure.
Background
Currently, in the packaging process, dies having different functions are often packaged in a package structure to form a specific function, which is called MCM (multi-chip module, chinese name). The MCM has the advantages of small volume, high reliability, high performance, multifunction and the like.
With miniaturization and weight reduction of electronic devices, chip packages having a compact structure and a small volume are increasingly favored in the market.
However, how to further reduce the volume of the chip package is a problem to be solved in the art.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, including:
forming a first protection layer on the front surface of the first die to be packaged;
Forming a second protection layer on the front surface of a second bare chip to be packaged, and laminating and fixing the first bare chip to be packaged, the front surface of which is provided with the first protection layer, on the front surface of the second bare chip to be packaged through the second protection layer, wherein one surface of the second protection layer, which is far away from the second bare chip to be packaged, is flush with one surface of the first protection layer, which is far away from the first bare chip to be packaged;
attaching the stacked first die to be packaged and the second die to be packaged on a carrier plate, wherein the back surfaces of the first die to be packaged and the second die to be packaged are upward, and the front surfaces of the first die to be packaged and the second die to be packaged are towards the carrier plate;
And forming an encapsulation layer, wherein the encapsulation layer is formed on the back surface of the second die to be encapsulated and the exposed carrier plate.
Optionally, a second protective layer is formed on the front surface of the second die to be packaged, and the first die to be packaged with the first protective layer formed on the front surface is stacked and fixed in the front surface of the second die to be packaged through the second protective layer, and the semiconductor packaging method includes:
Applying the second protective layer on the front surface of the second die to be packaged;
after the second protective layer is preliminarily heated, applying the first die to be packaged, the front surface of which is provided with the first protective layer, to a preset position of the front surface of the second die to be packaged through the second protective layer;
And continuing to heat the second protective layer, wherein the second protective layer is cured by heating, and the first die to be packaged is cured to the front surface of the second die to be packaged along with the second protective layer.
Optionally, the preliminary heating time is 30 seconds to 60 seconds, and the temperature is 80 degrees to 120 degrees; the heating time is 1-4 hours, and the temperature is 190-200 ℃.
Optionally, before the first die to be packaged with the first protective layer formed on the front surface is stacked and fixed on the front surface of the second die to be packaged through the second protective layer, the semiconductor packaging method includes: grinding the back surface of the first die to be packaged; and/or the number of the groups of groups,
Before forming the second protective layer on the front surface of the second die to be packaged, the semiconductor packaging method comprises the following steps: and grinding the back surface of the second die to be packaged.
Optionally, after forming the encapsulation layer, the semiconductor packaging method includes:
And stripping the carrier plate to expose the front surfaces of the first die to be packaged and the second die to be packaged.
Optionally, after exposing the front sides of the first die to be packaged and the second die to be packaged, the semiconductor packaging method includes:
Forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first die to be packaged;
forming a second protection layer opening on the second protection layer, wherein the second protection layer opening is positioned at a welding pad of the second die to be packaged;
And forming rewiring structures on the front sides of the first die to be packaged and the second die to be packaged, wherein the rewiring structures are electrically connected with the welding pads on the first die to be packaged through the first protective layer opening and are electrically connected with the welding pads on the second die to be packaged through the second protective layer opening.
Optionally, after the first die to be packaged with the first protective layer formed on the front surface is stacked and fixed on the front surface of the second die to be packaged through the second protective layer, before the first die to be packaged and the second die to be packaged are attached to a carrier board, the semiconductor packaging method includes:
forming a first protection layer opening on the first protection layer at a position corresponding to the bonding pad of the first die to be packaged, and forming a second protection layer opening on the second protection layer at a position corresponding to the bonding pad of the second die to be packaged.
Optionally, after forming a first protection layer opening on the first protection layer at a position corresponding to the bonding pad of the first die to be packaged and forming a second protection layer opening on the second protection layer at a position corresponding to the bonding pad of the second die to be packaged, the semiconductor packaging method includes:
And filling a first conductive medium in the first protective layer opening so that the first conductive medium is electrically connected with the bonding pad on the front side of the first die to be packaged, and filling a second conductive medium in the second protective layer opening so that the second conductive medium is electrically connected with the bonding pad on the front side of the second die to be packaged.
Optionally, after forming the encapsulation layer, the semiconductor packaging method includes:
stripping the carrier plate to expose the front surfaces of the first die to be packaged and the second die to be packaged;
And forming a rewiring structure on the front surfaces of the first die to be packaged and the second die to be packaged, wherein the rewiring structure is electrically connected with a welding pad on the first die to be packaged through the first conductive medium and is electrically connected with a welding pad on the second die to be packaged through the second conductive medium.
Another aspect of the present application provides a semiconductor package structure, including:
the packaging layer is provided with a plurality of concave cavities;
the first die and the second die are arranged in a stacked mode, the first die and the second die are located in the cavity, the back face of the second die faces the bottom of the cavity, and the back face of the first die faces the front face of the second die;
The first protection layer is formed on the front surface of the first bare chip, a first protection layer opening is formed on the first protection layer, and the first protection layer opening is positioned at a position corresponding to a welding pad on the front surface of the first bare chip;
The second protection layer is formed on the front surface of the second bare chip, a second protection layer opening is formed in the second protection layer, the second protection layer opening is located at a position corresponding to a welding pad on the front surface of the second bare chip, the first bare chip is fixed on the front surface of the second bare chip through the second protection layer, and one surface of the second protection layer, which is far away from the second bare chip, is flush with one surface of the first protection layer, which is far away from the first bare chip;
and the rewiring structure is formed on the front surfaces of the first die and the second die and used for leading out welding pads on the front surfaces of the first die and the second die.
Optionally, the projection of the first die is located within the outer periphery of the second die.
Optionally, the number of the first dies is a plurality, the first dies are tiled on the front surface of the second die, and the projections of the first dies are all located in the outer periphery of the second die.
According to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, on one hand, the beneficial effect of reducing the whole occupied space is realized through the compact structure formed by stacking the first bare chip and the second bare chip, and on the other hand, the first bare chip is directly fixed on the front surface of the second bare chip through the second protective layer, and the first bare chip is prevented from being fixed by using the bonding layer, so that the thickness of the whole layer structure is reduced, and the beneficial effect of reducing the whole occupied space is further realized.
Drawings
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 2 (a) -2(s) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 3 is a schematic structural view of a semiconductor package structure obtained by using the above semiconductor packaging method according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" or "an" and the like in the description and in the claims do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper" and/or "lower" and the like are used for ease of description only and are not limited to one position or one spatial orientation. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
According to various embodiments of the present application, a semiconductor packaging method is provided. Forming a first protection layer on the front surface of the first die to be packaged in the packaging process; forming a second protection layer on the front surface of a second bare chip to be packaged, and laminating and fixing the first bare chip to be packaged, the front surface of which is provided with the first protection layer, on the front surface of the second bare chip to be packaged through the second protection layer, wherein one surface of the second protection layer, which is far away from the second bare chip to be packaged, is flush with one surface of the first protection layer, which is far away from the first bare chip to be packaged; mounting the first bare chip to be packaged with the front surface forming the first protection layer and the second bare chip to be packaged with the front surface forming the second protection layer on a carrier plate, wherein the back surfaces of the first bare chip to be packaged and the second bare chip to be packaged are both upward, and the front surfaces are both directed towards the carrier plate; and forming an encapsulation layer, wherein the encapsulation layer is formed on the back surface of the second die to be encapsulated and the exposed carrier plate. According to the semiconductor packaging method, on one hand, the beneficial effect of reducing the whole occupied space is achieved through the compact structure of the stacked first bare chip and the second bare chip, on the other hand, the first bare chip is directly fixed on the front face of the second bare chip through the second protective layer, and the first bare chip is prevented from being fixed through the bonding layer, so that the thickness of the whole layer structure is reduced, the beneficial effect of reducing the whole occupied space is further achieved, and the semiconductor packaging structure has the advantages of being small in size and compact in structure and is suitable for small-sized light-weight electronic equipment. In addition, in the above embodiment of the present application, the first die to be packaged having the first protective layer formed on the front surface and the second die to be packaged having the second protective layer formed on the front surface are mounted on the carrier, and then the first die to be packaged and the second die to be packaged are encapsulated. The semiconductor packaging method of the application is applied to MCM, and has remarkable advantages.
As shown in fig. 1,2 (a) -2(s) and 3, the present application provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application. As shown in fig. 1, the semiconductor packaging method includes the steps of:
step 101: forming a first protection layer on the front surface of the first die to be packaged;
Step 102: forming a second protection layer on the front surface of a second bare chip to be packaged, and laminating and fixing the first bare chip to be packaged, the front surface of which is provided with the first protection layer, on the front surface of the second bare chip to be packaged through the second protection layer, wherein one surface of the second protection layer, which is far away from the second bare chip to be packaged, is flush with one surface of the first protection layer, which is far away from the first bare chip to be packaged;
Step 103: attaching the stacked first die to be packaged and the second die to be packaged on a carrier plate, wherein the back surfaces of the first die to be packaged and the second die to be packaged are upward, and the front surfaces of the first die to be packaged and the second die to be packaged are towards the carrier plate;
Step 104: and forming an encapsulation layer, wherein the encapsulation layer is formed on the back surface of the second die to be encapsulated and the exposed carrier plate.
The semiconductor packaging structure formed by the semiconductor packaging method in the embodiment has the advantages that on one hand, the beneficial effect of reducing the whole occupied space is realized through the compact structure formed by stacking the first bare chip and the second bare chip, on the other hand, the first bare chip is directly fixed on the front surface of the second bare chip through the second protective layer, and the first bare chip is prevented from being fixed by using the bonding layer, so that the thickness of the whole layer structure is thinned, and the beneficial effect of reducing the whole occupied space is further realized.
In this embodiment, in step 101, a first protection layer is formed on the front surface of the first die to be packaged, where the first protection layer may be formed on the front surface of the semiconductor wafer before dicing the semiconductor wafer into a plurality of first dies to be packaged, and then dicing the semiconductor wafer to obtain the first die to be packaged with the first protection layer formed on the front surface. It will be understood, of course, that the first protective layer may be formed on the front surface of each first die to be packaged after the semiconductor wafer is cut into the first die to be packaged, as the process allows, and is specifically selected according to the actual situation.
As shown in fig. 2 (a), the front surface of the first semiconductor wafer 100, that is, the front surface corresponding to the first die 201 to be packaged, has a first insulating layer 2011 and a first bonding pad 2012, and the first bonding pad 2012 is used for electrically connecting with the outside. The front side of the first die 201 to be packaged is the active side of the first die 201 to be packaged.
As shown in fig. 2 (b), a first protection layer 202 is formed on the front surface of the first semiconductor wafer 100, i.e., the front surface corresponding to the first die 201 to be packaged.
The first protective layer 202 is made of one or more of insulating materials such as polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like. Optionally, the material of the protective layer is selected to be insulating and capable of accommodating materials for chemical cleaning, polishing, etc. The first protective layer 202 may be formed on the first semiconductor wafer by lamination (Lamination), coating (Coating), printing (Printing), or the like. The temperature, pressure and time ranges are different according to the materials, and the curing conditions of different materials are different.
Next, as shown in fig. 2 (c), after the step of forming the first protective layer 202 is completed, the back surface of the first semiconductor wafer 100, that is, the back surface corresponding to the first die 201 to be packaged, is polished to thin the thickness of the first die 201 to be packaged, thereby thinning the thickness of the final overall packaging structure, and further realizing the beneficial effect of reducing the overall occupied space.
Then, as shown in fig. 2 (d), the first semiconductor wafer 100 with the first protection layer 202 formed thereon is cut along the scribe line, so as to obtain a plurality of first dies to be packaged 201 with the first protection layer 202 formed thereon. The cutting process may be mechanical cutting or laser cutting.
The first die 201 to be packaged with the first protective layer 202 is shown in fig. 2 (e), where the front surface of the first die 201 to be packaged still has the first insulating layer and the first bonding pad, but they are not labeled in the figure for convenience of subsequent process flow. The first die 201 to be packaged formed through the above steps is a die to be packaged having a specific function, and the first die 201 to be packaged is preferably a thin, small-sized die to be packaged.
Before step 102, i.e. before the second protective layer 202 'is formed on the front side of the second die 201' to be packaged, the semiconductor packaging method comprises: the backside of the second die 201' to be packaged is ground.
Specifically, as shown in fig. 2 (f), the front surface of the second semiconductor wafer 100', that is, the front surface corresponding to the second die 201' to be packaged, has a second insulating layer 2011' and a second bonding pad 2012', and the second bonding pad 2012' is for electrical connection with the outside. The front side of the second die 201 'to be packaged, i.e., the active side of the second die 201' to be packaged.
Next, as shown in fig. 2 (g), the back surface of the second semiconductor wafer 100', i.e., the back surface corresponding to the second die 201' to be packaged, is polished to thin the thickness of the second die 201' to be packaged, thereby thinning the thickness of the final overall package structure, and further realizing the beneficial effect of reducing the overall occupied space.
Then, as shown in fig. 2 (h), the second semiconductor wafer 100 'is cut along the scribe line, so as to obtain a plurality of second dies 201' to be packaged. The cutting process may be mechanical cutting or laser cutting.
The structure of the formed second die 201 'to be packaged is shown in fig. 2 (i), in which the front surface of the second die 201' to be packaged still has the second insulating layer and the second bonding pad, but they are not labeled in the figure for the convenience of the subsequent process flow.
In step 102, as shown in fig. 2 (j), specifically, it includes:
A second protective layer 202 'is applied to the front side of the second die 201' to be packaged. The second protective layer 202' is made of an insulating material such as one or more of polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like. Optionally, the material of the protective layer is selected to be insulating and capable of accommodating materials for chemical cleaning, polishing, etc. The second protective layer 202 'may be formed on the second die 201' to be packaged by lamination (Lamination), coating (Coating), printing (Printing), or the like.
After the second protective layer 202' is preliminarily heated, the first die 201 to be packaged having the first protective layer 202 formed on the front side is applied to a predetermined position of the front side of the second die 201' to be packaged through the second protective layer 202 '. Since the viscosity of the primarily heated second protective layer 202' will first decrease and the second protective layer 202' has strong fluidity at this time, the first die 201 to be packaged is placed at a predetermined position on the front surface of the second die 201' to be packaged, and the primarily heated second protective layer 202' that is originally between the first die 201 to be packaged and the second die 201' to be packaged can be squeezed away and around the periphery of the first die 201 to be packaged by applying pressure.
Continuing to heat the second protection layer 202', as the heating proceeds, the second protection layer 202' is cured by heating, and the first die 201 to be packaged is cured to the front surface of the second die 201 'along with the second protection layer 202'.
It should be noted that, the time and temperature of the preliminary heating are determined according to the specific kind of the material of the second protective layer 202', and general rules are as follows: the temperature of the preliminary heating is lower than the curing temperature of the material of the second protective layer 202'.
According to the rheological characteristics of the material of the second protective layer 202' during curing, the viscosity of the material of the second protective layer 202' decreases due to an increase in temperature, and when the temperature increases above the curing temperature, the material of the second protective layer 202' causes cross-linking between molecules, thereby increasing the viscosity, and the preliminary heating temperature is selected to be below and controllable below the curing temperature.
After the first die 201 to be packaged having the first protective layer 202 formed on the front surface is applied to the front surface of the second die 201' to be packaged at a predetermined position, the temperature may be raised to the curing temperature of the material of the second protective layer 202' or more, the curing thermodynamic characteristics of the different materials are different, the specific heating time is determined according to the data of the curing thermodynamics of the materials, the heating temperature is a temperature higher than the curing temperature, the heating time is the time for the second protective layer 202' to be heated to the full curing corresponding to the heating temperature, and generally the shorter the heating temperature is, the shorter the time required for the material to be fully crosslinked is, i.e., the shorter the curing time is.
In this embodiment, the preliminary heating time is 30 seconds to 60 seconds, and the temperature is 80 degrees to 120 degrees. The heating time is 1-4 hours, and the temperature is 190-200 ℃.
In the present embodiment, the number of the first dies to be packaged 201 is one, and the projections of the first dies to be packaged 201 are located within the outer periphery of the second dies to be packaged 201'. However, the number of the first die 201 to be packaged may be plural, the plural number is tiled on the front surface of the second die 201 'to be packaged, and the projections of the plural first die 201 to be packaged are located within the outer periphery of the second die 201'.
In this embodiment, the thickness of the first die 201 to be packaged is smaller than the thickness of the second die 201' to be packaged. Since the first die 201 to be packaged is fixed on the second die 201 'to be packaged by the first protective layer 202 during the manufacturing process, the thickness of the first die 201 to be packaged is smaller than that of the second die 201' to be packaged, so that the second die 201 'to be packaged can provide better support when the first die 201 to be packaged is fixed on the second die 201' to be packaged by the first protective layer 202. In addition, the occupied space of the whole packaging structure is reduced.
As shown in fig. 2 (j), a surface of the second protective layer 202' away from the second die 201' to be packaged is flush with a surface of the first protective layer 202 away from the first die 201 to be packaged, so as to ensure that the whole mounting surface is a plane when the stacked first die 201 to be packaged and the second die 201' to be packaged are mounted on the carrier.
As can be seen from the above, the step of laminating the first die 201 to be packaged to the second die 201' to be packaged and the step of forming the second protective layer 202' on the second die 201' to be packaged are performed simultaneously.
After completing step 102, the semiconductor packaging method includes, before proceeding to step 103:
Step 1025: as shown in fig. 2 (k), first protection layer openings 2021 are formed on the first protection layer 202 at positions corresponding to the bonding pads of the first die 201 to be packaged, each first protection layer opening 2021 corresponding to at least the bonding pads of the first die 201 to be packaged or the wires led out from the bonding pads, so that the bonding pads on the front surface of the first die 201 to be packaged or the wires led out from the bonding pads are exposed from the first protection layer opening 2021; and forming second protection layer openings 2021' on the second protection layer 202' at positions corresponding to the bonding pads of the second die 201' to be packaged, wherein each second protection layer opening 2021' is at least corresponding to the bonding pads of the second die 201' to be packaged or the wires led out from the bonding pads, so that the bonding pads on the front surface of the second die 201' to be packaged or the wires led out from the bonding pads are exposed from the second protection layer opening 2021 '.
If the first protective layer 202 material is a laser reactive material, the first protective layer opening 2021 may be formed in a laser patterning manner; if the first protective layer 202 material is a photosensitive material, the first protective layer opening 2021 may be lithographically formed. The shape of the first protection layer opening 2021 may be round, but may be other shapes such as oval, square, line, etc. The same applies to the second protective layer 202', and will not be described again here.
Step 1026: as shown in fig. 2 (l), the first protection layer opening 2021 is filled with the first conductive medium 203, such that the first conductive medium 203 is electrically connected with the bonding pad of the first die 201 to be packaged, and the first conductive medium 203 forms a vertical connection structure in the first protection layer opening 2021, such that the bonding pad of the surface of the first die 201 to be packaged extends to the surface of the first protection layer 202; and filling the second protection layer opening 2021 'with a second conductive medium 203' so that the second conductive medium 203 'is electrically connected with the bonding pad of the second die 201' to be packaged, and forming a vertical connection structure in the second protection layer opening 2021 'by the second conductive medium 203' so that the bonding pad of the surface of the second die 201 'to be packaged extends to the surface of the second protection layer 202'.
In some embodiments, the first conductive medium may not be filled in the first protection layer opening and the second conductive medium may be filled in the second protection layer opening, so that the plurality of first protection layer openings and the second protection layer openings are still hollow after the first die to be packaged with the first protection layer and the second die to be packaged with the second protection layer are mounted on the carrier.
In step 103, as shown in fig. 2 (m), the stacked first die 201 to be packaged and second die 201 'to be packaged are attached to the carrier 200 through an adhesive layer (not labeled in the figure), and the back sides of the first die 201 to be packaged and the second die 201' to be packaged are both upward, and the front sides are both facing the carrier 200. The bonding layer is used for bonding the first die to be packaged and the second die to be packaged, and can be made of a material which is easy to peel off, so that the carrier plate, the first die to be packaged and the second die to be packaged are peeled off in the subsequent process, for example, a thermal separation material which can lose adhesiveness through heating can be adopted.
In other embodiments, the bonding layer may be a two-layer structure, and the thermally-separable material layer and the die attach layer are adhered to the carrier 200, and the thermally-separable material layer loses adhesion when heated, and can be peeled off from the carrier 200, and the die attach layer is an adhesive material layer, and may be used to adhere the first die to be packaged and the second die to be packaged. After the first die to be packaged and the second die to be packaged are peeled off from the carrier 200, the die attach layer thereon may be removed by chemical cleaning. In one embodiment, the adhesive layer may be formed on the carrier 200 by lamination, printing, or the like.
As shown in fig. 2 (m), the stacked first die 201 to be packaged and the second die 201' to be packaged are placed on the carrier board 200 according to a predetermined arrangement position, and for convenience of expression, only one stacked first die 201 to be packaged and second die 201' are shown in the figure, and in fact, there are a plurality of stacked first dies 201 to be packaged and second dies 201' to be packaged on the carrier board 200 according to a predetermined arrangement position.
It can be understood that in the one-time packaging process, the first die to be packaged and the second die to be packaged may be plural, that is, the first die to be packaged and the second die to be packaged are simultaneously attached to the carrier 200, packaged, and cut into plural packages after the packaging is completed; one package may include one or more stacked first and second die to be packaged, and the positions of the one or more stacked first and second die to be packaged may be freely set according to the needs of the actual product.
Next, in step 104, an encapsulation layer 204 is covered on the carrier 200 and formed on the back surface of the second die 201' to be encapsulated and the exposed adhesive layer. As shown in fig. 2 (n), the encapsulation layer 204 is used to completely encapsulate the carrier 200 and the second die 201' to be encapsulated, so as to reconfigure a flat structure, so that after the carrier 200 is peeled off, rewiring and encapsulation can be continued on the reconfigured flat structure.
In one embodiment, the encapsulation layer 204 may be formed by laminating an epoxy film or ABF (Ajinomoto buildup film), or may be formed by injection molding (Injection molding), compression molding (Compression molding), or Transfer molding (Transfer molding) of an epoxy compound.
The encapsulation layer 204 includes a first surface 2041 opposite the carrier 200, is substantially planar, and is parallel to the surface of the carrier 200. The thickness of the encapsulation layer 204 may be thinned by grinding or polishing the first surface 2041. In an alternative embodiment, the thickness of the encapsulation layer 204 may be thinned to the back of the first die 201 to be packaged and the second die 201' to be packaged.
When encapsulating with the encapsulation layer 204, the encapsulation material easily penetrates between the carrier 200 and the first die 201 to be encapsulated and the second die 201' to be encapsulated during this process, since the encapsulation layer requires high pressure molding at the time of molding. By the embodiment of the application, a first protective layer 202 is formed outside the first die 201 to be packaged, and a second protective layer 202' is formed outside the second die 201' to be packaged, so that the first protective layer 202 and the second protective layer 202' can prevent the encapsulating material from penetrating to the surfaces of the first die 201 and the second die 201' to be packaged, and even if the encapsulating material penetrates, after the encapsulating material is peeled off from the carrier, the surfaces of the first protective layer 202 and the second protective layer 202' can be directly treated by a chemical mode or a grinding mode without directly contacting the front surfaces of the first die 201 and the second die 201' to be packaged, and further, the circuit structures of the front surfaces of the first die 201 and the second die 201' to be packaged cannot be damaged.
In an embodiment, as shown in fig. 2 (o), since the carrier 200 has a thermal separation film between the first die 201 to be packaged and the second die 201' to be packaged, the adhesion layer can be reduced in viscosity after being heated by heating, so as to peel off the carrier 200. By peeling the carrier 200 by heating the adhesive layer, damage to the first die 201 to be packaged and the second die 201' to be packaged during peeling can be minimized. In other embodiments, the carrier 200 may also be peeled off directly mechanically.
After the carrier 200 is peeled off, the lower surface of the encapsulation layer 204 facing the carrier 200, the front surfaces of the first die 201 to be packaged and the second die 201' to be packaged are exposed. After the carrier 200 is peeled off, a flat structure is obtained comprising the first die 201 to be packaged, the second die 201' to be packaged, the first protective layer 202 covering the front side of the first die 201 to be packaged, the second protective layer 202' covering the front side of the second die 201' to be packaged, and the encapsulation layer 204 encapsulating the back side of the first die 201 to be packaged. On the formed flat structure, rewiring and the like can be performed according to actual conditions, so that the first to-be-packaged die 201 and the second to-be-packaged die 201' are electrically connected with the outside.
In the embodiment of the present application, after the carrier 200 is peeled off, the surfaces of the first protective layer 202 and the second protective layer 202 'are exposed, and the die attach layer in the adhesive layer is still present on the surfaces of the first protective layer 202 and the second protective layer 202', and when removed by chemical means, the surfaces of the first protective layer 202 and the second protective layer 202 'can also protect the first die 201 to be packaged and the second die 201' to be packaged from damage. After the bonding layer is completely removed, if the encapsulating material is permeated before, the surface can be leveled by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; without the first protective layer 202 and the second protective layer 202', the surfaces of the first die 201 and the second die 201' to be packaged cannot be treated chemically or by grinding so as not to damage the circuits of the front surfaces of the first die 201 and the second die 201 '.
Then, rewiring is performed on the protection layer 202 of the first to-be-packaged die 201 and the front surface of the second to-be-packaged die 201', so as to form a rewiring structure. The front side of the first die 201 to be packaged and the front side of the second die 201 'to be packaged each have pads of die internal circuitry that can be brought out by rewiring on the front side of the first die 201 to be packaged and the front side of the second die 201'. The step of forming the rewiring structure includes: as shown in fig. 2 (p), a first rewiring layer 206 is formed on the first protective layer 202 of the first die 201 to be packaged, the front surface of the second protective layer 202 'of the second die 201' to be packaged, and the exposed encapsulation layer 204, and is electrically connected to the bonding pad of the first die 201 to be packaged and the bonding pad of the second die 201 'to be packaged through the first protective layer opening 2021, and the second protective layer opening 2021'; as shown in fig. 2 (q), a first conductive stud 208 is formed on the first rewiring layer 206; thereafter, as shown in fig. 2 (r), a first dielectric layer 207 is formed on the surfaces of the first rewiring layer 206 and the first conductive stud 208. The thickness of the first dielectric layer 207 may be such that the surface of the first conductive stud 208 is just exposed; the first dielectric layer 207 may also cover all exposed surfaces of the encapsulation layer 204, the protection layer 202 and the first rewiring layer 206, and then be thinned to the surface of the first conductive stud 208. In this process, the conductive features of the rewiring structure include the first rewiring layer 206 and the first conductive stud 208.
The first conductive stud 208 is preferably circular in shape, but may be rectangular, square, or other shapes, and the conductive stud 208 is electrically connected to the first rewiring layer 206. Specifically, the first conductive bump 208 may be formed on the first rewiring layer 206 by photolithography and electroplating.
In another embodiment, after the first rewiring layer 206 is formed, a first dielectric layer 207 may be formed on the first rewiring layer 206 and the exposed protective layer 202 and the encapsulation layer 204, wherein the first dielectric layer 207 has a first opening, and then a first conductive stud 208 electrically connected to the first rewiring layer 206 is formed in the first opening of the first dielectric layer 207. In this process, the conductive features of the rewiring structure include the first rewiring layer 206 and the first conductive stud 208.
In yet another embodiment, the first opening of the first dielectric layer may not be filled, i.e., the first conductive bump 208 electrically connected to the first rewiring layer 206 is not formed, so that the bonding pad or connection point of the first rewiring layer of the completed package is exposed from the first opening. In this process, the conductive features of the rewiring structure include only the first rewiring layer 206.
In an embodiment, the first dielectric layer 207 may be formed by lamination (Lamination), molding (Molding) or Printing (Printing), preferably using an epoxy compound.
Further, in an embodiment, the re-routing may be repeated on the front sides of the first die and the second die, such as a second re-routing layer or layers may be formed outside the front side plastic package in the same manner to achieve multi-layer re-routing of the product.
In this embodiment, since the protective layer opening is already formed on the protective layer 202, at least the protective layer opening can be directly seen when the first rewiring layer 206 is formed, and thus the first rewiring layer 206 can be more accurately aligned when formed.
It should be noted that, in another embodiment, the adjustment of step 1025 and step 1026 to the peeling of the carrier may also be performed after the formation of the encapsulation layer and the peeling of the carrier, that is, after the formation of the encapsulation layer and the peeling of the carrier, the first protection layer opening is formed on the first protection layer, the second protection layer opening is formed on the second protection layer, and then the rewiring structure is formed on the front surfaces of the first die to be encapsulated and the second die to be encapsulated, and the rewiring structure is electrically connected to the bonding pad on the first die to be encapsulated through the first protection layer opening and is electrically connected to the bonding pad on the second die to be encapsulated through the second protection layer opening. Alternatively, the first rewiring layer of the rewiring structure may be formed by filling the first protective layer opening with the first conductive medium and filling the second protective layer opening with the second conductive medium. However, the method is not limited thereto, and the first rewiring layer forming the rewiring structure and the filling of the first protective layer opening with the first conductive medium and the filling of the second protective layer opening with the second conductive medium may be performed in the same conductive layer forming process.
Subsequently, after the package of the rewiring structure, the entire package structure is cut into a plurality of packages, that is, a plurality of semiconductor packages by laser or mechanical cutting, as shown in fig. 2(s), and the structure diagram of the formed semiconductor package structure is shown in fig. 3.
Fig. 3 is a schematic structural view of a semiconductor package structure obtained by using the above semiconductor packaging method according to an exemplary embodiment of the present application. As shown in fig. 3, the semiconductor package structure includes:
An encapsulation layer 204 provided with a plurality of concave cavities;
The first die 201 and the second die 201 'which are arranged in a stacked manner, wherein the first die 201 and the second die 201' are positioned in the cavity, the back surface of the second die 201 'faces the bottom of the cavity, and the back surface of the first die 201 faces the front surface of the second die 201';
the first protection layer 202 is formed on the front surface of the first die 201, and a first protection layer opening is formed on the first protection layer 202 and is positioned at a position corresponding to the bonding pad on the front surface of the first die 201;
The second protection layer 202 'is formed on the front surface of the second die 201', a second protection layer opening is formed on the second protection layer 202', the second protection layer opening is located at a position corresponding to a bonding pad on the front surface of the second die 201', the first die 201 is fixed on the front surface of the second die 201 'through the second protection layer 202', and one surface of the second protection layer 202 'away from the second die 201' is flush with one surface of the first protection layer 202 away from the first die 201;
and a rewiring structure formed on the front surfaces of the first die 201 and the second die 201 'for extracting the bonding pads on the front surfaces of the first die 201 and the second die 201'.
In this way, the semiconductor packaging structure of the embodiment has the beneficial effects of reducing the whole occupied space by the compact structure formed by stacking the first bare chip and the second bare chip on one hand, and directly fixing the first bare chip on the front surface of the second bare chip by the second protective layer on the other hand, so that the first bare chip is prevented from being fixed by using the adhesive layer, the thickness of the whole layer structure is reduced, and the beneficial effects of reducing the whole occupied space are further realized.
The projection of the first die 201 in the semiconductor package structure is located within the outer periphery of the second die 201' to further achieve the beneficial effect of reducing the overall occupied space.
In the present embodiment, the number of the first dies 201 is one, but the number of the first dies 201 is not limited thereto, and may be plural, the plural number is tiled on the front surface of the second die 201', and the projections of the plural first dies 201 are all located within the outer periphery of the second die 201'.
In the present embodiment, the thickness h1 of the first die 201 is smaller than the thickness h1 'of the second die 201'. As described above, since the first die 201 is fixed on the second die 201' by the first protective layer 202 during the fabrication process, by setting the thickness h1 of the first die 201 to be smaller than the thickness h1' of the second die 201', the second die 201' can provide better support when the first die 201 is fixed on the second die 201' by the first protective layer 202. In addition, the occupied space of the whole packaging structure is reduced.
In some embodiments, the rewiring structure comprises: a first rewiring layer 206 formed on the protective layer 202, the second die 201' and the exposed encapsulation layer 204 and electrically connected with the bonding pads of the first die 201 through the protective layer openings; and a first dielectric layer 207 formed on the first rewiring layer 206 and the exposed protective layer 202, the second die 201' and the encapsulation layer 204, and having a first opening, wherein a first conductive stud 208 electrically connected to the first rewiring layer 206 is disposed in the first opening of the first dielectric layer 207.
In another embodiment, the rewiring structure comprises a plurality of rewiring layers to achieve multi-layer rewiring of a product.
In the application, the device embodiment and the method embodiment can be mutually complemented under the condition of no conflict.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.

Claims (13)

1. A method of packaging a semiconductor, comprising:
forming a first protection layer on the front surface of the first die to be packaged;
Forming a second protection layer on the front surface of a second bare chip to be packaged, and laminating and fixing the first bare chip to be packaged, the front surface of which is provided with the first protection layer, on the front surface of the second bare chip to be packaged through the second protection layer, wherein one surface of the second protection layer, which is far away from the second bare chip to be packaged, is flush with one surface of the first protection layer, which is far away from the first bare chip to be packaged; the back surface of the first die to be packaged is in direct contact with the front surface of the second die to be packaged;
attaching the stacked first die to be packaged and the second die to be packaged on a carrier plate, wherein the back surfaces of the first die to be packaged and the second die to be packaged are upward, and the front surfaces of the first die to be packaged and the second die to be packaged are towards the carrier plate;
And forming an encapsulation layer, wherein the encapsulation layer is formed on the back surface of the second die to be encapsulated and the exposed carrier plate.
2. The semiconductor packaging method according to claim 1, wherein a second protective layer is formed on a front surface of a second die to be packaged, and the first die to be packaged, the front surface of which is formed with the first protective layer, is stacked and fixed in the front surface of the second die to be packaged through the second protective layer, the semiconductor packaging method comprising:
Applying the second protective layer on the front surface of the second die to be packaged;
after the second protective layer is preliminarily heated, applying the first die to be packaged, the front surface of which is provided with the first protective layer, to a preset position of the front surface of the second die to be packaged through the second protective layer;
And continuing to heat the second protective layer, wherein the second protective layer is cured by heating, and the first die to be packaged is cured to the front surface of the second die to be packaged along with the second protective layer.
3. The semiconductor packaging method according to claim 2, wherein the preliminary heating time is 30 seconds to 60 seconds and the temperature is 80 degrees to 120 degrees; the heating time is 1-4 hours, and the temperature is 190-200 ℃.
4. The semiconductor packaging method according to claim 1, characterized in that before the first die to be packaged having the first protective layer formed on the front side is stacked and fixed on the front side of the second die to be packaged by the second protective layer, the semiconductor packaging method comprises: grinding the back surface of the first die to be packaged; and/or the number of the groups of groups,
Before forming the second protective layer on the front surface of the second die to be packaged, the semiconductor packaging method comprises the following steps: and grinding the back surface of the second die to be packaged.
5. The semiconductor packaging method according to claim 1, wherein after the encapsulation layer is formed, the semiconductor packaging method comprises:
And stripping the carrier plate to expose the front surfaces of the first die to be packaged and the second die to be packaged.
6. The semiconductor packaging method of claim 5, wherein after exposing the front faces of the first die to be packaged and the second die to be packaged, the semiconductor packaging method comprises:
Forming a first protection layer opening on the first protection layer, wherein the first protection layer opening is positioned at a welding pad of the first die to be packaged;
forming a second protection layer opening on the second protection layer, wherein the second protection layer opening is positioned at a welding pad of the second die to be packaged;
And forming rewiring structures on the front sides of the first die to be packaged and the second die to be packaged, wherein the rewiring structures are electrically connected with the welding pads on the first die to be packaged through the first protective layer opening and are electrically connected with the welding pads on the second die to be packaged through the second protective layer opening.
7. The semiconductor packaging method according to claim 1, wherein after the first die to be packaged having the first protective layer formed on the front side is stacked and fixed on the front side of the second die to be packaged through the second protective layer, before the first die to be packaged and the second die to be packaged are mounted on a carrier board, the semiconductor packaging method comprises:
forming a first protection layer opening on the first protection layer at a position corresponding to the bonding pad of the first die to be packaged, and forming a second protection layer opening on the second protection layer at a position corresponding to the bonding pad of the second die to be packaged.
8. The semiconductor packaging method of claim 7, wherein after forming a first protective layer opening on the first protective layer at a position corresponding to a pad of the first die to be packaged and forming a second protective layer opening on the second protective layer at a position corresponding to a pad of the second die to be packaged, the semiconductor packaging method comprises:
And filling a first conductive medium in the first protective layer opening so that the first conductive medium is electrically connected with the bonding pad on the front side of the first die to be packaged, and filling a second conductive medium in the second protective layer opening so that the second conductive medium is electrically connected with the bonding pad on the front side of the second die to be packaged.
9. The semiconductor packaging method according to claim 8, wherein after the encapsulation layer is formed, the semiconductor packaging method comprises:
stripping the carrier plate to expose the front surfaces of the first die to be packaged and the second die to be packaged;
And forming a rewiring structure on the front surfaces of the first die to be packaged and the second die to be packaged, wherein the rewiring structure is electrically connected with a welding pad on the first die to be packaged through the first conductive medium and is electrically connected with a welding pad on the second die to be packaged through the second conductive medium.
10. A semiconductor package structure, characterized in that the semiconductor package structure is manufactured by the semiconductor package method according to any one of claims 1 to 9; it comprises the following steps:
the packaging layer is provided with a plurality of concave cavities;
the first die and the second die are arranged in a stacked mode, the first die and the second die are located in the cavity, the back face of the second die faces the bottom of the cavity, and the back face of the first die faces the front face of the second die;
The first protection layer is formed on the front surface of the first bare chip, a first protection layer opening is formed on the first protection layer, and the first protection layer opening is positioned at a position corresponding to a welding pad on the front surface of the first bare chip;
The second protection layer is formed on the front surface of the second bare chip, a second protection layer opening is formed in the second protection layer, the second protection layer opening is located at a position corresponding to a welding pad on the front surface of the second bare chip, the first bare chip is fixed on the front surface of the second bare chip through the second protection layer, and one surface of the second protection layer, which is far away from the second bare chip, is flush with one surface of the first protection layer, which is far away from the first bare chip;
and the rewiring structure is formed on the front surfaces of the first die and the second die and used for leading out welding pads on the front surfaces of the first die and the second die.
11. The semiconductor package structure of claim 10, wherein a projection of the first die is located within an outer periphery of the second die.
12. The semiconductor package according to claim 11, wherein the number of the first dies is plural, the plural first dies are tiled on the front surface of the second die, and projections of the plural first dies are located within the outer periphery of the second die.
13. The semiconductor package structure of claim 10, wherein a thickness of the first die is less than a thickness of the second die.
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