CN113723042B - Interface position layout method and device, electronic device and storage medium - Google Patents
Interface position layout method and device, electronic device and storage medium Download PDFInfo
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- CN113723042B CN113723042B CN202111027117.5A CN202111027117A CN113723042B CN 113723042 B CN113723042 B CN 113723042B CN 202111027117 A CN202111027117 A CN 202111027117A CN 113723042 B CN113723042 B CN 113723042B
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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Abstract
An interface position layout method and apparatus, an electronic device and a storage medium of an integrated circuit, the integrated circuit including at least one module, each module including a plurality of ports including a target port to be set, the layout method comprising: generating a routing path resource list based on a routing path to be planned in the integrated circuit, wherein the routing path resource list comprises physical position information of the routing path; determining physical location information of a target port; and determining a routing path corresponding to the target port based on the routing path resource list according to the physical position information of the target port, and obtaining an interface position corresponding to the target port. The layout method can improve the accuracy and reliability of the determined interface position, thereby improving the layout efficiency of the interface position in the integrated circuit.
Description
Technical Field
Embodiments of the present disclosure relate to a layout method of an interface position of an integrated circuit, an interface position layout apparatus of an integrated circuit, an electronic device, and a storage medium.
Background
At present, with the continuous development and progress of chip technology, high speed, high integration, low power consumption and low cost have become the main development direction of the integrated circuit industry, and the performance requirements of the market on chip products are correspondingly improved. Therefore, the design scale and complexity of the chip are also greatly increased.
Disclosure of Invention
At least one embodiment of the present disclosure provides a layout method of interface locations of an integrated circuit including at least one module, each of the modules including a plurality of ports including a target port to be set, the method comprising: generating a routing path resource list based on a routing path to be planned in the integrated circuit, wherein the routing path resource list comprises physical position information of the routing path; determining physical location information of the target port; and determining a routing path corresponding to the target port based on the routing path resource list according to the physical position information of the target port, and obtaining an interface position corresponding to the target port.
For example, in the layout method of the interface position of the integrated circuit provided in an embodiment of the present disclosure, the routing path resource list further includes interface state information of the routing path, and the method further includes: and adding port information corresponding to the target port into interface state information of a routing path corresponding to the target port in the routing path resource list so as to update the routing path resource list for use in subsequent layout operation.
For example, in a layout method of an interface position of an integrated circuit according to an embodiment of the present disclosure, determining, according to physical position information of the target port, a routing path corresponding to the target port based on the routing resource list, to obtain the interface position corresponding to the target port includes: and matching the target port with the routing path according to the physical position information of the target port and the physical position information of the routing path, and determining the routing path corresponding to the target port.
For example, in a layout method of an interface position of an integrated circuit provided in an embodiment of the present disclosure, generating the routing path resource list based on a routing path to be planned in the integrated circuit includes: determining physical position information of the routing path according to the physical layout structure of the integrated circuit; determining physical location information of the target port includes: and determining the physical position information of the target port according to the physical layout structure of the integrated circuit.
For example, in a layout method of an interface position of an integrated circuit according to an embodiment of the present disclosure, the integrated circuit includes at least one routing layer, each routing layer includes at least one routing path, physical location information of the routing path includes a routing layer where the routing path is located, and physical location information of the target port includes a routing layer where the target port is located.
For example, in a layout method of an interface position of an integrated circuit according to an embodiment of the present disclosure, determining physical position information of the routing path according to a physical layout structure of the integrated circuit includes: establishing a physical coordinate system based on a physical edge of the integrated circuit, wherein an interface of the integrated circuit is formed on the physical edge; determining projection coordinates of an interface corresponding to the routing path in the physical coordinate system, wherein the physical position information of the routing path comprises the projection coordinates of the interface corresponding to the routing path in the physical coordinate system; according to the physical position information of the target port and the physical position information of the routing path, matching the target port with the routing path, and determining the routing path corresponding to the target port, including: determining initial coordinates of an interface position corresponding to the target port in the physical coordinate system according to the physical position information of the target port; and comparing the initial coordinates of the interface position in the physical coordinate system with the projection coordinates of the interface corresponding to the routing path in the physical coordinate system, and determining the routing path corresponding to the target port.
For example, in a layout method of an interface position of an integrated circuit according to an embodiment of the present disclosure, a physical edge of the integrated circuit includes a plurality of edges connected in sequence, an interface of the integrated circuit is formed on any one of the plurality of edges, and determining the projection coordinates of the interface corresponding to the routing path in the physical coordinate system includes: and determining the coordinates of the interface corresponding to the routing path in an edge coordinate system established based on the edge where the interface is located.
For example, in the layout method of the interface position of the integrated circuit provided in an embodiment of the present disclosure, the generating the routing path resource list based on the routing paths to be planned in the integrated circuit further includes: and sequencing the routing paths pointing to each side for each routing layer to obtain the logic offset of each routing path pointing to each side, wherein the routing path resource list comprises the logic offset of the routing paths on the side pointed by the routing paths.
For example, in the layout method of the interface position of the integrated circuit provided in an embodiment of the present disclosure, the generating the routing path resource list based on the routing paths to be planned in the integrated circuit further includes: and mapping the physical position information of the routing path to the logic offset of the routing path on the side pointed by the routing path, and generating the routing path resource list in a hash table mode.
For example, in a layout method of an interface position of an integrated circuit according to an embodiment of the present disclosure, determining, according to physical position information of the target port, the initial coordinates of an interface position corresponding to the target port in the physical coordinate system includes: determining an edge for placing an interface position corresponding to the target port, and determining an initial sub-coordinate of the interface position in an edge coordinate system established based on the edge; comparing the initial coordinates of the interface position in the physical coordinate system with the projection coordinates of the interface corresponding to the routing path in the physical coordinate system, and determining the routing path corresponding to the target port, including: and comparing the initial sub-coordinates of the interface position in the side coordinate system established based on the side with the coordinates of the interface corresponding to each routing path pointing to the side in the side coordinate system, and determining the routing path corresponding to the target port.
For example, in a layout method of an interface position of an integrated circuit according to an embodiment of the present disclosure, comparing the initial sub-coordinates of the interface position in the edge coordinate system established based on the edge with the coordinates of interfaces corresponding to routing paths pointing to the edge in the edge coordinate system, determining a routing path corresponding to the target port includes: calculating the average value of the distances between adjacent coordinates for the coordinates of the interfaces corresponding to the routing paths pointing to the edge in the edge coordinate system; dividing the initial sub-coordinates of the interface position in the edge coordinate system by the average value and rounding to obtain an initial offset; and determining a logic offset matched with the initial offset in the logic offsets of the routing paths pointing to the edge on the edge, and taking the routing path corresponding to the matched logic offset as the routing path corresponding to the target port.
For example, in a layout method of an interface position of an integrated circuit according to an embodiment of the present disclosure, determining, among the logic offsets on the edge of each trace path pointing to the edge, a logic offset that matches the initial offset, and taking a trace path corresponding to the matched logic offset as a trace path corresponding to the target port, where the method includes: judging interface state information of the routing paths corresponding to the logic offset equal to the initial offset in the logic offset of each routing path pointing to the edge; if the interface state information of the routing path is empty, the routing path is used as the routing path corresponding to the target port; if the interface state information of the routing path is not null, the initial offset is increased by an adjustment amount to obtain a new offset, and the interface state information of the routing path corresponding to the logic offset equal to the new offset is continuously judged.
For example, in the layout method of the interface position of the integrated circuit according to an embodiment of the present disclosure, determining, based on the routing resource list, a routing path corresponding to the target port according to the physical position information of the target port, to obtain the interface position corresponding to the target port, and further includes: and determining the matching sequence of the target ports based on the signal logic of the integrated circuit.
For example, the layout method of the interface position of the integrated circuit according to an embodiment of the present disclosure further includes: the destination port is determined based on signal logic of the integrated circuit.
For example, the layout method of the interface position of the integrated circuit according to an embodiment of the present disclosure further includes: and acquiring a routing path to be planned in the integrated circuit based on the layout of the integrated circuit.
At least one embodiment of the present disclosure also provides an interface position layout apparatus of an integrated circuit, the interface position layout apparatus of the integrated circuit including: the system comprises a route path resource list generation unit, a physical position information determination unit and a route path matching unit; the integrated circuit comprises at least one module, each module comprising a plurality of ports including a target port to be set; the route path resource list generation unit is configured to generate a route path resource list based on a route path to be planned in the integrated circuit, wherein the route path resource list comprises physical position information of the route path; the physical location information determining unit is configured to determine physical location information of the target port; the routing path matching unit is configured to determine a routing path corresponding to the target port based on the routing path resource list according to the physical position information of the target port, and obtain an interface position corresponding to the target port.
At least one embodiment of the present disclosure also provides an electronic device including a memory and a processor; the memory non-transitory stores computer-executable instructions; the processor is configured to execute the computer-executable instructions that when executed by the processor implement a method of layout of interface locations of an integrated circuit according to any of the embodiments of the present disclosure.
At least one embodiment of the present disclosure also provides a non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement a layout method of interface locations of an integrated circuit according to any embodiment of the present disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
FIG. 1 is a schematic flow chart of a method of layout of interface locations of an integrated circuit provided by some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of an integrated circuit provided in some embodiments of the present disclosure;
FIG. 3 is a schematic flow chart of a layout method of interface locations of another integrated circuit provided by some embodiments of the present disclosure;
FIG. 4 is a schematic diagram of a routing resource list provided by some embodiments of the present disclosure;
FIG. 5 is a schematic diagram of another routing resource list provided by some embodiments of the present disclosure;
FIG. 6 is a schematic flow chart diagram of a layout method of interface locations of yet another integrated circuit provided by some embodiments of the present disclosure;
FIG. 7A is a schematic flow chart of step S210 in a method for layout of interface locations of an integrated circuit according to some embodiments of the present disclosure;
FIG. 7B is a schematic flow chart of step S220 in a method for layout of interface locations of an integrated circuit according to some embodiments of the present disclosure;
FIG. 8 is a schematic diagram of a specific implementation example of a layout method of interface locations of an integrated circuit according to some embodiments of the present disclosure;
FIG. 9 is a schematic flow chart diagram of one example of step S222 in a layout method of interface locations of an integrated circuit provided by some embodiments of the present disclosure;
FIG. 10 is a schematic flow chart diagram of a layout method of interface locations of yet another integrated circuit provided by some embodiments of the present disclosure;
FIG. 11 is a schematic block diagram of an interface position layout apparatus for an integrated circuit provided in some embodiments of the present disclosure;
FIG. 12 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure;
FIG. 13 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure; and
Fig. 14 is a schematic diagram of a storage medium according to some embodiments of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
With the rapid development of the integrated circuit industry, the scale and complexity of circuit design are increasing, and the physical implementation difficulty of chips is also increasing. In the physical implementation of a chip, for example, automation software is generally used to design the placement positions of external interfaces in the chip for implementing external information interaction. At present, the external interfaces to be set are placed in sequence according to a certain rule by adopting automatic software, for example, the external interfaces are uniformly distributed on each side of the chip at equal intervals.
However, in the physical implementation process adopting the external interface setting mode, for example, in the physical implementation process of a chip with a larger circuit scale or a complex circuit design, mismatching between the designed interface position and the available routing resources in the chip often occurs, for example, conflict occurs between the designed interface position and the available routing channels in the chip, and problems such as violating of physical distance, uneven distribution of routing resources, repeated setting of interfaces and the like occur, so that an ideal physical implementation effect is difficult to achieve. Therefore, in the process of designing and developing the chip, a great deal of time is consumed to carry out layout design on each interface position of the chip, so that the development period of the chip is prolonged, and the physical realization efficiency of the chip is reduced.
At least one embodiment of the present disclosure provides a layout method of an interface position of an integrated circuit, the integrated circuit including at least one module, each module including a plurality of ports including a target port to be set, the layout method of the interface position of the integrated circuit including: generating a routing path resource list based on a routing path to be planned in the integrated circuit, wherein the routing path resource list comprises physical position information of the routing path; determining physical location information of a target port; and determining a routing path corresponding to the target port based on the routing path resource list according to the physical position information of the target port, and obtaining an interface position corresponding to the target port.
The layout method of the interface position of the integrated circuit provided by the embodiment of the disclosure can be applied to integrated circuits with different circuit structures or different layout designs, and the physical position information of the target port and the physical position information of the routing path can be utilized to jointly determine the routing path corresponding to the target port and the interface position corresponding to the routing path by generating the routing path resource list comprising the physical position information of the routing path, so that conflicts between the layout of the interface position and the routing path resources available or to be planned in the integrated circuit are avoided, such as occurrence of problems of physical distance violations, uneven distribution of the routing path resources, repeated interface setting and the like, and the layout design of the interface position is facilitated to achieve ideal physical realization effects.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements already described.
Fig. 1 is a schematic flow chart of a layout method of interface positions of an integrated circuit according to some embodiments of the present disclosure.
The layout method of the interface position of the integrated circuit provided by the embodiment of the disclosure can be applied to the design of the integrated circuit, such as the chip design. The integrated circuit includes one or more modules, each module including a plurality of ports including a target port to be set. For example, a port of a module may transmit different types of signals, such as digital signals, analog signals, power supply voltage signals, etc., so that the module can implement data communication, information interaction, etc., with other modules or external devices through the port. For example, the destination port of the module may be coupled to an interface in the integrated circuit for external communication, such that the destination port may perform functions such as external information interaction through the interface of the integrated circuit.
As shown in fig. 1, the layout method of the interface positions of the integrated circuit provided in the embodiment of the present disclosure includes steps S10 to S30.
Step S10: and generating a routing path resource list based on the routing path to be planned in the integrated circuit, wherein the routing path resource list comprises physical position information of the routing path.
Step S20: physical location information of the destination port is determined.
Step S30: and determining a routing path corresponding to the target port based on the routing path resource list according to the physical position information of the target port, and obtaining the interface position corresponding to the target port.
In the above-described embodiments of the present disclosure, in order to clearly describe the layout method of the interface position corresponding to the destination port, the description is made based on the module including the destination port in the integrated circuit, but this does not constitute a limitation on, for example, the structure or the type of the integrated circuit in the embodiments of the present disclosure. For example, the integrated circuit in the embodiments of the present disclosure may further include other modules that do not provide the destination port, or may further include other modules having different functions or structures as needed according to different needs, and the embodiments of the present disclosure are not particularly limited thereto.
Fig. 2 is a schematic diagram of an integrated circuit provided in some embodiments of the present disclosure, for example, fig. 2 shows a module 100 of the integrated circuit 10 with a destination port 111. It should be noted that one module 100 shown in fig. 2 is merely an exemplary illustration, and the number, structure, function, etc. of the modules 100 included in the integrated circuit 10 are not particularly limited by the embodiments of the present disclosure.
For example, referring to fig. 2, the module 100 includes a plurality of ports 110, where a target port 111 to be set is included in the plurality of ports 110, and the target port 111 may be connected to an interface 120 for external communication in the integrated circuit 10, so that the target port 111 may implement functions of data communication, information interaction, etc. with external devices or modules through the interface 120 of the integrated circuit 10.
For example, referring to fig. 2, other ports 110 in the module 100 than the destination port 111 may include internal ports for data communication or information interaction with other internal modules in the integrated circuit 10, or may also include ports that are suspended, i.e., that do not establish signal connections with other ports or signal sources. The embodiments of the present disclosure are not particularly limited in the number, function, type, etc. of ports 110 included in the module 100.
The layout method of the interface locations of the integrated circuit shown in fig. 1 is described in detail below in connection with the integrated circuit 10 shown in fig. 2.
For example, for the above step S10, at the time of front-end design of the integrated circuit 10, each of the routing paths available or to be planned in the integrated circuit 10, such as each of the routing paths L1 to Ln shown in fig. 2, may be determined according to, for example, a circuit design or a layout structure of the integrated circuit 10, for example, where n is a positive integer greater than 1 and is less than or equal to the number of routing paths available or to be planned in the integrated circuit 10. For example, one end of the routing path points to and corresponds to one interface 120 of the integrated circuit 10, and the other end of the routing path may be used to connect with the destination port 111, thereby, after determining the routing path corresponding to the destination port 111, allowing the destination port 111 to connect with the interface 120 corresponding to the routing path through the determined routing path, and further determining the interface position corresponding to the destination port 111.
For example, the generated route path resource list includes physical location information of each of the route paths L1 to Ln, and the physical location information may include, for example, layout locations of each of the route paths L1 to Ln in the integrated circuit 10, for example, location information of each of the route paths L1 to Ln in a physical coordinate system established based on the integrated circuit 10, and the location information may include, for example, one-dimensional data, two-dimensional data, or three-dimensional data information.
For example, for the above-described step S120, the physical location information of the target port 111 may include a layout location of the target port 111 in the integrated circuit 10, such as location information of the target port 111 in the above-described physical coordinate system established based on the integrated circuit 10. For example, in front-end design of the integrated circuit 10, a layout position of the module 100 in the integrated circuit 10 may be determined, and further, based on the layout position of the module 100 in the integrated circuit 10, a layout position of the target port 111 of the module 100 in the integrated circuit 10 may be further determined, so as to obtain physical position information of the target port 111.
For example, in the step S130, after determining the physical location information of the destination port 111, the obtained physical location information of the destination port 111 may be compared with the physical location information of each of the routes L1 to Ln to be planned in the generated route path resource list, so as to determine the route path used by the destination port 111 by using the physical location information of the destination port 111 and the physical location information of each of the routes L1 to Ln together, and further determine the interface 120 corresponding to the route path to obtain the interface location corresponding to the destination port 111.
The layout method of the interface positions of the integrated circuit provided in the above embodiments of the present disclosure may be applicable to the integrated circuits 10 having different structural designs. Compared with the mode of uniform layout of the interface positions adopted in the conventional chip design, the layout method provided by the embodiment of the disclosure can better perform adaptive layout design on the interface positions in different types of chips according to actual different requirements, so as to avoid conflict between the interface positions of the planned target port 111 and the routing paths available or to be planned in the integrated circuit 10, for example, the problems of physical distance violations, uneven distribution of the routing path resources and the like can be avoided, and further, the layout design of the interface positions is beneficial to achieving ideal physical realization effects. Therefore, the accuracy and reliability of the layout of the interface positions of the integrated circuit 10 can be improved, the time required for layout of the interface positions is reduced, the layout efficiency of the interface positions is improved, the development period of the integrated circuit 10 is shortened, and the physical realization efficiency of the integrated circuit 10 is improved.
For example, in some embodiments of the present disclosure, the step S30 may include: the matching order of the destination ports is determined based on the signal logic of the integrated circuit.
For example, taking the integrated circuit 10 shown in fig. 2 as an example, when the interface positions of the plurality of target ports 111 in the integrated circuit 10 need to be laid out, the sequence of matching between each target port 111 and the routing path to be planned may be determined based on the signal logic of the integrated circuit 10. For example, the target port 111 with higher performance requirements or for implementing more important functions may be preferentially matched according to the functions or performance requirements of the target port 111 required to be implemented in the signal logic of the integrated circuit 10, so that the layout efficiency of each interface position in the integrated circuit 10 may be significantly improved, the physical implementation effect of the integrated circuit 10 is improved, and the reliability and stability of the designed integrated circuit 10 are further improved.
Fig. 3 is a schematic flow chart of a layout method of interface positions of another integrated circuit provided by some embodiments of the present disclosure. It should be noted that, except for step S40, steps S10 to S30 in the layout method of the interface positions of the integrated circuit shown in fig. 3 are substantially the same as or similar to steps S10 to S30 in the layout method of the interface positions of the integrated circuit shown in fig. 1, and the repetition is omitted.
For example, in some embodiments of the present disclosure, the trace resource list generated in step S10 further includes interface state information of the trace path. As shown in fig. 3, the layout method of the interface position of the integrated circuit further includes the following step S40.
Step S40: and adding the port information corresponding to the target port into the interface state information of the routing path corresponding to the target port in the routing path resource list so as to update the routing path resource list for use in subsequent layout operation.
For example, the interface status information of the routing path may include a usage status of an interface corresponding to the routing path, such as whether the interface corresponding to the routing path has been allocated for use by a corresponding destination port. In the case that the interface corresponding to the routing path is allocated to the corresponding destination port for use, the interface status information of the routing path may further include port information corresponding to the destination port using the interface, for example, the port information may include a name, a type, and the like of the destination port.
Fig. 4 is a schematic diagram of a routing path resource list provided in some embodiments of the present disclosure, for example, the routing path resource list may correspond to the initial routing path resource list generated in step S10 and not updated. Fig. 5 is a schematic diagram of another route path resource list provided in some embodiments of the present disclosure, for example, the route path resource list may correspond to the route path resource list updated in step S40.
For example, taking the routing path corresponding to the destination port 111 shown in fig. 2 as the routing path L1 as an example, as shown in fig. 4 and fig. 5, after determining that the routing path corresponding to the destination port 111 is the routing path L1, port information corresponding to the destination port 111, for example, the name PINA of the destination port 111, is added to interface state information of the routing path L1 in the routing path resource list, for example, interface state information N/a corresponding to the routing path L1 in the initial routing path resource list shown in fig. 4 is updated to PINA shown in fig. 5, so that real-time update of the generated routing path resource list is realized for use in a subsequent layout operation.
Therefore, by updating the interface state information of each routing path in the routing path resource list in real time, the conflict possibly generated between the layout of the interface position and the routing paths available or to be planned in the integrated circuit can be avoided, for example, the problems that the same interface is repeatedly arranged or the same interface position is repeatedly allocated can be avoided. Therefore, the layout of the interface positions can achieve ideal physical realization effect, thereby improving the accuracy and reliability of the layout of the interface positions of the integrated circuit, reducing the time required for layout of the interface positions and improving the layout efficiency of the interface positions.
For example, in some embodiments of the present disclosure, the above-described step S30 shown in fig. 1 includes the following step S230.
Step S230: and matching the target port with the routing path according to the physical position information of the target port and the physical position information of the routing path, and determining the routing path corresponding to the target port.
For example, when determining the routing path corresponding to the target port 111 based on the routing path resource list generated in step S10, the physical location information of the routing path matching the physical location information of the target port 111 may be found from the routing path resource list based on the relative physical location relationship between the target port 111 and the routing paths to be planned, and the routing path corresponding to the target port 111 may be determined based on the correspondence relationship between the relative physical location of the target port 111 in the integrated circuit 10 and the relative physical locations of the routing paths in the integrated circuit 10, for example.
Fig. 6 is a schematic flow chart of a layout method of interface positions of yet another integrated circuit provided in some embodiments of the present disclosure. For example, step S210 shown in fig. 6 corresponds to one example of step S10 shown in fig. 1, step S220 shown in fig. 6 corresponds to one example of step S20 shown in fig. 1, and step S230 shown in fig. 6 corresponds to one example of step S30 shown in fig. 1.
For example, as shown in fig. 6, in some embodiments of the present disclosure, the layout method of the interface position of the integrated circuit includes the following steps S210 to S230.
Step S210: and determining the physical position information of the routing path according to the physical layout structure of the integrated circuit.
Step S220: and determining the physical position information of the target port according to the physical layout structure of the integrated circuit.
Step S230: and matching the target port with the routing path according to the physical position information of the target port and the physical position information of the routing path, and determining the routing path corresponding to the target port.
Therefore, according to the physical layout structure of the integrated circuit, the physical position information between the target port and each routing path to be planned in the same physical space coordinate system can be obtained, and the target port and the routing path are matched according to the physical position information established in the same physical space coordinate system, so that the determined routing path corresponding to the target port is more accurate, the physical distance rule in the integrated circuit is more met, and the layout design of the interface position is facilitated to achieve a better physical realization effect.
For example, integrated circuit 10 may include one or more trace layers, each including one or more trace paths, such as each trace path L1 through Ln shown in FIG. 2, all located in the same trace layer M1. The physical location information of the routing path includes a routing layer where the routing path is located, for example, the routing resource list shown in fig. 4 and fig. 5 includes a routing layer M1 where the routing paths L1 to Ln are located. The physical location information of the destination port includes a routing layer where the destination port is located, for example, the destination port 111 shown in fig. 2 is located at the same routing layer M1 as the routing layers L1 to Ln.
For example, when the target port is matched with the routing path, the target port in each layer in the integrated circuit can be matched with the routing path to be planned in the routing layer in sequence according to the routing layer where the target port is located, so that the problems of physical distance violations, uneven distribution of routing path resources and the like can be avoided, the accuracy and reliability of the layout of the interface position are improved, the time consumed in the process of laying out the interface position can be shortened, and the layout efficiency of the interface position is improved.
Next, a specific implementation method of the steps S210 to S230 will be exemplarily described by taking as an example the matching of the target port 111 in the trace layer M1 shown in fig. 2 and each of the trace paths L1 to Ln in the trace layer M1.
Fig. 7A is a schematic flowchart of step S210 in a method for laying out an interface position of an integrated circuit according to some embodiments of the present disclosure, and fig. 7B is a schematic flowchart of step S220 in a method for laying out an interface position of an integrated circuit according to some embodiments of the present disclosure.
For example, as shown in fig. 7A, the above step S210 may include the following steps S211 and S212.
Step S211: based on the physical edge of the integrated circuit, a physical coordinate system is established, and an interface of the integrated circuit is formed on the physical edge.
Step S212: and determining projection coordinates of the interface corresponding to the routing path in a physical coordinate system.
For example, the physical location information of the routing path includes projection coordinates of the interface corresponding to the routing path in a physical coordinate system.
For example, as shown in fig. 7B, the above step S212 may include the following steps S221 and S222.
Step S221: and determining initial coordinates of the interface position corresponding to the target port in a physical coordinate system according to the physical position information of the target port.
Step S222: and comparing the initial coordinates of the interface position in the physical coordinate system with the projection coordinates of the interface corresponding to the routing path in the physical coordinate system, and determining the routing path corresponding to the target port.
For example, a physical edge of integrated circuit 10 may refer to a physical edge of integrated circuit 10 that is used to locate interfaces 120. By projecting the destination port 111 and the routing paths L1 to Ln into the physical coordinate system established based on the physical edge of the integrated circuit 10, the comparison between the physical location information of the destination port 111 and the physical location information of the routing paths L1 to Ln can be facilitated, so that the routing paths matched with the destination port 111 can be more accurately determined, and the obtained interface location corresponding to the destination port 111 more accords with the physical design specification of the integrated circuit.
Fig. 8 is a schematic diagram of a specific implementation example of a layout method of an interface position of an integrated circuit according to some embodiments of the present disclosure, for example, fig. 8 shows a partial area in a trace layer M1 of the integrated circuit 10 shown in fig. 2.
For example, taking the integrated circuit 10 shown in fig. 2 as an example, referring to fig. 2 and 8, the physical edge of the integrated circuit 10 includes a plurality of edges EDG1, EDG2, EDG3, and EDG4 connected in sequence, and the interface 120 of the integrated circuit 10 is formed on any one of the plurality of edges EDG1, EDG2, EDG3, and EDG 4. For example, interfaces 120 corresponding to the routing paths L1 to Ln are formed on the side EDG 1. For example, fig. 8 shows a case where the routing paths L1 to Ln are L1 to L5.
For example, the step S212 includes: and determining the coordinates of the interface corresponding to the routing path in an edge coordinate system established based on the edge where the interface is located. For example, the coordinates of the interfaces 120 corresponding to the routing paths L1 to Ln (e.g., the routing paths L1 to L5) shown in fig. 2 and 8 in the side coordinate system established based on the side EDG1 are the coordinates S1 to Sn shown in fig. 4 and 5, respectively, for example, the values of the coordinates S1 to Sn gradually increase with the point where the side EDG1 and the side EDG4 intersect each other as the origin of the side coordinate system.
For example, as shown in fig. 4 and 5, the routing resource list further includes logical offsets 1 to n of the routing paths L1 to Ln on the edge EDG1 pointed to by the routing paths L1 to Ln. It should be noted that, the logical offset of the routing paths L1 to Ln on the pointed edge EDG1 may be an increasing sequence of 1 from 1 and sequentially increasing 1 as shown in fig. 4 and 5; or in other examples of the disclosure, the logic offset of the trace paths L1 to Ln on the pointed edge EDG1 may also start from 0, 2 or other suitable values, or may sequentially increase or decrease other values different from 1, or may also be a suitable random number sequence, etc., and the embodiments of the disclosure do not limit the specific data type of the logic offset.
For example, in order to obtain the logical offsets 1 to n of the routing paths L1 to Ln shown in fig. 4 and 5 on the edge EDG1 to which the routing paths L1 to Ln point, step S130 shown in fig. 1 may include: for each trace layer, the trace paths pointing to each edge are ordered to obtain the logical offset of the respective trace paths pointing to each edge. For example, taking the routing paths L1 to Ln located in the routing layer M1 and pointing to the edge EDG1 as an example, the routing paths L1 to Ln may be ordered according to the numerical values of the coordinates S1 to Sn of the interfaces 120 corresponding to the routing paths L1 to Ln in the edge coordinate system established based on the edge EDG1, so as to determine the logic offsets 1 to n of the routing paths L1 to Ln on the edge EDG 1.
For example, step S130 shown in fig. 1 may further include: and mapping the physical position information of the routing path to the logic offset of the routing path on the side pointed by the routing path, and generating a routing path resource list in the form of a hash table. For example, after obtaining the logical offsets 1 to n of the routing paths L1 to Ln, physical position information such as the routing layer M1 where the routing paths L1 to Ln are located, the edge EDG1 to which they are directed, coordinates S1 to Sn in an edge coordinate system established based on the edge EDG1, and the like is mapped to the logical offsets 1 to n of the routing paths L1 to Ln on the edge EDG1, respectively, thereby generating the routing path resource lists shown in fig. 4 and 5 in the form of hash tables. In the routing path resource list generated in the form of a hash table, each routing path is defined with unique parameter information, so that conflicts caused by the fact that a plurality of target ports use the same routing path can be avoided, and the method is beneficial to meeting rules in the physical design of chips.
For example, after generating the route resource list shown in fig. 4 and 5 in the form of a hash table, the above-described step S221 may include the following steps S2211 and S2212.
Step S2211: an edge for placing an interface location corresponding to the destination port is determined.
Step S2211: an initial sub-coordinate of the interface location in an edge coordinate system established based on the edge is determined.
For example, after generating the trace resource list shown in fig. 4 and 5 in the form of a hash table, the above-described step S222 may include: and comparing the initial sub-coordinates of the interface position in the side coordinate system established based on the side with the coordinates of the interface corresponding to each routing path pointing to the side in the side coordinate system, and determining the routing path corresponding to the target port.
For example, the edge EDG1 for placing the interface position corresponding to the target port 111 may be determined according to the placement position and the placement direction of the module 100 and the target port 111 in the integrated circuit 10, and the projection coordinate of the target port 111 on the edge EDG1 may be determined as the initial sub-coordinate ES0 of the interface position corresponding to the target port 111 on the edge EDG1 according to the physical position information of the target port 111 in the integrated circuit 10. Further, the routing path corresponding to the target port 111 may be determined based on the comparison result between the initial sub-coordinates ES0 and the coordinates S1 to Sn of the routing paths L1 to Ln in the side coordinate system established based on the side EDG 1.
Fig. 9 is a schematic flowchart of an example of step S222 in a layout method of interface positions of an integrated circuit according to some embodiments of the present disclosure.
For example, step S222 may include the following steps S2221 to 2213.
Step S2221: for the coordinates of the interface corresponding to each routing path pointing to the edge in the edge coordinate system, an average value of the spacing between adjacent coordinates is calculated.
Step S2222: dividing the initial sub-coordinates of the interface position in the edge coordinate system by the average value and rounding to obtain the initial offset.
Step S2223: and determining the logic offset matched with the initial offset in the logic offset of each routing path pointing to the edge on the edge, and taking the routing path corresponding to the matched logic offset as the routing path corresponding to the target port.
For example, as shown in fig. 2,4 and 8, taking matching the target port 111 with the routing paths L1 to L5 as an example, for coordinates S1 to S5 of the interface 120 corresponding to each routing path L1 to L5 directed to the edge EDG1 in the edge coordinate system, an average value p0 of the pitches p1, p2, p3 and p4 between adjacent coordinates is calculated. The initial sub-coordinates ES0 of the interface position corresponding to the target port 111 in the side coordinate system are divided by the average value p0 and rounded to obtain an initial offset X, for example, the initial offset X corresponding to the target port 111 is 1, that is, x=1. Then, among the logical offsets 1 to 5 on the side EDG1 of the respective routing paths L1 to L5 directed to the side EDG1, a logical offset matching the initial offset X is determined, and the routing path corresponding to the matched logical offset is taken as the routing path corresponding to the target port 111.
For example, among the logical offsets 1 to 5 on the side EDG1 of the respective routing paths L1 to L5 directed to the side EDG1, the interface state information of the routing path corresponding to the logical offset equal to the initial offset X is determined, for example, when x=1, the interface state information of the routing path L1 corresponding to the logical offset 1 equal to the initial offset X is determined. If the interface status information of the trace path L1 is empty as shown in fig. 4, the trace path L1 is taken as the trace path corresponding to the destination port 111, so that the interface status information of the trace path L1 is updated to PINA as shown in fig. 5.
For example, when the layout is performed on the interface positions corresponding to the other target ports that need to be placed on the edge EDG1, the above-mentioned matching process for the target port 111 may be repeated. For example, if the initial offset corresponding to the destination port to be laid out subsequently is also 1, since the interface state information of the routing path L1 corresponding to the logical offset 1 is not null, it is necessary to increase the initial offset corresponding to the destination port by an adjustment amount to obtain a new offset, for example, by 1 to obtain a new offset 2, and to continue to determine the interface state information of the routing path corresponding to the logical offset equal to the new offset 2, for example, determine the interface state information of the routing path L2 corresponding to the logical offset 2 equal to the new offset 2. If the interface status information of the routing path L2 is empty as shown in fig. 4, the routing path L2 is taken as the routing path corresponding to the target port, and the interface status information of the routing path L2 in the routing path resource list is updated.
For example, when the new offset obtained after superposition exceeds the maximum logic offset corresponding to each routing path in the routing path resource list, error information is generated, and the interface position corresponding to the target port is judged again, for example, the initial offset corresponding to the target port is changed or the interface position corresponding to the target port is selected to be set on other sides of the integrated circuit.
And sequentially circulating the matching operation steps, and sequentially laying out the interface positions corresponding to the target ports in each routing layer corresponding to each side of the integrated circuit, so as to obtain the interface positions corresponding to each target port in the integrated circuit. Meanwhile, port information corresponding to the target port is given to interface state information of a routing path corresponding to the target port in the routing path resource list to obtain an updated routing path resource list, and then according to the updated routing path resource list, interfaces corresponding to the target port can be placed at corresponding positions on each side of the integrated circuit, for example, pins corresponding to the target port are welded at corresponding positions on each side of the integrated circuit, so that optimization of a physical implementation process of interface position layout in the integrated circuit is achieved.
Fig. 10 is a schematic flow chart of a layout method of interface positions of yet another integrated circuit provided in some embodiments of the present disclosure. It should be noted that, except for step S101 and step S102, steps S103 to S105 in the layout method of the interface positions of the integrated circuit shown in fig. 10 are substantially the same as or similar to steps S10 to S30 in the layout method of the interface positions of the integrated circuit shown in fig. 1, and the repetition is not repeated here.
For example, as shown in fig. 10, in some embodiments of the present disclosure, the layout method of the interface position of the integrated circuit further includes the following step S101.
Step S101: the destination port is determined based on signal logic of the integrated circuit.
For example, the destination port 111 for implementing external information interaction in the module 100 of the integrated circuit 10 may be determined according to signal logic of the integrated circuit 10, such as signal connection relationships, logic relationships, or transmission paths in the integrated circuit 10.
For example, as shown in fig. 10, in some embodiments of the present disclosure, the layout method of the interface position of the integrated circuit further includes the following step S102.
Step S102: and acquiring a routing path to be planned in the integrated circuit based on the layout of the integrated circuit.
For example, the signal connection channels to be planned or available in the integrated circuit 10 may be determined as the routing paths according to the signal logic of the integrated circuit 10, such as the signal connection relationship or logic relationship in the integrated circuit 10, and the physical location information of the routing paths may be determined in a subsequent step according to the determined signal connection channels and the actual physical layout of the signal connection channels in the integrated circuit 10.
It should be noted that, in the embodiments of the present disclosure, the flow of the layout method of the interface position of the integrated circuit provided in the foregoing embodiments of the present disclosure may include more or less operations, and these operations may be performed sequentially or performed in parallel. Although the flow of the layout method of interface locations of an integrated circuit described above includes a plurality of operations occurring in a particular order, it should be clearly understood that the order of the plurality of operations is not limited. The layout method of the interface positions of the integrated circuits described above may be performed once or a plurality of times according to a predetermined condition.
The present disclosure also provides an interface position layout device of an integrated circuit, where the interface position layout device of the integrated circuit can avoid a conflict between an interface position layout and a trace path resource available in the integrated circuit, for example, can avoid problems of physical distance violations, uneven distribution of trace path resources, repeated interface setting, and the like, and is favorable for making the layout of the interface position achieve an ideal physical implementation effect. Therefore, the accuracy and reliability of the layout of the interface positions of the integrated circuit can be improved, the time required for layout of the interface positions is reduced, the layout efficiency of the interface positions is improved, the development period of the physical design of the integrated circuit is shortened, and the physical realization efficiency of the integrated circuit is improved.
Fig. 11 is a schematic block diagram of an interface position layout apparatus of an integrated circuit provided in some embodiments of the present disclosure.
For example, as shown in fig. 11, the interface position layout apparatus 700 of the integrated circuit includes: a route path resource list generation unit 701, a physical location information determination unit 702, and a route path matching unit 703. The integrated circuit includes at least one module, each module including a plurality of ports including a target port to be set.
The routing path resource list generating unit 701 is configured to generate a routing path resource list based on routing paths to be planned in the integrated circuit. The routing path resource list includes physical location information of the routing paths. For example, the route path resource list generation unit 701 may perform step S10 in the layout method of the interface positions of the integrated circuit shown in fig. 1.
The physical location information determining unit 702 is configured to determine physical location information of the target port. For example, the physical location information determining unit 702 may perform step S20 in the layout method of the interface locations of the integrated circuit shown in fig. 1.
The routing path matching unit 703 is configured to determine, based on the routing path resource list, a routing path corresponding to the target port according to the physical location information of the target port, and obtain an interface location corresponding to the target port. For example, the trace path matching unit 703 may perform step S30 in the layout method of the interface positions of the integrated circuit shown in fig. 1.
For example, the interface position layout apparatus 700 of the integrated circuit further includes a routing path resource list updating unit. For example, the routing path resource list further includes interface state information of the routing path, and the routing path resource list updating unit is configured to add port information corresponding to the target port to the interface state information of the routing path corresponding to the target port in the routing path resource list, so as to update the routing path resource list for use in a subsequent layout operation.
For example, the interface position layout apparatus 700 of the integrated circuit further comprises a target port determination unit configured to determine a target port based on signal logic of the integrated circuit.
For example, the interface position layout apparatus 700 of an integrated circuit further includes a routing path acquisition unit configured to acquire routing paths to be planned in the integrated circuit based on the layout of the integrated circuit.
For example, the trace path matching unit 703 is further configured to match the target port with the trace path according to the physical location information of the target port and the physical location information of the trace path, and determine the trace path corresponding to the target port.
For example, the physical location information determining unit 702 is further configured to: determining physical position information of the routing path according to the physical layout structure of the integrated circuit; and determining physical location information of the target port according to the physical layout structure of the integrated circuit.
For example, the route path resource list generation unit 701, the physical location information determination unit 702, and the route path matching unit 703 include codes and programs stored in a memory; the processor may execute the codes and programs to implement some or all of the functions of the route path resource list generation unit 701, the physical location information determination unit 702, and the route path matching unit 703 as described above. For example, the route path resource list generating unit 701, the physical location information determining unit 702, and the route path matching unit 703 may be dedicated hardware devices for realizing some or all of the functions of the route path resource list generating unit 701, the physical location information determining unit 702, and the route path matching unit 703 described above. For example, the route path resource list generating unit 701, the physical location information determining unit 702, and the route path matching unit 703 may be one circuit board or a combination of a plurality of circuit boards for realizing the functions as described above. In an embodiment of the present application, the circuit board or the combination of the circuit boards may include: (1) one or more processors; (2) One or more non-transitory memories coupled to the processor; and (3) firmware stored in the memory that is executable by the processor.
The route path resource list generating unit 701 is configured to implement step S10 shown in fig. 1, the physical location information determining unit 702 is configured to implement step S20 shown in fig. 1, and the route path matching unit 703 is configured to implement step S30 shown in fig. 1. Thus, the specific description of the track path resource list generating unit 701 may refer to the related description of step S10 shown in fig. 1 in the above-described embodiment of the layout method of the interface positions of the integrated circuits, the specific description of the physical position information determining unit 702 may refer to the related description of step S20 shown in fig. 1 in the above-described embodiment of the layout method of the interface positions of the integrated circuits, and the specific description of the track path matching unit 703 may refer to the related description of step S30 shown in fig. 1 in the above-described embodiment of the layout method of the interface positions of the integrated circuits. In addition, the layout device of the interface position of the integrated circuit can achieve similar technical effects as the layout method of the interface position of the integrated circuit, and the description is omitted herein.
At least one embodiment of the present disclosure also provides an electronic device including a processor, a memory, and one or more computer program modules. One or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing the layout method of interface locations of an integrated circuit provided by any of the embodiments of the present disclosure.
Fig. 12 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure. As shown in fig. 12, the electronic device 300 includes a processor 310 and a memory 320. Memory 320 is used to store computer-executable instructions (e.g., one or more computer program modules) non-transitory. The processor 310 is configured to execute the computer-executable instructions that, when executed by the processor 310, perform one or more steps of the method of layout of the interface locations of the integrated circuit described above. The memory 320 and the processor 310 may be interconnected by a bus system and/or other forms of connection mechanisms (not shown).
For example, the processor 310 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture, or the like. The processor 310 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 300 to perform the desired functions.
For example, memory 320 may comprise any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer readable storage medium and executed by the processor 310 to implement various functions of the electronic device 300. Various applications and various data, as well as various data used and/or generated by the applications, etc., may also be stored in the computer readable storage medium.
It should be noted that, in the embodiments of the present disclosure, specific functions and technical effects of the electronic device 300 may refer to the above description about the layout method of the interface position of the integrated circuit and the layout apparatus of the interface position of the integrated circuit, which are not repeated herein.
Fig. 13 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 400 is suitable, for example, for implementing the layout method of the interface locations of the integrated circuit provided by the embodiments of the present disclosure. The electronic device 400 may be a terminal device or the like. It should be noted that the electronic device 400 shown in fig. 13 is merely an example, and does not impose any limitation on the functionality and scope of use of the embodiments of the present disclosure.
As shown in fig. 13, the electronic device 400 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 410, which may perform various suitable actions and processes according to a program stored in a Read Only Memory (ROM) 420 or a program loaded from a storage means 480 into a Random Access Memory (RAM) 430. In the RAM 430, various programs and data required for the operation of the electronic device 400 are also stored. The processing device 410, ROM 420, and RAM 430 are connected to each other by a bus 440. An input/output (I/O) interface 450 is also connected to bus 440.
In general, the following devices may be connected to the I/O interface 450: input devices 460 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 470 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, etc.; storage 480 including, for example, magnetic tape, hard disk, etc.; and communication device 490. The communication means 490 may allow the electronic device 400 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 13 shows an electronic device 400 having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided, and that electronic device 400 may alternatively be implemented or provided with more or fewer means.
For example, according to embodiments of the present disclosure, the layout method of interface positions of an integrated circuit described above may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program comprising program code for performing the method of layout of interface locations of an integrated circuit as described above. In such an embodiment, the computer program may be downloaded and installed from a network via communications device 490, or from storage 480, or from ROM 420. The functions defined in the layout method of the interface positions of the integrated circuits provided by the embodiments of the present disclosure may be implemented when the computer program is executed by the processing device 410.
Fig. 14 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. For example, as shown in fig. 14, the storage medium 500 may be a non-transitory computer-readable storage medium, and the one or more computer-readable instructions 501 may be stored non-transitory on the storage medium 500. For example, the computer readable instructions 501, when executed by a processor, may perform one or more steps in a layout method according to the interface locations of an integrated circuit described above.
For example, the storage medium 500 may be applied to the above-described electronic device, and for example, the storage medium 500 may include a memory in the electronic device.
For example, the storage medium may include a memory card of a smart phone, a memory component of a tablet computer, a hard disk of a personal computer, random Access Memory (RAM), read Only Memory (ROM), erasable Programmable Read Only Memory (EPROM), portable compact disc read only memory (CD-ROM), flash memory, or any combination of the foregoing, as well as other suitable storage media.
For example, the description of the storage medium 500 may refer to the description of the memory in the embodiment of the electronic device, and the repetition is omitted. The specific functions and technical effects of the storage medium 500 may refer to the above description of the layout method of the interface location of the integrated circuit and the layout apparatus of the interface location of the integrated circuit, and will not be repeated herein.
For the purposes of this disclosure, the following points are also noted:
(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.
(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.
The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.
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