CN113707663B - Semiconductor structure, three-dimensional memory and preparation method thereof - Google Patents
Semiconductor structure, three-dimensional memory and preparation method thereof Download PDFInfo
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- CN113707663B CN113707663B CN202110985861.XA CN202110985861A CN113707663B CN 113707663 B CN113707663 B CN 113707663B CN 202110985861 A CN202110985861 A CN 202110985861A CN 113707663 B CN113707663 B CN 113707663B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The application provides a preparation method of a three-dimensional memory, which comprises the following steps: forming a stacked structure including a channel structure on a substrate; forming a first insulating layer on a side of the stacked structure away from the substrate; etching the first insulating layer to form a first groove; etching the first insulating layer based on the first groove to expand the first groove into a second groove; etching the first insulating layer based on the second groove to form a first contact through hole penetrating through the first insulating layer along the direction perpendicular to the substrate, wherein the width of the first contact through hole is smaller than that of the second groove at one side close to the substrate; and filling the first contact through hole to form a channel contact. The three-dimensional memory and the preparation method thereof ensure that enough process windows exist when the channel contacts are aligned with the channel structure and the connecting contacts in an alignment way to a certain extent, save trial run time and improve the yield and production efficiency of products.
Description
Technical Field
The present application relates to the field of semiconductor design and fabrication, and more particularly, to a semiconductor structure, a structure of a three-dimensional memory (3D NAND), and a method of fabricating the same.
Background
Memory is an important device in modern information technology for storing data information. With the increasing demands of various electronic devices for integration and data storage density, it is increasingly difficult for a general two-dimensional memory device to meet the demands, and in this case, a three-dimensional memory has been developed.
Three-dimensional memories typically employ at least one stacked structure, which can reduce the unit cost of the memory cells while achieving extremely high data storage densities. However, as the number of stacked layers increases, overlay (OVL) alignment between layers is increasingly difficult to control, especially at the contact interconnection layer location, because of the need to form conductive connection through an interconnection process, once alignment deviation occurs, electrical connection is very likely to be unstable, stability of device operation is affected, and even a problem of disconnection occurs. Therefore, achieving a stable interconnection process, improving the stability of the memory is a problem that needs to be rapidly solved.
Disclosure of Invention
The present application provides a semiconductor structure, a three-dimensional memory, and a method of fabricating the same that at least partially solve the above-mentioned problems of the prior art.
According to one aspect of the present application, there is provided a method of manufacturing a three-dimensional memory, the method may include: forming a stacked structure including a channel structure on a substrate; forming a first insulating layer on a side of the stacked structure away from the substrate; etching the first insulating layer to form a first groove; etching the first insulating layer based on the first groove to expand the first groove into a second groove; etching the first insulating layer based on the second groove to form a first contact through hole penetrating through the first insulating layer along the direction perpendicular to the substrate, wherein the width of the first contact through hole is smaller than that of the second groove at one side close to the substrate; and filling the first contact through hole to form a channel contact.
In one embodiment of the present application, the method may further include: a second insulating layer including a connection contact is formed on a side of the first insulating layer away from the substrate, the connection contact and the channel contact being in contact with each other.
In one embodiment of the present application, the width of the channel contact may be greater than the width of the connection contact where the connection contact and the channel contact each other.
In one embodiment of the present application, the channel structure may include a channel plug, and the channel contact and the channel plug are in contact with each other.
In one embodiment of the present application, the width of the channel contact may be smaller than the width of the channel plug where the channel contact and the channel plug contact each other.
In one embodiment of the present application, etching the first insulating layer based on the first groove is isotropic etching.
In one embodiment of the present application, the isotropic etching may include at least one of wet etching and gas etching.
In one embodiment of the present application, before forming the first groove, the method may further include: forming a mask layer with a first opening on one side of the first insulating layer away from the substrate; and etching the first insulating layer based on the first opening to form a first groove.
In one embodiment of the present application, the material of the channel contact and the connection contact may be a conductive material.
Another aspect of the present application provides a semiconductor structure, which may include: a substrate; a stacked structure on the substrate, including dielectric layers and gate layers alternately stacked; a channel structure penetrating the laminated structure; and a first insulating layer located on a side of the stacked structure away from the substrate, comprising a channel contact, wherein the channel contact is in contact with the channel structure.
In one embodiment of the present application, the structure may further include: the second insulating layer is positioned on one side, far away from the substrate, of the first insulating layer and comprises a connecting contact, wherein the width of the top of the connecting contact is larger than that of the bottom, the top is one side, far away from the substrate, and the bottom is one side, close to the substrate.
In one embodiment of the present application, the width of the channel contact may be greater than the width of the connection contact where the connection contact and the channel contact each other.
In one embodiment of the present application, the channel structure may include a channel plug, and the channel contact and the channel plug are in contact with each other.
In one embodiment of the present application, the width of the channel contact may be smaller than the width of the channel plug where the channel contact and the channel plug contact each other.
In one embodiment of the present application, the material of the channel contact and the connection contact may be a conductive material.
In yet another aspect, the present application provides a three-dimensional memory device that may include any of the above semiconductor structures.
According to the semiconductor structure, the three-dimensional memory and the preparation method of the semiconductor structure, in the process of forming the first contact through hole, an isotropic etching process is added, so that the finally formed channel contact is small in width at the bottom and large in width at the top, and a sufficient process window is ensured to a certain extent when the channel contact is aligned with the channel structure and the connecting contact in an alignment manner. The width of the bottom of the channel contact is small, which is beneficial to the contact between the channel contact and the channel structure; the width at channel contact top is big, is favorable to channel contact and connection contact, has reduced channel contact and channel structure and connection contact to a certain extent and has overlapped the degree of difficulty, has saved the time of trial run (pi-run), has improved the yield and the production efficiency of product.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments, made with reference to the following drawings. Wherein:
FIG. 1 is a flow chart of a method for fabricating a three-dimensional memory 1000 according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a three-dimensional memory after forming a channel structure according to an embodiment of the present application;
fig. 3 is a schematic cross-sectional view of a semiconductor structure after forming a first recess according to an embodiment of the present application;
fig. 4 is a schematic cross-sectional view of a semiconductor structure after forming a second recess according to an embodiment of the present application;
fig. 5A is a schematic cross-sectional view of a semiconductor structure after forming a first contact via according to an embodiment of the present application;
fig. 5B is a schematic cross-sectional view of the semiconductor structure after forming a channel contact in accordance with an embodiment of the present application; and
fig. 6 is a schematic cross-sectional view of a semiconductor structure after formation of connection contacts in accordance with an embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed description are merely illustrative of exemplary embodiments of the application and are not intended to limit the scope of the application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
In the drawings, the size, dimensions and shape of elements have been slightly adjusted for convenience of description. The figures are merely examples and are not drawn to scale. As used herein, the terms "about," "approximately," and the like are used as terms of a table approximation, not as terms of a table degree, and are intended to account for inherent deviations in measured or calculated values that will be recognized by one of ordinary skill in the art. In addition, in this application, the order in which the processes of the steps are described does not necessarily indicate the order in which the processes occur in actual practice, unless explicitly defined otherwise or the context may be inferred.
It will be further understood that terms such as "comprises," "comprising," "includes," "including," "having," "containing," "includes" and/or "including" are open-ended, rather than closed-ended, terms that specify the presence of the stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features listed, it modifies the entire list of features rather than just modifying the individual elements in the list. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, embodiments and features of embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a flowchart of a method for manufacturing a three-dimensional memory 1000 according to an embodiment of the present application. As shown in fig. 1, the present application provides a method 1000 for preparing a three-dimensional memory, including:
step S110: forming a stacked structure including a channel structure on a substrate;
step S120: forming a first insulating layer on a side of the stacked structure away from the substrate;
step S130: etching the first insulating layer to form a first groove;
step S140: etching the first insulating layer based on the first groove to expand the first groove into a second groove;
step S150: etching the first insulating layer based on the second groove to form a first contact through hole penetrating the first insulating layer in the direction perpendicular to the substrate, wherein the width of the first contact through hole is smaller than that of the second groove at one side close to the substrate; and
step S160: the first contact via is filled to form a channel contact.
The specific process of each step of the above-described preparation method 1000 will be described in detail below with reference to fig. 2 to 6.
Fig. 2 is a schematic diagram of a three-dimensional memory after forming a channel structure according to an embodiment of the present application. As shown in fig. 2, a stack structure 120 is formed on a substrate 110, wherein the stack structure 120 includes dielectric layers 121 and sacrificial layers 122 alternately stacked. The substrate 110 may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. The material of the substrate 110 may also be a compound semiconductor. For example, the substrate 110 may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, or the like. It is noted that the substrate 110 of the present application may also be fabricated using at least one of the other semiconductor materials known in the art.
The stacked structure 120 may include a plurality of dielectric layers 121 and sacrificial layers 122 alternately stacked in a direction perpendicular to the substrate 110. The method of forming the stacked structure 120 may include a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof, which is not limited in this application. In the stacked structure 120, the thicknesses of the plurality of sacrificial layers 122 may be the same or different, and the thicknesses of the plurality of dielectric layers 121 may be the same or different, and the thicknesses of the dielectric layers 121 and the sacrificial layers 122 may be set according to specific process requirements. The sacrificial layer 122 may be removed and replaced with a conductive material in a subsequent process to form a gate layer, i.e., a word line. Alternatively, the material of the dielectric layer 121 may include silicon oxide, and the material of the sacrificial layer 122 may include silicon nitride. The greater the number of dielectric layers 121 and sacrificial layers 122 in the stacked structure 120, the higher the degree of integration.
The stacked structure 120 is etched to form a channel hole 130 (not shown) penetrating the stacked structure 120 and extending to the substrate 110, and a functional layer and a channel layer are sequentially formed on an inner wall of the channel hole 130 and an insulating material is filled in the channel hole 130 to form a channel structure 140. The channel holes 130 may be formed in the stacked structure 120 using, for example, a dry or wet etching process. The channel hole 130 may extend vertically in the direction of the substrate 110, thereby exposing a portion of the substrate 110. The functional layer 141 and the channel layer 142 may be sequentially formed on the sidewalls of the channel hole using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Among other things, the charge blocking layer, the charge trapping layer, and the tunneling layer may be referred to as a functional layer 141. The charge blocking layer is used for blocking outflow of stored charges of the charge trapping layer, and the charge trapping layer can pass through the tunneling layer through tunneling effect under the action of voltage so as to realize writing and erasing of memory data. Illustratively, the material of the charge blocking layer may be silicon oxide, the material of the charge trapping layer may be nitride, and the material of the tunneling layer may be oxide. In some embodiments, the channel structure may further include a channel plug 144, wherein the channel plug 144 is positioned on top of the channel structure, forming an electrical connection with the channel layer 142.
Fig. 3 is a schematic cross-sectional view of a semiconductor structure after forming a first recess according to an embodiment of the present application. In some embodiments, after forming the channel structure 140, a gate line slit (not shown) may be formed in the stacked structure 120 using, for example, a dry or wet etching process, and then the sacrificial layer 122 may be replaced with the gate layer 123 via the gate line slit. As shown in fig. 3, a first insulating layer 150 may be formed on a side of the stacked structure remote from the substrate using a thin film deposition process such as CVD, PVD, ALD or any combination thereof, and a mask layer (not shown) having a first opening may be formed on a side of the first insulating layer 150 remote from the substrate; and etching the first insulating layer 150 in a direction perpendicular to the substrate 110 based on the first opening to form a first groove 151. Wherein the first insulating layer may be etched using dry etching to form the first grooves 151, the first grooves 151 having a depth smaller than the thickness of the first insulating layer 150. Wherein the first insulating layer may comprise one or a combination stack of a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, a zirconium oxide layer.
Fig. 4 is a schematic cross-sectional view of a semiconductor structure after forming a second recess according to an embodiment of the present application. As shown in fig. 4, the first insulating layer 150 is isotropically etched based on the first grooves 151 to expand the first grooves 151 into the second grooves 152. Wherein the isotropic etching may include at least one of wet etching and gas etching, and the second grooves 152 of a desired depth and width may be formed by controlling an etching rate according to the requirements of the semiconductor structure.
Fig. 5A is a schematic cross-sectional view of a semiconductor structure after forming a first contact via according to an embodiment of the present application. As shown in fig. 5A, etching of the first insulating layer is continued based on the second grooves 152 to form first contact vias 153 penetrating the first insulating layer 150 in a direction perpendicular to the substrate. Wherein the first contact via 153 is located above the channel structure 140 and a width of the first contact via 153 is smaller than a width of the second recess 152 at a side close to the substrate 110. Fig. 5B is a schematic cross-sectional view of the semiconductor structure after forming a channel contact in accordance with an embodiment of the present application. As shown in fig. 5B, a conductive material is filled into the first contact via (C1 CH) 153, forming a channel contact 154, wherein the filled conductive material may include metallic tungsten and copper. Since the prior art is to ensure alignment of the channel contact 154 with the channel plug 144, the width of the bottom (side close to the substrate) of the channel contact 154 is relatively small. The channel contact 154 of the present application has a bottom width (the side closer to the substrate) that is smaller than the width of the top (the side farther from the substrate). The small bottom width of channel contact 154 facilitates alignment of the overlay between channel contact 154 and channel plug 144 where channel contact 154 and channel plug 144 contact each other, enabling electrical connection of channel contact 154 and channel plug 144, wherein the bottom width of channel contact 154 is less than the top width of channel plug 144.
Fig. 6 is a schematic cross-sectional view of a semiconductor structure after formation of connection contacts in accordance with an embodiment of the present application. As shown in fig. 6, the second insulating layer 160 may be formed on the side of the first insulating layer 150 remote from the substrate using a thin film deposition process such as CVD, PVD, ALD or any combination thereof, and the material of the second insulating layer 160 may be the same as or different from the first insulating layer 150, and the thickness of the second insulating layer 160 may be the same as or different from the first insulating layer 150. The second insulating layer is via etched over the second recess 152 and the via filled to form a connection contact 161 that contacts the channel contact 154. The channel contact 154 of the present application has a bottom width (the side closer to the substrate) that is smaller than the width of the top (the side farther from the substrate). The large width of the top of the channel contact 154 facilitates alignment of the channel contact 154 with the connection contact 161 where the channel contact 154 and the connection contact 161 contact each other, enabling electrical connection of the channel contact 154 with the connection contact 161, wherein the bottom width of the connection contact 161 is smaller than the top width of the channel contact 154.
In some embodiments, a metal layer is further included on a side of the second insulating layer 160 remote from the substrate, and the metal layer may be electrically connected to the connection contact 161.
In the self embodiment, the channel contact with small width at the bottom and large width at the top is formed by adding the isotropic etching process, so that enough process window is ensured to a certain extent when the channel contact is aligned with the channel structure and the connecting contact in an alignment manner. The width of the bottom of the channel contact is small, which is beneficial to the contact between the channel contact and the channel structure; the width of the top of the channel contact is large, which is beneficial for the contact between the channel contact and the connecting contact. Although the isotropic etching process is added, the difficulty in alignment of the channel contact with the channel structure and the connecting contact is reduced to a certain extent, the pilot run time is saved, and the yield and the production efficiency of products are improved.
In another aspect of the present application, a semiconductor structure is provided, which may include: a substrate; a stacked structure on the substrate, including dielectric layers and gate layers alternately stacked; a channel structure penetrating the stacked structure; and a first insulating layer located on a side of the stack structure away from the substrate, including a channel contact, wherein the channel contact is in contact with the channel structure.
In one embodiment of the present application, the semiconductor structure may further include a second insulating layer located on a side of the first insulating layer remote from the substrate, including a connection contact, wherein the connection contact and the channel contact are in contact with each other. The width of the channel contact is greater than the width of the connection contact where the connection contact and the channel contact each other.
In one embodiment of the present application, the channel structure includes a channel plug, and the channel contact and the channel plug are in contact with each other. The width of the channel contact is smaller than the width of the channel plug at the point where the channel contact and the channel plug contact each other.
In one embodiment of the present application, the material of the channel contact and the connection contact is a conductive material, such as metallic tungsten and copper.
The present application also provides a three-dimensional memory that may include any of the semiconductor structures described above.
Since the contents and structures referred to in the description of the preparation method 1000 above are fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto are not repeated.
The purpose, technical scheme and beneficial effects of the invention are further described in detail in the detailed description. It is to be understood that the above description is only of specific embodiments of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A method for manufacturing a three-dimensional memory, comprising:
forming a stacked structure including a channel structure on a substrate;
forming a first insulating layer on a side of the stacked structure away from the substrate;
forming a mask layer with a first opening on one side of the first insulating layer away from the substrate;
etching the first insulating layer based on the first opening to form a first groove;
isotropically etching the first insulating layer based on the first groove to expand the first groove into a second groove;
etching the first insulating layer based on the second groove to form a first contact through hole penetrating through the first insulating layer along the direction perpendicular to the substrate, wherein the width of the first contact through hole is smaller than that of the second groove at one side close to the substrate; and
and filling the first contact through hole to form a channel contact.
2. The method of manufacturing according to claim 1, wherein the method further comprises:
a second insulating layer including a connection contact is formed on a side of the first insulating layer away from the substrate, the connection contact and the channel contact being in contact with each other.
3. The method of manufacturing according to claim 2, wherein the width of the channel contact is larger than the width of the connection contact where the connection contact and the channel contact are in contact with each other.
4. The method of manufacturing according to claim 1, wherein the channel structure includes a channel plug, the channel contact and the channel plug being in contact with each other.
5. The method of manufacturing according to claim 4, wherein a width of the channel contact is smaller than a width of the channel plug at a point where the channel contact and the channel plug are in contact with each other.
6. The method of manufacturing according to claim 1, wherein the isotropic etching includes at least one of wet etching and gas etching.
7. The method of manufacturing of claim 2, wherein the material of the channel contact and the connection contact is a conductive material.
8. A semiconductor structure prepared by the method of preparing a three-dimensional memory according to any one of claims 1 to 7, comprising:
a substrate;
a stacked structure on the substrate, including dielectric layers and gate layers alternately stacked;
a channel structure penetrating the laminated structure; and
the first insulating layer is positioned on one side of the stacked structure far away from the substrate and comprises a channel contact, wherein the width of the top of the channel contact is larger than that of the bottom, the top is one side far away from the substrate, and the bottom is one side close to the substrate.
9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises:
and a second insulating layer, which is positioned on one side of the first insulating layer away from the substrate, and comprises a connecting contact, wherein the connecting contact and the channel contact are contacted with each other.
10. The semiconductor structure of claim 9, wherein a width of the channel contact is greater than a width of the connection contact where the connection contact and the channel contact each other.
11. The semiconductor structure of claim 8, wherein the channel structure comprises a channel plug, the channel contact and the channel plug being in contact with each other.
12. The semiconductor structure of claim 11, wherein a width of the channel contact is smaller than a width of the channel plug where the channel contact and the channel plug contact each other.
13. The semiconductor structure of claim 9, wherein the material of the channel contact and the connection contact is a conductive material.
14. A three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 8 to 13.
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