CN113707557A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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Abstract
本发明涉及一种半导体结构及其制备方法。该半导体结构的制备方法包括：提供基底，基底包括衬底、衬底介质层和全耗尽沟道层；其中，基底内形成有阱区；衬底介质层位于衬底上，且覆盖阱区；全耗尽沟道层层位于衬底介质层上；于全耗尽沟道层的上表面形成栅极结构；于全耗尽沟道层的上表面形成源极和漏极，源极与漏极分别位于栅极结构相对的两侧。上述半导体结构的制备方法，通过在阱区和浮栅之间形成全耗尽沟道层，可以减小半导体结构工作时的漏电流；同时，源极和漏极形成于全耗尽沟道层的上表面，源极和漏极的体积更大，与在基底中形成源极和漏极的方案相比，利用上述半导体结构的制备方法可以明显提高所得半导体结构的饱和电流。
The present invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure includes: providing a substrate, the substrate comprising a substrate, a substrate dielectric layer and a fully depleted channel layer; wherein, a well region is formed in the substrate; the substrate dielectric layer is located on the substrate and covers the well region ; The fully depleted channel layer is located on the substrate dielectric layer; the gate structure is formed on the upper surface of the fully depleted channel layer; the source electrode and the drain electrode are formed on the upper surface of the fully depleted channel layer, and the source electrode and the The drains are located on opposite sides of the gate structure, respectively. In the preparation method of the above semiconductor structure, by forming a fully depleted channel layer between the well region and the floating gate, the leakage current of the semiconductor structure during operation can be reduced; at the same time, the source electrode and the drain electrode are formed in the fully depleted channel layer. On the upper surface of the semiconductor structure, the volume of the source electrode and the drain electrode is larger. Compared with the scheme of forming the source electrode and the drain electrode in the substrate, the above-mentioned preparation method of the semiconductor structure can significantly improve the saturation current of the obtained semiconductor structure.
Description
Technical Field
The present invention relates to semiconductor devices and manufacturing thereof, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
A non-volatile memory (NVM) is a device essential to each semiconductor process, and can hold existing data when the chip is completely powered off, and read out the data when the chip is powered back again, so as to continue to use the data.
NOR flash is one of the two major non-volatile flash technologies currently on the market. The response speed of the conventional NOR flash memory cell is relatively slow, and with the continuous development of technologies such as artificial intelligence and big data, the conventional NOR flash memory cell is more and more difficult to meet the continuously improved computing requirements.
Disclosure of Invention
Accordingly, it is desirable to provide a semiconductor structure and a method for fabricating the same, which can solve the problems of the conventional NOR flash memory cell structure, such as large leakage current and large transistor-to-transistor variability.
A method of fabricating a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a substrate, a substrate medium layer and a fully depleted channel layer; wherein, a well region is formed in the substrate; the substrate dielectric layer is positioned on the substrate and covers the well region; the fully depleted channel layer is positioned on the substrate dielectric layer by layer; forming a gate structure on the upper surface of the fully depleted channel layer; and forming a source electrode and a drain electrode on the upper surface of the fully depleted channel layer, wherein the source electrode and the drain electrode are respectively positioned at two opposite sides of the grid structure.
According to the preparation method of the semiconductor structure, the fully depleted channel layer is formed between the well region and the floating gate, so that the leakage current of the semiconductor structure during working can be reduced; meanwhile, the source electrode and the drain electrode are formed on the upper surface of the fully depleted channel layer, the volume of the source electrode and the volume of the drain electrode are larger, and compared with the scheme of forming the source electrode and the drain electrode in the substrate, the saturation current of the obtained semiconductor structure can be obviously improved by using the preparation method of the semiconductor structure.
In one embodiment, the source and the drain are formed on the top surface of the fully depleted channel layer using an epitaxial process.
In one embodiment, the forming a gate structure on the top surface of the fully depleted channel layer includes: forming a tunneling dielectric material layer, a floating gate material layer, a control dielectric material layer and a control gate material layer which are sequentially stacked from bottom to top on the fully depleted channel layer; etching the control gate material layer, the control dielectric material layer, the floating gate material layer and the tunneling dielectric material layer to obtain a gate stack structure comprising the tunneling dielectric layer, the floating gate, the control dielectric layer and the control gate which are sequentially stacked from bottom to top; and forming grid side walls on two opposite sides of the grid laminated structure.
In one embodiment, the substrate dielectric layer comprises a buried oxide layer; the tunneling dielectric layer comprises an oxide layer, and the control dielectric layer comprises an oxide layer, a nitride layer and an oxide layer which are sequentially overlapped from bottom to top; the floating gate and the control gate each comprise a polysilicon gate.
In one embodiment, an orthographic projection of the gate structure on the upper surface of the fully depleted channel layer, an orthographic projection of the source on the upper surface of the fully depleted channel layer, and an orthographic projection of the drain on the upper surface of the fully depleted channel layer are all located within the upper surface of the fully depleted channel layer.
The application also discloses a semiconductor structure, including: the substrate comprises a substrate, a substrate dielectric layer and a fully depleted channel layer; wherein, a well region is formed in the substrate; the substrate dielectric layer is positioned on the substrate and covers the well region; the fully depleted channel layer is positioned on the substrate dielectric layer by layer; the grid structure is positioned on the upper surface of the fully depleted channel layer; the source electrode is positioned on the upper surface of the fully depleted channel layer and positioned on one side of the grid structure; and the drain electrode is positioned on the upper surface of the fully depleted channel layer and positioned on one side of the grid structure far away from the source electrode.
In one embodiment, the source and the drain are formed on the upper surface of the fully depleted channel layer by an epitaxial process.
In one embodiment, the gate structure comprises a gate stack structure located on an upper surface of the fully depleted channel layer; the grid laminated structure comprises a tunneling dielectric layer, a floating gate, a control dielectric layer and a control grid which are sequentially overlapped from bottom to top; and the grid side walls are positioned at two opposite sides of the grid laminated structure.
In one embodiment, the substrate dielectric layer comprises a buried oxide layer; the tunneling dielectric layer comprises an oxide layer, and the control dielectric layer comprises an oxide layer, a nitride layer and an oxide layer which are sequentially overlapped from bottom to top; the floating gate and the control gate each comprise a polysilicon gate.
In one embodiment, an orthographic projection of the gate structure on the upper surface of the fully depleted channel layer, an orthographic projection of the source on the upper surface of the fully depleted channel layer, and an orthographic projection of the drain on the upper surface of the fully depleted channel layer are all located within the upper surface of the fully depleted channel layer.
A fully depleted channel layer is arranged between the well region and the floating gate of the semiconductor structure, so that the leakage current of the semiconductor structure during working can be reduced; meanwhile, the source electrode and the drain electrode are arranged on the upper surface of the fully depleted channel layer, and compared with a semiconductor structure with the source electrode and the drain electrode formed in the substrate, the semiconductor structure has higher saturation current and higher response speed in practical application.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
Fig. 1 is a schematic cross-sectional structure diagram of a bulk silicon floating gate NOR flash memory cell.
Fig. 2 is a block flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.
Fig. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present application.
Fig. 4 is a cross-sectional structure of a semiconductor structure according to another embodiment of the present application.
The reference numbers illustrate: 1. a substrate; 11. a substrate; 12. a substrate dielectric layer; 13. a fully depleted channel layer; 21. tunneling through the dielectric layer; 22. a floating gate; 23. a control dielectric layer; 231. a first oxide layer; 232. a nitride layer; 233. a second oxide layer; 24. a control gate; 25. a gate side wall; 3. a source electrode; 4. and a drain electrode.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The application of non-volatile memory (NVM) is becoming more and more popular, and two non-volatile flash technologies currently in use on the market are NOR flash technology and NAND flash technology. In the NOR flash memory technology, the floating gate NOR flash memory cell has been widely used, and the schematic cross-sectional structure of the conventional floating gate NOR flash memory cell is shown in fig. 1.
The operation of a floating gate NOR flash memory cell will be briefly described to facilitate an understanding of the improvements of the present invention. The floating gate 22 in a floating gate NOR flash memory cell is primarily used to trap, store and release electrons. Wherein the trapped electrons and the released electrons correspond to a write operation and an erase operation of the NOR flash memory cell, respectively.
Specifically, when a NOR flash memory cell is erased, a high positive voltage may be applied to the well region to attract most of the electrons stored in the floating gate 22 into the well region, resulting in a transistor that is almost identical to a normal transistor. At this time, the first voltage VDD is applied to the control gate 24, and when the value of the first voltage VDD is greater than a threshold voltage vt (threshold voltage), the NOR flash memory cell is turned on, and a saturation current is generated between the source 3 and the drain 4. At this time, the read value of the NOR flash memory cell is 1.
When a write operation is performed on a NOR flash memory cell, a suitable positive voltage is first applied to the control gate 24 to attract a portion of the electrons from the well region into the floating gate 22. Since the floating gate 22 is provided with insulating layers above and below, this portion of electrons is latched into the floating gate 22, forming a negative pressure region. When the first voltage VDD is applied to the control gate 24, the negative pressure region formed by electrons in the floating gate 22 can counteract a portion of the first voltage VDD, so that the actual voltage on the gate structure is less than the threshold voltage Vt, and thus a current path cannot be formed between the source 3 and the drain 4, and a saturation current cannot be generated. At this time, the read value of the NOR flash memory cell is 0.
The above mechanism is the basic mechanism for the operation of the floating gate NOR flash memory cell, and the NOR flash memory cell shown in fig. 1 has the problems of large leakage current and large variability between NOR flash memory cells in practical application. When the variability between NOR flash memory cells is large, it cannot be guaranteed that the saturation currents generated by different NOR flash memory cells are uniform in magnitude. In applications with high requirements on accuracy, the floating gate NOR flash memory cell cannot meet the accuracy requirements. For example, for new computational requirements such as artificial intelligence, neural networks, etc., the variability between different transistors must be controlled within very strict criteria to avoid errors in the computation results.
Based on this, the present application provides a method for manufacturing a semiconductor structure, as shown in fig. 2, the method for manufacturing a semiconductor structure includes:
s11: providing a substrate, wherein the substrate comprises a substrate, a substrate dielectric layer and a fully depleted channel layer; wherein, a well region is formed in the substrate; the substrate dielectric layer is positioned on the substrate and covers the well region; the fully depleted channel layer is positioned on the substrate dielectric layer by layer;
s12: forming a grid structure on the upper surface of the fully depleted channel layer;
s13: and forming a source electrode and a drain electrode on the upper surface of the fully depleted channel layer, wherein the source electrode and the drain electrode are respectively positioned at two opposite sides of the grid structure.
A schematic cross-sectional structure of the semiconductor structure formed by the above method is shown in fig. 3. In step S11, the substrate dielectric layer 12 may include a buried oxide layer. The buried oxide layer not only can reduce the parasitic capacitance between the source 3 and the drain 4, but also can effectively inhibit electrons from flowing from the source 3 to the drain 4, thereby greatly reducing the leakage current. The buried oxide layer is combined with the fully depleted channel layer 13, so that a saturation current with higher consistency can be generated when the semiconductor structure is conducted, and the variability (variation) of the semiconductor structure is reduced. Taking the semiconductor structure as an example of a NOR flash memory cell, the NOR flash memory cell with the structure can be used in more sophisticated computing arrays by improving the uniformity of the NOR flash memory cell.
In steps S12 and S13, the gate, the source electrode 3, and the drain electrode 4 are all formed on the upper surface of the fully depleted channel layer 13, as shown in fig. 3. Wherein, the source electrode 3 and the drain electrode 4 are respectively positioned at two opposite sides of the grid electrode. Specifically, the source electrode 3 and the drain electrode 4 may be fabricated by an epitaxial process, which aims to increase the saturation current. With the continuous shrinkage of semiconductor structures, the saturation current is also continuously reduced, and the switching speed of the device is further reduced. In addition, in the present embodiment, the saturation current is further reduced due to the introduction of the buried oxide layer and the fully depleted channel. The epitaxial source electrode 3 and the epitaxial drain electrode 4 are prepared through an epitaxial process, so that the saturation current in a channel can be greatly increased when the source electrode 3 and the drain electrode 4 are conducted, and the switching speed of the semiconductor structure is increased.
In one embodiment, the step of forming a gate structure on the upper surface of the fully depleted channel layer 13 includes:
s121: forming a tunneling dielectric material layer (not shown), a floating gate material layer (not shown), a control dielectric material layer (not shown) and a control gate material layer (not shown) which are sequentially stacked from bottom to top on the fully depleted channel layer 13;
s122: etching the control gate material layer, the control dielectric material layer, the floating gate material layer and the tunneling dielectric material layer to obtain a gate laminated structure comprising a tunneling dielectric layer 21, a floating gate 22, a control dielectric layer 23 and a control gate 24 which are sequentially laminated from bottom to top;
s123: and forming gate spacers 25 on two opposite sides of the gate stack structure.
The tunnel dielectric layer 21 may include an oxide layer, such as a silicon dioxide layer. The floating gate 22 and the control gate 24 may comprise polysilicon gates. The control dielectric layer 23 may include an oxide layer, such as a silicon dioxide layer, and may also include a first oxide layer 231, a nitride layer 232, and a second oxide layer 233, which are stacked in sequence from bottom to top, as shown in fig. 4.
As an example, the semiconductor structure obtained by the above method may comprise a floating gate NOR flash memory cell. The floating gate 22 is located between the two dielectric layers, and when electrons enter the floating gate 22 through a tunneling effect, the electrons can be relatively stably retained in the floating gate 22 to form a negative voltage region, so that a voltage applied by the control gate 24 is offset to a certain extent. Thus, the floating gate 22 can control the on and off of the floating gate NOR flash memory cell together with the control gate 24.
In one embodiment, the orthographic projection of the gate structure on the upper surface of the fully depleted channel layer 13, the orthographic projection of the source 3 on the upper surface of the fully depleted channel layer 13, and the orthographic projection of the drain 4 on the upper surface of the fully depleted channel layer 13 are all located within the upper surface of the fully depleted channel layer 13.
Another aspect of the present application further discloses a semiconductor structure, as shown in fig. 3, including a substrate 1, where the substrate 1 includes a substrate 11, a substrate dielectric layer 12, and a fully depleted channel layer 13; wherein, a well region is formed in the substrate 1; the substrate dielectric layer 12 is positioned on the substrate 11 and covers the well region; the fully depleted channel layer 13 is positioned on the substrate medium layer 12; a gate structure on an upper surface of the fully depleted channel layer 13; the source electrode 3 is positioned on the upper surface of the fully depleted channel layer 13 and positioned on one side of the grid structure; and the drain electrode 4 is positioned on the upper surface of the fully depleted channel layer 13 and positioned on one side of the gate structure far away from the source electrode 3.
As an example, the semiconductor structure in the present embodiment may be a NOR flash memory cell. The substrate medium layer 12 is arranged between the substrate 11 and the fully depleted channel layer 13, so that an electronic channel between the source electrode 3 and the drain electrode 4 is limited in the fully depleted channel layer 13, electron transfer between the source electrode 3 and the drain electrode 4 through a well region is avoided, and leakage current is greatly reduced. By way of example, the substrate dielectric layer 12 may include a buried oxide layer. The buried oxide layer may also reduce the parasitic capacitance between the source 3 and the drain 4.
The fully depleted channel layer 13 does not require a doping process and the depletion region fills the channel layer. The fully depleted channel layer 13 is combined with the substrate medium layer 12, and a channel of saturation current is limited in the fully depleted channel layer 13 under the condition that the semiconductor structure is conducted, so that the consistency of the semiconductor structure is greatly improved, and the variability among different semiconductor structures is reduced. With the increasing demand for computer computing power, consistency between computing units is becoming more and more important. For example, in the field of neural networks, when memory computing technology is used for computing, different memory computing units must have high consistency so as to avoid error accumulation and calculation result errors in multi-bit addition computing.
In the present embodiment, the source 3 and the drain 4 are not formed in the substrate 1 as in the conventional transistor, but are formed on the upper surface of the substrate 1, as shown in fig. 3. Specifically, the source electrode 3 and the drain electrode 4 may be formed on the upper surface of the fully depleted channel layer 13 through an epitaxial process to obtain the epitaxial source electrode 3 and the epitaxial drain electrode 4. By forming the epitaxial source 3 and the epitaxial drain 4 on the upper surface of the fully depleted channel layer 13, the saturation current in the channel can be greatly increased when the transistor is turned on, and the switching speed of the semiconductor structure can be increased.
In one embodiment, the gate structure includes a gate stack structure on an upper surface of the fully depleted channel layer 13; the grid laminated structure comprises a tunneling dielectric layer 21, a floating gate 22, a control dielectric layer 23 and a control grid 24 which are sequentially overlapped from bottom to top; and the gate side walls 25 are positioned at two opposite sides of the gate laminated structure.
In particular, as shown in fig. 3, the floating gate sidewall spacer isolates the source 3 from the gate stack and also isolates the drain 4 from the gate stack. The gate stack structure comprises four different functional layers. Wherein, the tunnel dielectric layer 21 at the bottom contacting with the fully depleted channel layer 13, when an external force is applied, the electrons in the well region can penetrate through the tunnel dielectric layer 21 and enter the floating gate 22. The floating gate 22 is located above the tunneling dielectric layer 21 and is used for trapping electrons and storing the electrons under certain conditions or releasing the electrons under external force. For example, when a sufficiently large positive voltage is applied to the well region, most of the electrons in the floating gate 22 are attracted to the well region. The upper surface of the floating gate 22 is provided with a control dielectric layer 23 for separating the floating gate 22 from the control gate 24. The uppermost of the gate stack is a control gate 24. the control gate 24 can be understood as the gate of a typical transistor, which is connected to a voltage source for providing a turn-on voltage for the semiconductor structure.
As an example, the tunnel dielectric layer 21 may include an oxide layer, the control dielectric layer 23 may include an oxide layer, a nitride layer 232 and an oxide layer stacked in sequence from bottom to top, and the floating gate 22 and the control gate 24 may each include a polysilicon gate. Specifically, the control dielectric layer 23 may include a first oxide layer 231, a nitride layer 232 and a second oxide layer 233 stacked in sequence from bottom to top, as shown in fig. 4
In one embodiment, the orthographic projection of the gate structure on the upper surface of the fully depleted channel layer 13, the orthographic projection of the source 3 on the upper surface of the fully depleted channel layer 13, and the orthographic projection of the drain 4 on the upper surface of the fully depleted channel layer 13 are all located within the upper surface of the fully depleted channel layer 13.
In one embodiment, the semiconductor structure may include a floating gate NOR flash memory cell, wherein the floating gate NOR flash memory cell combines with an FDSOI process to form a buried oxide layer and a fully depleted channel layer 13 above a substrate 11, thereby reducing a leakage current of the NOR flash memory cell and allowing a conduction current generated when the NOR flash memory cell is turned on to have a higher uniformity. Meanwhile, the epitaxial source electrode 3 and the epitaxial drain electrode 4 are arranged on the upper surface of the fully depleted channel layer 13, so that the saturation current of the NOR unit is increased, and the response speed of the NOR unit in the calculation process is improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
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