CN113707008A

CN113707008A - Display panel and splicing display device

Info

Publication number: CN113707008A
Application number: CN202011476864.2A
Authority: CN
Inventors: 林俊贤
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2020-05-22
Filing date: 2020-12-15
Publication date: 2021-11-26
Anticipated expiration: 2040-12-15
Also published as: CN113707008B

Abstract

The present disclosure provides a display panel and a tiled display device. The display panel comprises a substrate, an array circuit and a power supply circuit. The substrate has a top surface, a bottom surface, and a side surface between the top surface and the bottom surface. The array circuit is disposed on the top surface. Power is supplied to the array circuit by a power supply circuit. The power supply circuit has a power input terminal. The power input terminals correspond to the at least two discrete terminals. At least two dispersion terminals are disposed on the side surface and disperse power to different portions of the array circuit.

Description

Display panel and splicing display device

Technical Field

The present disclosure relates to a display panel and a tiled display device, and more particularly, to a display panel or a tiled display device capable of improving the problem of uneven brightness.

Background

Electronic devices or tiled electronic devices have been widely used in mobile phones, televisions, monitors, tablet computers, vehicle displays, wearable devices, and desktop computers. With the rapid development of electronic devices, the quality requirements of electronic devices are higher, and how to uniformly transmit electronic devices to an active region (e.g., a display region) has become one of the research projects.

Disclosure of Invention

According to an embodiment of the present disclosure, a display panel includes a substrate, an array circuit, and a power supply circuit. The substrate has a top surface, a bottom surface, and a side surface between the top surface and the bottom surface. The array circuit is disposed on the top surface. Power is supplied to the array circuit by a power supply circuit. The power supply circuit has power input terminals corresponding to the at least two discrete terminals. At least two dispersion terminals are disposed on the side surface and disperse power to different portions of the array circuit.

According to an embodiment of the present disclosure, a tiled display device includes a plurality of display panels, each of which includes a substrate, an array circuit, and a power supply circuit. The substrate has a top surface, a bottom surface, and a side surface between the top surface and the bottom surface. The array circuit is disposed on the top surface. Power is supplied to the array circuit by a power supply circuit. The power supply circuit has power input terminals corresponding to the at least two discrete terminals. At least two dispersion terminals are disposed on the side surface and disperse power to different portions of the array circuit.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1A is a top perspective view of a display panel according to an embodiment of the disclosure;

FIG. 1B is a bottom perspective view of the display panel of FIG. 1A;

FIG. 2A is a schematic bottom view of a display panel according to another embodiment of the present disclosure;

FIG. 2B is a cross-sectional view of the display panel of FIG. 2A along the line A-A';

FIG. 3 is a bottom perspective view of a display panel according to another embodiment of the present disclosure;

FIG. 4A is a schematic bottom view of a display panel according to another embodiment of the present disclosure;

fig. 4B is an enlarged schematic view of the region R of the display panel of fig. 4A.

Description of the reference numerals

10. 10a, 10b, 10 c: a display panel;

100: a substrate;

102: a top surface;

104: a bottom surface;

106a, 106b, 106c, 106 d: a side surface;

110: an array circuit;

111. 111 a: a power supply line;

1111. 1111 a: a first portion;

1112. 1112 a: a second portion;

112: a signal line;

120. 120 a: a power supply circuit;

121. 121 ', 121 a': a power input terminal;

1211: a first end;

1212: a second end;

122. 122 ', 122 a', 123 ', 123 a': a dispersion terminal;

1221. 1231: a fifth end;

1222. 1232: a sixth terminal;

124. 124 ', 124 a': a first conductive line;

1241. 1251: a third end;

1242. 1252: a fourth end;

125. 125 ', 125 a': a second conductive line;

125A, 125A ', 125 aA': main line

125B, 125B ', 125 aB': branching part

126. 126 ', 126 a': a power supply test pad;

130. 130 a: a signal supply circuit;

131. 131 a: a signal input terminal;

132. 132 a: a transmission terminal;

133. 133 a: a third conductive line;

134. 134 a: a signal test pad;

140: an insulating layer;

A-A': a section line;

c1, C2: an electronic component;

GE: a gate electrode;

l1, L2, L3: a light emitting element;

r: an area;

SD 1: a source electrode;

SD 2: a drain electrode;

t1: a transistor;

w1, W2: a width;

x, Y, Z: and (4) direction.

Detailed Description

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which it is noted that, for the sake of clarity and brevity of the drawings, the various drawings in the present disclosure depict only some of the electronic devices and are not necessarily drawn to scale. In addition, the number and size of the elements in the figures are merely illustrative and are not intended to limit the scope of the present disclosure.

In the following specification and claims, the words "comprise", "comprising", "includes" and "including" are open-ended words that should be interpreted as meaning "including, but not limited to …".

Certain terms are used throughout the description and following claims to refer to particular elements. It will be understood by those skilled in the art that electronic device manufacturers may refer to elements by different names, and that this document does not intend to distinguish between elements that are functionally the same, but that have different names. When the terms "comprises," "comprising," and/or "having" are used in this specification, they specify the presence of stated features, regions, steps, operations, and/or elements, but do not preclude the presence or addition of one or more other features, regions, steps, operations, elements, and/or groups thereof.

When an element such as a layer or region is referred to as being "on" or extending "onto" another element (or variations thereof), it can be directly on or extend directly onto the other element or intervening elements may also be present. On the other hand, when an element is referred to as being "directly on" or extending "directly onto" another element (or variations thereof), there are no intervening elements present between the two. Also, when an element is referred to as being "coupled" to another element (or variations thereof), it can be directly connected to the other element or be indirectly connected (e.g., electrically connected) to the other element through one or more elements.

As used herein, the term "about" or "substantially" generally means within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The amounts given herein are approximate, that is, the meanings of "about" and "substantially" may be implied without specifically stating "about" or "substantially". Furthermore, the term "range between a first value and a second value" means that the range includes the first value, the second value, and other values therebetween.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, layers and/or sections, these elements, layers and/or sections should not be limited by these terms, and these terms are only used to distinguish one element, layer and/or section from another. Thus, a first element, layer or section discussed below could be termed a second element, layer or section without departing from the teachings of some embodiments of the present disclosure. In addition, for the sake of brevity, the terms "first", "second", and the like may not be used in the description to distinguish different elements. The first element and/or the second element recited in the claims may be construed as any element in the specification that conforms to the recitations therein without departing from the scope defined by the appended claims.

In the present disclosure, the thickness, length and width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but not limited thereto. In addition, there may be some error in any two values or directions for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the technical solutions provided in the following different embodiments can be used alternatively, combined or mixed with each other to form another embodiment without departing from the spirit of the present disclosure.

In the present disclosure, the length and the width may be measured by an optical microscope, and the thickness may be measured by a cross-sectional image of an electron microscope, but not limited thereto. In addition, there may be some error in any two values or directions for comparison.

The electronic device of the present disclosure may include a display device, an antenna device (e.g., a liquid crystal antenna), a sensing device, a light-emitting device, a touch device, a curved device, a device with any shape, a bendable device, a flexible device, a splicing device, or a combination thereof, but is not limited thereto. The electronic device may include a light-emitting diode (LED), a liquid crystal, a phosphor, a Quantum Dot (QD), other suitable materials, or a combination of the foregoing, but is not limited thereto. The light emitting diode may include, but is not limited to, an Organic Light Emitting Diode (OLED), an inorganic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED or a quantum dot light emitting diode (QLED, QDLED), other suitable LED types, or any combinations thereof. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, a shelf system …, and the like. The present disclosure will be described with reference to a display device, but not limited thereto.

It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure. Features of the various embodiments may be combined and matched as desired, without departing from the spirit or ambit of the invention.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1A is a top perspective view of a display panel according to an embodiment of the disclosure. Fig. 1B is a bottom perspective view of the display panel of fig. 1A.

Referring to fig. 1A and fig. 1B, the display panel 10 of the present embodiment may include a substrate 100, an array circuit 110,

power supply circuits

120 and 120a, and a plurality of light emitting devices (e.g., light emitting devices L1, L2, and L3), and fig. 1A schematically illustrates 3 light emitting devices, but not limited thereto. The substrate 100 may have a top surface 102, a bottom surface 104, and side surfaces (e.g.,

side surfaces

106a, 106b, 106c, 106d) between the top surface 102 and the bottom surface 104, and fig. 1A schematically illustrates 4 side surfaces, but not limited thereto. Such side surfaces (e.g.,

side surfaces

106a, 106b, 106c, 106d) connect, for example, between the top surface 102 and the bottom surface 104. For example, side surface 106a is opposite side surface 106b, and side surface 106c is opposite side surface 106 d. In some embodiments, the substrate 100 may include a rigid substrate, a flexible substrate, or a combination thereof. The material of the substrate 100 may include glass, quartz, sapphire (sapphire), ceramic, Polycarbonate (PC), Polyimide (PI), polyethylene terephthalate (PET), other suitable substrate materials, or a combination thereof, but is not limited thereto.

Referring to fig. 1A, the array circuit 110 may be disposed on the top surface 102 of the substrate 100 for electrically connecting the power supply circuit (e.g., the power supply circuit 120a) and the light emitting devices (e.g., the light emitting devices L1, L2, L3). In some embodiments, the array circuit 110 may include, but is not limited to, a power line 111a, a signal line 112 (such as, but not limited to, a scan line or a data line), a transistor T1, and/or a capacitor (not shown). In some embodiments, the transistor T1 may include, but is not limited to, a gate GE, a source SD1, and a drain SD 2. In other embodiments, the positions of the source SD1 and the drain SD2 can be reversed. In some embodiments, the power line 111 may be electrically connected to a plurality of transistors T1 (e.g., but not limited to, the source SD1 of the transistor T1). In some embodiments, the different signal lines 112 may be electrically connected to the corresponding transistors T1 (e.g., the gate GE of the transistor T1), and the different transistors T1 (e.g., the drain SD2 of the transistor T1) may be electrically connected to the corresponding light emitting devices (e.g., the light emitting devices L1, L2, and L3), respectively, but are not limited thereto. In some embodiments, the power line 111a may be electrically connected to the other end of the light emitting devices (e.g., the light emitting devices L1, L2, and L3), but is not limited thereto. In some embodiments, the power line 111 and the power line 111a respectively transmit different signals. For example, the power line 111 may be used to transfer a first signal (e.g., VDD), and the power line 111a may be used to transfer a second signal (e.g., Vss), but is not limited thereto. In some embodiments (referring to fig. 1A and 1B), the power supply circuit 120 and/or the power supply circuit 120a may be electrically connected to a plurality of light emitting elements (e.g., light emitting elements L1, L2, L3) through the array circuit 110. Therefore, the power from the

power supply circuits

120, 120a can be transmitted to the light emitting elements (e.g., the light emitting elements L1, L2, L3) to drive the light emitting elements to emit light. It should be noted that the connection relationship among the components of the array circuit 110 or the size (or shape) of the components are merely illustrative, and other connection relationships or sizes (or shapes) of the components can be designed according to the requirement. For example, the shapes of the

power lines

111 and 111a are only illustrative.

Referring to fig. 1A and 1B, the power supply circuit 120 may be disposed on the bottom surface 104 and the side surface 106a of the substrate 100. The material of the lines in the power supply circuit 120 may include a transparent conductive material or a non-transparent conductive material, such as indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, tin oxide, a metal material (e.g., aluminum, molybdenum, copper, silver, etc.), other suitable materials, or a combination thereof, but is not limited thereto. In some embodiments, the power supply circuit 120 may have a power input terminal 121 and at least two discrete terminals (e.g., the discrete terminal 122 and the discrete terminal 123), and the power input terminal 121 corresponds to the at least two discrete terminals (e.g., the discrete terminal 122 and the discrete terminal 123). In some embodiments, the power supply circuit 120 may have a first conductive line 124 and a second conductive line 125, but not limited thereto. In some embodiments, the power supply circuit 120a may have a power input terminal 121a, at least two discrete terminals (e.g., the discrete terminal 122a and the discrete terminal 123a), a first conductive line 124a, and a second conductive line 125a, but not limited thereto, the power input terminal 121a corresponds to the at least two discrete terminals (e.g., the discrete terminal 122a and the discrete terminal 123 a). In some embodiments, the power input terminal 121 (or the power input terminal 121a), the first conductive line 124 (or the first conductive line 124a), and the second conductive line 125 (or the second conductive line 125a) may be disposed on the bottom surface 104 of the substrate 100, respectively, and the first conductive line 124 (or the first conductive line 124a) and the second conductive line 125 (or the second conductive line 125a) may be formed of the same film layer. In some embodiments, at least two discrete terminals (e.g., the

discrete terminals

122 and 123, or the

discrete terminals

122a and 123a) may be respectively disposed on (or dispersed in) a side surface (e.g., the side surface 106a) of the substrate 100.

In some embodiments, the power input terminal 121 may have a first end 1211 and a second end 1212 opposite to each other, the first conductive line 124 has a third end 1241 and a fourth end 1242 opposite to each other, and the second conductive line 125 has a third end 1251 and a fourth end 1252 opposite to each other. At least two dispersion terminals (e.g., the dispersion terminal 122 and the dispersion terminal 123) may be dispersed on the side surface 106a of the substrate 100, the dispersion terminal 122 has a fifth end 1221 and a sixth end 1222 opposite to each other, and the dispersion terminal 123 has a fifth end 1231 and a sixth end 1232 opposite to each other. In some embodiments, the first end 1211 of the power input terminal 121 may be electrically connected to the third end 1241 of the first conductive line 124, and the second end 1212 of the power input terminal 121 may be electrically connected to the third end 1251 of the second conductive line 125. The fourth end 1242 of the first conductive line 124 may be electrically connected to the fifth end 1221 of the discrete terminal 122, and the fourth end 1252 of the second conductive line 125 may be electrically connected to the fifth end 1231 of the discrete terminal 123, but is not limited thereto. In some embodiments, the sixth end 1222 of the discrete terminal 122 may be electrically connected to the first portion 1111 of the power line 111 of the array circuit 110, and the sixth end 1232 of the discrete terminal 123 may be electrically connected to the second portion 1112 of the power line 111 of the array circuit 110. That is, the third end 1241 and the fourth end 1242 of the first conductive wire 124 may be electrically connected to the power input terminal 121 and the discrete terminal 122, respectively, and the third end 1251 and the fourth end 1252 of the second conductive wire 125 may be electrically connected to the power input terminal 121 and the discrete terminal 123, respectively. The fifth end 1221 and the sixth end 1222 of the discrete terminal 122 may be electrically connected to the first conductive line 124 and the first portion 1111 of the power line 111 of the array circuit 110, respectively, and the fifth end 1231 and the sixth end 1232 of the discrete terminal 123 may be electrically connected to the second conductive line 125 and the second portion 1112 of the power line 111 of the array circuit 110, respectively, that is, at least two discrete terminals (e.g., the discrete terminal 122 and the discrete terminal 123) may be electrically connected to different portions (e.g., the first portion 1111 and the second portion 1112 of the power line 111) of the array circuit 110, respectively. In some embodiments, at least two of the distribution terminals can distribute the power to different portions of the array circuit 110 (i.e., the first portion 1111 and the second portion 1112 of the power line 111). In some embodiments, the power input terminal 121 may correspond to or be electrically connected to at least two discrete terminals (e.g., the discrete terminal 122 and the discrete terminal 123), and the power input terminal 121 may be electrically connected to two discrete terminals (e.g., the discrete terminal 122 and the discrete terminal 123) of the at least two discrete terminals through the first wire 124 and the second wire 125, respectively, and electrically connected to different portions (i.e., the first portion 1111 and the second portion 1112) of the power line 111 and/or the light emitting devices (e.g., the light emitting devices L1, L2, L3) through the discrete terminals, but is not limited thereto. In some embodiments, the first portion 1111 and the second portion 1112 can be electrically connected to each other. In some embodiments, first portion 1111 and second portion 1112 may be formed from the same conductive layer.

In some embodiments, a power supply circuit (e.g., the power supply circuit 120 or the power supply circuit 120a) may, for example, receive a current provided by an electronic element (e.g., the electronic element C1 or the electronic element C2), and power is provided to the array circuit 110 through the power supply circuit (e.g., the power supply circuit 120 or the power supply circuit 120 a). The electronic component C1 or the electronic component C2 may include a chip or a flexible circuit board (FPC), but is not limited thereto. Specifically, in some embodiments, the power input terminal (e.g., the power input terminal 121 or the power input terminal 121a) of the power supply circuit (e.g., the power supply circuit 120 or the power supply circuit 120a) can distribute the power inputted or provided by the corresponding electronic component (e.g., the electronic component C1 or the electronic component C2) to the first conductive line (e.g., the first conductive line 124 or the first conductive line 124a) and the second conductive line (e.g., the second conductive line 125 or the second conductive line 125 a). Then, the first conductive wire (e.g., the first conductive wire 124 or the first conductive wire 124a) and the second conductive wire (e.g., the second conductive wire 125 or the second conductive wire 125a) respectively transmit power to at least two corresponding distributed terminals, such as the distributed terminal 122 (or the distributed terminal 122a) and the distributed terminal 123 (or the distributed terminal 123 a). Then, the power is respectively distributed to different parts of the array circuit 110, such as a first part (e.g., the first part 1111 or the first part 1111a) and a second part (e.g., the second part 1112 or the second part 1112a) of the array circuit 110 through at least two distribution terminals. For example, the power input terminals (e.g., the power input terminal 121 or the power input terminal 121a) may correspond to two distributed terminals, respectively, such that the two distributed terminals may be divided into two parts, for example, by a ratio of 1: a ratio of 1 divides power to different portions of the array circuit 110, such as, but not limited to, a first portion (first portion 1111 or first portion 1111a) and a second portion (second portion 1112 or second portion 1112a) of the array circuit 110. In other words, a discrete terminal (e.g., discrete terminal 122 or discrete terminal 122a) may substantially deliver 1/2 power (or current) to a first portion (e.g., first portion 1111 or first portion 1111a) of array circuitry 110, and another discrete terminal (e.g., discrete terminal 123 or discrete terminal 123a) may substantially deliver 1/2 power (or current) to a second portion (e.g., second portion 1112 or second portion 1112a) of array circuitry 110.

In some embodiments, the discrete terminals 122 are, for example, adjacent to the side surface 106c of the substrate 100, the discrete terminals 123 are far from the side surface 106c of the substrate 100, and other terminals (for example, the transmission terminals 132) are further disposed between the discrete terminals 122 and the discrete terminals 123, so that the discrete terminals 122 and the discrete terminals 123 can be dispersed on different areas of the side surface 106a of the substrate 100, but not limited thereto. In some embodiments, the discrete terminals 122a are, for example, adjacent to the side surface 106d of the substrate 100, the discrete terminals 123a are far from the side surface 106d of the substrate 100, and other wires (e.g., the transmission terminals 132a) are further disposed between the discrete terminals 122a and the discrete terminals 123a, so that the discrete terminals 122 and the discrete terminals 123 can be dispersed on different areas of the side surface 106a of the substrate 100, but not limited thereto. As described above, since the dispersion terminal (e.g., the dispersion terminal 122 or the dispersion terminal 122a) and the other dispersion terminal (e.g., the dispersion terminal 123 or the dispersion terminal 123a) can be dispersed on different regions of the side surface 106a of the substrate 100, the power (or current) transmitted or provided by the power supply circuit (e.g., the power supply circuit 120 or the power supply circuit 120a) can be uniformly dispersed to the first portion (e.g., the first portion 1111 or the first portion 1111a) and the second portion (e.g., the second portion 1112 or the second portion 1112a) of the array circuit 110 through at least two electrically connected or corresponding dispersion terminals, respectively, so that the power (or current) can be uniformly distributed in the array circuit 110, the power can be more uniformly transmitted to different light emitting elements (such as the light emitting elements L1, L2, and L3) to improve the brightness uniformity of the light emitted by the light emitting elements. Therefore, compared with the conventional electronic device, since power may be transmitted through a single circuit path, a voltage drop (IR drop) problem is likely to occur, which causes a problem of non-uniform brightness of the light emitting device. The electronic device of the embodiment can provide at least two circuit paths to transmit power (or current) by at least one circuit path, thereby improving the problem of uneven brightness of the light-emitting element or voltage drop.

With continued reference to fig. 1A and 1B, in some embodiments, the power supply circuit 120 and the power supply circuit 120a are disposed adjacent to each other on the bottom surface 104. In some embodiments, the power input terminal 121 of the power supply circuit 120 is, for example, far away from the power supply circuit 120a, and the power input terminal 121a of the power supply circuit 120a is, for example, far away from the power supply circuit 120, but is not limited thereto. In some embodiments, the power input terminal 121, the first conductive line 124 and the discrete terminal 122 of the power supply circuit 120 are adjacent to the side surface 106c of the substrate 100. In some embodiments, the discrete terminals 123 of the power supply circuit 120 are distant from the side surface 106c of the substrate 100. In some embodiments, the power input terminal 121a, the first conductive line 124a and the discrete terminal 122a of the power supply circuit 120a are adjacent to the side surface 106d of the substrate 100. In some embodiments, the discrete terminals 123a of the power supply circuit 120a are away from the side surface 106d of the substrate 100.

Referring to fig. 1B, the display panel 10 of the present embodiment further includes a signal supply circuit (e.g., the signal supply circuit 130 or the signal supply circuit 130a) disposed on the bottom surface 104 of the substrate 100. The signal supply circuit (e.g., the signal supply circuit 130 or the signal supply circuit 130a) may, for example, receive a signal (e.g., a scan signal or a data signal, but not limited thereto) provided by an electronic element (e.g., the electronic element C1 or the electronic element C2), and provide the signal to the array circuit 110 through the signal supply circuit (e.g., the signal supply circuit 130 or the signal supply circuit 130 a). The signal supplying circuit (e.g., the signal supplying circuit 130 or the signal supplying circuit 130a) may have at least one signal input terminal (e.g., the signal input terminal 131 or the signal input terminal 131a), at least one transmission terminal (e.g., the transmission terminal 132 or the transmission terminal 132a), and at least one third conductive wire (e.g., the third conductive wire 133 or the third conductive wire 133a), where the signal input terminal (e.g., the signal input terminal 131 or the signal input terminal 131a) corresponds to the transmission terminal (e.g., the transmission terminal 132 or the transmission terminal 132a), but is not limited thereto. In some embodiments, the signal input terminal (e.g., the signal input terminal 131 or the signal input terminal 131a) may be electrically connected to the transmission terminal (e.g., the transmission terminal 132 or the transmission terminal 132a) through a third wire (e.g., the third wire 133 or the third wire 133 a).

Since the signal supply circuit 130 is similar to the signal supply circuit 130a in structure, the signal supply circuit 130 is taken as an example for explanation. In some embodiments, the signal input terminal 131 and the third conductive line 133 of the signal supply circuit 130 may be disposed on the bottom surface 104 of the substrate 100, respectively, and the transmission terminal 132 may be disposed on the side surface 106a of the substrate 100. In some embodiments, the transmission terminals (e.g., the transmission terminal 132 or the transmission terminal 132a) are disposed on the side surface (e.g., the side surface 106b) and located between two of the at least two dispersion terminals, for example, at least one transmission terminal 132 may be located between the dispersion terminal 122 and the dispersion terminal 123, and at least one transmission terminal 132 ' may be located between the dispersion terminal 122 ' and the dispersion terminal 123 '. In some embodiments, the transmission terminal (e.g., the transmission terminal 132 or the transmission terminal 132a) can transmit a signal to the array circuit 110. In some embodiments, at least one third conductive line 133 may be disposed between the first conductive line 124 and the second conductive line 125 of the power supply circuit 120. In some embodiments, the first conductive line 124, the second conductive line 125, and/or the third conductive line 133 may be formed of the same film layer (e.g., a conductive layer), but not limited thereto. Referring to fig. 1A and fig. 1B, in some embodiments, the signal may be transmitted to the corresponding or electrically connected third conductive line 133 through the signal supply circuit 130, and further transmitted to the corresponding or electrically connected transmission terminal 132, so as to transmit the signal to the signal lines 112 of the array circuit 110, respectively, and drive the light emitting devices (e.g., the light emitting devices L1, L2, L3) electrically connected through the signal lines 112, respectively, but is not limited thereto. In some embodiments, when viewed in a normal direction of the bottom surface 104 of the substrate 100, the power input terminal (e.g., the power input terminal 121 or the power input terminal 121a), the first conductive line (e.g., the first conductive line 124 or the first conductive line 124a), and the second conductive line (e.g., the second conductive line 125 or the second conductive line 125a) are connected to each other and, for example, surround the signal input terminal (e.g., the signal input terminal 131 or the signal input terminal 131a) and the third conductive line (e.g., the third conductive line 133 or the third conductive line 133 a).

In some embodiments (as shown in fig. 1B), at least one electronic component (e.g., the electronic component C1 or the electronic component C2) may be disposed on the bottom surface 104 of the substrate 100, and the electronic component (e.g., the electronic component C1 or the electronic component C2) may be electrically connected or bonded to the signal input terminal (e.g., the signal input terminal 131 or the signal input terminal 131a) and the power input terminal (e.g., the power input terminal 121 or the power input terminal 121 a). In some embodiments, at least one electronic component (e.g., the electronic component C1 or the electronic component C2) may have a plurality of bonding pads (not shown), the bonding pads may respectively correspond to the signal input terminals and/or the power input terminals, and the bonding pads are electrically connected or bonded to the corresponding signal input terminals and/or the power input terminals, for example.

In some embodiments, the power input terminal (e.g., the power input terminal 121 or the power input terminal 121a) may correspond to or be electrically connected to two discrete terminals, but the number of the discrete terminals corresponding to the power input terminal is not limited. In some embodiments, the power input terminals may correspond to at least two or more discrete terminals such that the at least two or more discrete terminals distribute power to different portions of the array circuit.

Although all the discrete terminals of the present embodiment are disposed on the same side surface (e.g., the side surface 106a), the disclosure does not limit the disposed positions of the discrete terminals. In some embodiments, different discrete terminals corresponding to or electrically connected to the same power input terminal may be respectively disposed on the same or different side surfaces. For example (not shown), different dispersion terminals (e.g., the dispersion terminal 122 and the dispersion terminal 123) corresponding to the power input terminal 121 may be respectively disposed on the same or different side surfaces (including the side surface 106a, the side surface 106b, the side surface 106c, and/or the side surface 106d), or different dispersion terminals (e.g., the dispersion terminal 122a and the dispersion terminal 123a) corresponding to the power input terminal 121a may be respectively disposed on the same or different side surfaces (including the side surface 106a, the side surface 106b, the side surface 106c, and/or the side surface 106 d).

Although the

discrete terminals

122 and 123 corresponding to or connected to the power input terminal 121 of the present embodiment can substantially transmit 1/2 power (or current) to the first portion 1111a and the second portion 1112 of the array circuit 110, respectively, and the

discrete terminals

122a and 123a corresponding to or connected to the power input terminal 121a can substantially transmit 1/2 power (or current) to the first portion 1111a and the second portion 1112a of the array circuit 110, the present disclosure does not limit the ratio of the power (or current) that can be transmitted by the discrete terminals. For example, when the power input terminal 121 corresponds to two discrete terminals (e.g., the discrete terminal 122 and the discrete terminal 123), the two discrete terminals are substantially equal to 1: a ratio of 1 distributes power to the different portions (e.g., first portion 1111 and second portion 1112) of the array circuit 110.

Specifically, since the voltage transmitted by the discrete terminals is the same as the voltage provided by the corresponding or electrically connected power input terminals, the amount of current and/or power that can be distributed or transmitted by the discrete terminals may be substantially equally divided according to the number of the discrete terminals electrically connected to the power input terminals. For example, when the number of the discrete terminals electrically connected to the power input terminal is n, the ratio of the current (and/or power) distributed to the discrete terminals is approximately 1/n.

Although three signal input terminals 131 (or input terminals 131a), three transmission terminals 132 (or transmission terminals 132a), and three wires 133 (or third wires 133a) are respectively illustrated, the present disclosure does not limit the number of the signal input terminals, the transmission terminals, and the third wires.

In addition, the display panel 10 of the present embodiment may also be tiled into a tiled display device (not shown). That is, the tiled display apparatus of the present embodiment may include a plurality of display panels 10.

Other examples will be listed below for illustration. It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Fig. 2A is a bottom perspective view of a display panel according to another embodiment of the disclosure. FIG. 2B is a cross-sectional view of the display panel of FIG. 2A along the line A-A'. Referring to fig. 2B and fig. 1B, the display panel 10a of the present embodiment is substantially similar to the display panel 10 of fig. 1B, and therefore, the same and similar components in the two embodiments are not repeated herein. The display panel 10a of the present embodiment is different from the display panel 10 in that the display panel 10a of the present embodiment further includes an insulating layer 140. Specifically, referring to fig. 2A, the insulating layer 140 may be disposed on the bottom surface 104 of the substrate 100 to cover or protect the circuit disposed on the bottom surface 104, including the power input terminal 121, the power input terminal 121a, the first conductive line 124a, the second conductive line 125a, the signal input terminal 131a, the third conductive line 133a, or other electronic elements. In some embodiments, the insulating layer 140 may selectively cover or protect a portion of the electronic element (e.g., electronic element C1 or electronic element C2).

In some embodiments, the insulating layer 140 may be disposed on a side surface (e.g., the side surface 106a) of the substrate 100 to cover and protect circuits disposed on the side surface (e.g., the side surface 106a or other side surfaces), including the dispersion terminals 122, the dispersion terminals 122a, the dispersion terminals 123a, the transmission terminals 132a, or other electronic elements. In the present embodiment, the insulating layer 140 may have a single-layer or multi-layer structure, and the material of the insulating layer 140 may include an organic material, an inorganic material, or a combination thereof, but is not limited thereto.

Referring to fig. 2B, in the present embodiment, the direction X, the direction Y and the direction Z are different directions. For example, the direction X is, for example, an extending direction substantially along a sectional line a-a', the direction Y is, for example, a normal direction of the substrate 100, the direction Z is, for example, an extending direction substantially along the first conductive line 124, the first conductive line 124a, the third conductive line 133, and the third conductive line 133a, the direction X is substantially perpendicular to the direction Y, the direction Y is substantially perpendicular to the direction Z, and the direction Z is substantially perpendicular to the direction X, but not limited thereto. In the embodiment, the first conductive line 124 (or the first conductive line 124a) has a width W1, the third conductive line 133 (or the third conductive line 133a) has a width W2, and the width W1 may be greater than or equal to the width W2, but not limited thereto. In the present embodiment, the width W1 is, for example, the maximum width of the first conductive trace 124 (or the first conductive trace 124a) in the direction X, and the width W2 is, for example, the maximum width of the third conductive trace 133 (or the third conductive trace 133a) in the direction X.

Fig. 3 is a bottom perspective view of a display panel according to another embodiment of the disclosure. Referring to fig. 1B and fig. 3, the display panel 10B of the present embodiment is substantially similar to the display panel 10 of fig. 1B, and therefore, the same and similar components in the two embodiments are not repeated herein. The display panel 10b of the present embodiment is different from the display panel 10 in that the second conductive line 125 of the power supply circuit 120 (or the discrete terminal 123 electrically connected to the second conductive line 125) in the display panel 10b is, for example, far away from the second conductive line 125a of the power supply circuit 120a (or the discrete terminal 123a electrically connected to the second conductive line 125 a). In the display panel 10 (fig. 1B) of fig. 1B, the second conductive line 125 of the power supply circuit 120 (or the discrete terminal 123 electrically connected to the second conductive line 125) is, for example, adjacent to the second conductive line 125a of the power supply circuit 120a (or the discrete terminal 123a electrically connected to the second conductive line 125 a). In addition, the power input terminal 121 of the power supply circuit 120 in the display panel 10b is, for example, adjacent to the power supply circuit 120a (e.g., the second conductive line 125a), or the power input terminal 121 is, for example, far away from the side surface 106 c. The power input terminal 121 of the power supply circuit 120 in the display panel 10 (as shown in fig. 1B) is, for example, far away from the power supply circuit 120a (e.g., the second conductive line 125a), or the power input terminal 121 is, for example, adjacent to the side surface 106 c.

In some embodiments, the second conductive line 125 is longer than the first conductive line 124, for example. In some embodiments, the second conductive line 125a is longer in length than the first conductive line 124a, for example. In some embodiments, the power input terminal 121 and the power input terminal 121a may respectively correspond to the same side of the electrically connected electronic component (e.g., the electronic component C1 or the electronic component C2), and fig. 3 illustrates that the power input terminal 121 and the power input terminal 121a may respectively correspond to the left side of the electrically connected electronic component (e.g., the electronic component C1 or the electronic component C2), but is not limited thereto. In other embodiments (not shown), the power input terminal 121 and the power input terminal 121a may correspond to the right side of an electronic component (e.g., the electronic component C1 or the electronic component C2) to which the electronic component is electrically connected, respectively. In addition, in some embodiments (as shown in fig. 1B), the power input terminal 121 and the power input terminal 121a may correspond to different sides of an electrically connected electronic component (e.g., the electronic component C1 or the electronic component C2), respectively, for example, the power input terminal 121 corresponds to the right side of the electrically connected electronic component C1, and the power input terminal 121a corresponds to the left side of the electrically connected electronic component C2. It should be noted that the range of the electronic component C1 or the electronic component C2 in all the figures of the present application is only illustrative, but not limited thereto.

Fig. 4A is a schematic bottom view of a display panel according to another embodiment of the disclosure. Fig. 4B is an enlarged schematic view of the region R of the display panel of fig. 4A. Referring to fig. 1B and fig. 4A, a display panel 10c of the present embodiment is similar to the display panel 10 of fig. 1B, and similar components in the two embodiments are not repeated here. In the display panel 10c, the power supply circuit 120 may have at least one power input terminal 121, at least one power input terminal 121 ', at least one first conductive line 124 electrically connected to the corresponding power input terminal 121, at least one first conductive line 124 ' electrically connected to the corresponding power input terminal 121 ', at least one second conductive line 125 electrically connected to the corresponding power input terminal 121, and at least one second conductive line 125 ' electrically connected to the corresponding power input terminal 121 '. In some embodiments, the power supply circuit 120 may further include at least one power test pad 126 electrically connected between the corresponding second conductive line 125 and the corresponding power input terminal 121. In some embodiments, the power supply circuit 120 may further include at least one power test pad 126 ' electrically connected between the corresponding second conductive line 125 ' and the corresponding power input terminal 121 ', respectively.

Similarly, the power supply circuit 120a may have at least one power input terminal 121a, at least one power input terminal 121a ', at least one first conductive line 124a electrically connected to the corresponding power input terminal 121a, at least one first conductive line 124a ' electrically connected to the corresponding power input terminal 121a ', at least one second conductive line 125a electrically connected to the corresponding power input terminal 121a, and at least one second conductive line 125a ' electrically connected to the corresponding power input terminal 121a '. In some embodiments, the power supply circuit 120a may further include at least one power test pad 126a electrically connected between the corresponding second conductive line 125a and the corresponding power input terminal 121 a. In some embodiments, the power supply circuit 120a may further include at least one power test pad 126a ' electrically connected between the corresponding second conductive line 125a ' and the corresponding power input terminal 121a ', respectively.

In some embodiments, the power input terminal 121 and the power input terminal 121' provide or pass different signals, for example, respectively. In some embodiments, the power input terminal 121a and the power input terminal 121 a' provide or pass different signals, for example, respectively. Specifically, referring to fig. 4A and 4B, the power input terminal 121 (or the power input terminal 121a) can be used to provide a high voltage, and the power input terminal 121 '(or the power input terminal 121 a') can be used to provide a low voltage or a ground signal, but not limited thereto. In some embodiments, the power input terminal 121 (or the power input terminal 121a) may be used to provide a low voltage or a ground signal, and the power input terminal 121 '(or the power input terminal 121 a') may be used to provide a high voltage, but not limited thereto.

The power supply circuit 120 is taken as an example for explanation, and the power supply circuit 120a may be similar to the power supply circuit 120. In some embodiments, the first conductive line 124 may be electrically connected to the discrete terminal 122, the second conductive line 125 may be electrically connected to the discrete terminal 123, and the first conductive line 124 is electrically connected to the second conductive line 125 through the power input terminal 121 and the power test pad 126, but is not limited thereto. In some embodiments, the first conductive line 124 'may be electrically connected to the discrete terminal 122', the second conductive line 125 'may be electrically connected to the discrete terminal 123', and the first conductive line 124 'may be electrically connected to the second conductive line 125' through the power input terminal 121 'and the power test pad 126', but is not limited thereto.

Referring to fig. 4A and 4B, in some embodiments, the plurality of second conductive lines 125 may be, for example, merged into a main line 125A, the main line 125A may be branched into a plurality of branch portions 125B, and the branch portions 125B are, for example, electrically connected to the discrete terminals 123, respectively. In some embodiments, the plurality of second conductive wires 125 'may be, for example, merged into a main wire 125A', the main wire 125A 'may be branched into a plurality of branch portions 125B', and the branch portions 125B 'may be, for example, electrically connected to the discrete terminals 123', respectively. Similarly, in the power supply circuit 120a, the plurality of second wires 125a may be, for example, merged into a main line 125aA, the main line 125aA may be branched into a plurality of branch portions 125aB, and the branch portions 125aB are, for example, electrically connected to the discrete terminals 123a, respectively. In some embodiments, the plurality of second conductive wires 125a 'may be, for example, merged into a main wire 125 aA', the main wire 125aA 'may be branched into a plurality of branch portions 125 aB', and the branch portions 125aB 'may be, for example, electrically connected to the discrete terminals 123 a', respectively. In some embodiments, the number of the second conductive lines and the number of the branch portions electrically connected to the different main lines may be changed according to requirements.

Referring to fig. 4A and 4B, the power supply circuit 120 is taken as an example for description, and the power supply circuit 120a is similar to the power supply circuit 120, for example. In some embodiments, multiple power test pads may be arranged adjacent to each other, or another test pad (e.g., a signal test pad) may be disposed between two power test pads. For example, the plurality of power test pads 126' may be arranged adjacent to each other, for example, but not limited thereto. In some embodiments, two of the plurality of power test pads 126 may be arranged adjacent to each other, for example, and two of the plurality of power test pads 126 may have at least one signal test pad 134 therebetween. In some embodiments, the number of power test pads 126 may be the same or different than the number of power test pads 126'. In some embodiments, the number of signal test pads 134 may be greater than the number of power test pads 126 and/or the number of power test pads 126'.

In some embodiments, the signal supply circuit 130 may have at least one signal input terminal 131, at least one third conductive line 133 electrically connected to one end of the corresponding signal input terminal 131, and at least one signal test pad 134 electrically connected to the other end of the signal input terminal 131. In some embodiments, the signal supply circuit 130a may have at least one signal input terminal 131a, at least one third conductive line 133a electrically connected to one end of the corresponding signal input terminal 131a, and at least one signal test pad 134a electrically connected to the other end of the signal input terminal 131 a.

In some embodiments, at least one or more signal input terminals 131 may be disposed between two power input terminals 121 (or power input terminals 121'). In some embodiments, at least one or more signal input terminals 131a may be disposed between two power input terminals 121a (or power input terminals 121 a').

In some embodiments, the power test pad 126 ', the power test pad 126 a', the signal test pad 134 and/or the signal test pad 134a may be applied with predetermined voltages by a probe to perform a light on test (light on test) or a circuit test, for example, by observing whether the light emitting devices electrically connected to the power test pads or the signal test pads emit light normally to confirm whether the power supply circuit, the signal supply circuit, the array circuit 110 and the circuits among the light emitting devices are turned on or short circuited (short circuit), but not limited thereto. In some embodiments, power test pads and/or signal test pads may not be provided.

In summary, in the display panel and the tiled display device including the display panel according to the embodiments of the disclosure, the power input terminal can correspond to the at least two scattering terminals, and the at least two scattering terminals can be scattered on the side surface of the substrate, so that power can be uniformly scattered to different portions of the array circuit (e.g., the first portion and the second portion of the array circuit) through the at least two scattering terminals, and thus, power (or current) can be more uniformly transmitted to different light emitting elements, and the light emitting brightness of different light emitting elements can be more uniform.

The above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present disclosure.

Claims

1. A display panel, characterized in that, comprising:

a substrate having a top surface, a bottom surface, and a side surface between the top surface and the bottom surface;

an array circuit disposed on the top surface; and

a power supply circuit, wherein power is supplied to the array circuit through the power supply circuit,

Wherein the power supply circuit has power input terminals corresponding to at least two distributed terminals, the at least two distributed terminals are disposed on the side surface, and distribute the power to different parts of the array circuit.

2 . The display panel according to claim 1 , wherein the power input terminals correspond to two distributed terminals. 3 .

3 . The display panel of claim 2 , wherein the two dispersing terminals disperse the power to the different parts of the array circuit in a ratio of 1:1. 4 .

4 . The display panel of claim 1 , wherein the at least two dispersed terminals are dispersed on the side surface. 5 .

5 . The display panel of claim 1 , wherein the power input terminal is electrically connected to two of the at least two distributed terminals through a first wire and a second wire, respectively. 6 .

6. The display panel according to claim 5, further comprising:

a signal supply circuit, wherein a signal is supplied to the array circuit through the signal supply circuit,

wherein the signal supply circuit has a signal input terminal corresponding to a transmission terminal, the transmission terminal is disposed on the side surface and is located between the two distributed terminals among the at least two distributed terminals, and the transmission terminal Terminals pass the signal to the array circuit.

7 . The display panel according to claim 6 , wherein the signal input terminal is electrically connected to the transmission terminal through a third wire, and the third wire is disposed between the first wire and the between the second wires.

8 . The display panel according to claim 7 , wherein the first wire, the second wire and the third wire are formed by the same film layer. 9 .

9. The display panel of claim 1, further comprising an insulating layer disposed on the bottom surface of the substrate.

10. A tiled display device, comprising a plurality of display panels, each of the plurality of display panels comprising:

an array circuit disposed on the top surface; and