CN113689893B

CN113689893B - Flash Array

Info

Publication number: CN113689893B
Application number: CN202110989487.0A
Authority: CN
Inventors: 蒋家勇; 石振东
Original assignee: Beijing Pansin Microelectronics Technology Co ltd
Current assignee: Beijing Pansin Microelectronics Technology Co ltd
Priority date: 2021-08-26
Filing date: 2021-08-26
Publication date: 2025-01-28
Anticipated expiration: 2041-08-26
Also published as: CN113689893A

Abstract

The present disclosure provides a flash memory array. The flash memory array according to the present disclosure includes: a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups extending in the row direction; and a plurality of bit line groups extending in the column direction, wherein a flash memory cell pair is arranged at the intersection of the word line group and the bit line group, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell adjacent in the row direction and sharing the same bit line group. The flash memory array according to the present disclosure can increase the arrangement density of the bit lines and reduce the parasitic resistance of the bit lines without increasing the size of the array. In addition, compared with the flash memory array of the prior art, the flash memory array according to the present disclosure also has better process compatibility and miniaturization characteristics.

Description

Flash memory array

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a flash memory array.

Background

Flash memory, abbreviated as flash memory, is a non-volatile memory, i.e. the stored data will not be lost even if the power is turned off, and is especially suitable for the fields of mobile communication and computer storage parts. In addition, some flash memories also have high density storage capability, and are suitable for applications such as mass storage media.

Conventional flash memories employ a floating gate type cell structure. The floating gate type nonvolatile memory originates from MIMIS (Metal-Insulator-Semiconductor) structure proposed by d.kahng and s.sze in 1967. The structure is formed by adding a Metal floating gate and an ultrathin tunneling Oxide layer on the basis of a traditional MOSFET (Metal-Oxide-Semiconductor FIELD EFFECT Transistor) so as to store charges by using the Metal floating gate. Based on this, masuoka et al, in 1984, first proposed the concept of Flash Memory (Flash Memory), i.e., to achieve high-speed erase capability by block-by-block (sector) erase bit-by-bit writing, and eliminate the select tube necessary in EEPROM (Erasable Programmable Read-only Memory) to have a smaller Memory cell size. After the advent of flash memory, it has been rapidly developed with its high writing speed, high integration, and superior performance. Intel corporation proposed an ETOX structure flash memory cell (ETOX: electron Tunneling Oxide device, electron tunneling oxide device) in 1988, which became the basis for the development of most floating gate type flash memory cell structures so far.

However, the floating gate type flash memory has the disadvantages of complicated process, adverse scaling down of process size and cell area due to the increased longitudinal height of the gate structure due to the existence of the floating gate structure in the flash memory cell, and adverse improvement of reliability of the memory due to free movement of stored charges in the floating gate due to the conductivity of the floating gate. In order to solve the problems of complicated process, poor reliability and the like of the floating gate type flash Memory, researchers have proposed a Charge trapping Memory (CTM: charge-Trapping-Memory), also called SONOS type (Silicon-Oxide-Nitride-Oxide-Silicon: silicon-Oxide-Nitride-Oxide-Silicon) flash Memory, which stores charges by using a Silicon Nitride medium. Based on this, eitan et al proposed a two-bit Memory cell structure NROM (Nitride-Read-Only-Memory) in 2000, which uses the non-conductive property of an insulating silicon Nitride Memory medium to realize two Memory bits at the source and drain terminals of a Memory transistor, but the cell structure has the disadvantages that the two Memory bits interfere with each other, and the size of the device cannot be reduced.

However, the conventional floating gate ETOX flash memory and SONOS NROM flash memory have problems that the process size cannot be reduced, the cell area is large, the writing power consumption is large, and the array area overhead is large, and high-density integration with a gigabit (Gb) capacity or more cannot be realized.

In addition, the existing flash memory array requires setting bit lines, word lines and source lines to achieve selection and operation of flash memory cells. However, the source line of the existing flash memory array is formed in the active region, and the sheet resistance of the active region is much higher than that of the metal. Therefore, to reduce the series resistance of the source lines, the active area source lines need to be shorted together by a common source line of metal every few rows or columns in the row direction or column direction, resulting in an increase in the area overhead of the flash memory array.

With the rapid development of applications such as mobile intelligent terminals, wearable devices, intelligent sensor networks and the like, higher requirements are put forward on the power consumption, storage capacity and cost of a flash memory, so that a flash memory technology with the advantages of low power consumption, small unit area, small process size, high array integration density, large capacity and the like is needed.

Disclosure of Invention

The above information disclosed in this background section is only for the understanding of the background of the inventive concept and therefore it may contain information that does not form the prior art.

In order to solve the above problems in the prior art, the present disclosure proposes a flash memory array.

According to one aspect of the present disclosure, there is provided a flash memory array including a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction, a plurality of word line groups extending in the row direction, and a plurality of bit line groups extending in the column direction, wherein flash memory cell pairs including first and second flash memory cells sharing the same bit line group adjacent in the row direction are provided at intersections of the word line groups and the bit line groups.

The flash memory array according to the present disclosure can improve the arrangement density of bit lines and can reduce the parasitic resistance of the bit lines without increasing the array size. In addition, the flash memory array according to the present disclosure also has better process compatibility and miniaturization characteristics than the prior art flash memory array.

However, the effects of the present disclosure are not limited to the above-described effects, and various extensions are to be understood without departing from the spirit and scope of the present disclosure, and the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principle of the invention.

Fig. 1 is a cross-sectional view illustrating a flash memory cell according to an embodiment of the present disclosure.

Fig. 2 shows an equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure.

Fig. 3 shows a circuit schematic of a flash memory cell pair according to a first embodiment of the present disclosure.

Fig. 4 shows a circuit schematic of a flash memory array according to a first embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of one layout example of a bit line group according to a first embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of another layout example of a bit line group according to the first embodiment of the present disclosure.

Fig. 7 shows a circuit schematic of a flash memory cell pair according to a second embodiment of the present disclosure.

Fig. 8 shows a circuit schematic of a flash array according to a second embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of one layout example of a bit line group according to a second embodiment of the present disclosure.

Fig. 10 shows a schematic diagram of a layout of control lines of a flash memory array according to an embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. It may be evident, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the example embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the particular shapes, configurations and characteristics of the exemplary embodiments may be used or implemented in other exemplary embodiments without departing from the spirit of the present invention.

Unless otherwise indicated, the illustrated exemplary embodiments should be understood as providing exemplary features of varying detail in some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise indicated, features, components, modules, layers, films, panels, regions, and/or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the drawings is typically provided to clarify the boundaries between adjacent elements. As such, no particular material, material property, dimension, proportion, commonality between illustrated elements, and/or any other property, attribute, shape, etc., whether cross-hatched or not present, is intended to convey or indicate any preference or requirement for the elements, unless otherwise indicated. In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While the exemplary embodiments may be implemented differently, the particular sequence of processes may be performed differently than as described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Also, like reference numerals designate like elements.

When an element such as a layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this extent, the term "connected" can refer to physical, electrical, and/or fluid connection with or without intervening elements. Furthermore, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system, such as x, y, and z axes, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of two or more of X only, Y only, Z only, or X, Y and Z, such as XYZ, XYY, YZ and ZZ, for example. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

Spatially relative terms, such as "under," "below," "beneath," "lower," "above," "upper," "higher" and "lateral" (e.g., as in "sidewall") and the like, may be used herein for descriptive purposes to describe the relationship between one element and another element as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both an orientation of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It should also be noted that as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not degree terms and are, therefore, utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

As is conventional in the art, some exemplary embodiments are described and illustrated in the figures in terms of functional blocks, units, and/or modules. Those skilled in the art will appreciate that the blocks, units, and/or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wired connections, or the like, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and/or modules are implemented by a microprocessor or other similar hardware, they may be written and controlled using software (e.g., microcode) to perform the various functions recited herein, and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented with dedicated hardware, or as a combination of dedicated hardware performing some functions and a processor (e.g., one or more written microprocessors and related circuitry) performing other operations. Furthermore, each block, unit, and/or module of some example embodiments may be physically separated into two or more interactive and discrete blocks, units, and/or modules without departing from the scope of the inventive concept. Furthermore, the blocks, units, and/or modules of some example embodiments may be physically combined into more complex blocks, units, and/or modules without departing from the scope of the inventive concept.

Embodiments are described herein with reference to cross-sectional and/or exploded views, which are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein are not necessarily to be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result, for example, from manufacturing. In this way, the regions illustrated in the figures may be schematic in nature and the shapes of the regions may not reflect the actual shape of the regions of the device and thus, are not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 illustrates a cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure.

As shown in fig. 1, a flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103.

Although the first doping type is defined as a P-type and the second doping type is defined as an N-type in fig. 1 as an example, it should be recognized by those skilled in the art that the present disclosure is not limited thereto and the first doping type may also be an N-type, in which case the second doping type may be a P-type.

According to embodiments of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

Further, the flash memory cell MC 100 includes a first memory transistor MS110, a gate transistor MG 120, and a second memory transistor MD 130 connected in series in this order. The first storage transistor MS110 may be disposed on the well region PW 102 and store the first DATA1. The second storage transistor MD 130 may be disposed on the well region PW 102 and store the second DATA2. The gate transistor MG 120 is disposed between the first memory transistor MS110 and the second memory transistor MD 130 in the horizontal direction DR1 on the well region PW 102 for isolating the first memory transistor MS110 and the second memory transistor MD 130 and performing a gate operation on the first memory transistor MS110 and the second memory transistor MD 130.

According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two storage transistors MS110 and MD 130, and thus the flash memory cell MC 100 can implement a two-bit storage function, i.e., simultaneously store the first DATA1 and the second DATA2.

Further, as shown in fig. 1, the source region of the first memory transistor MS 110 is connected to the first electrode S of the flash memory cell MC 100, which may also be referred to as the source S of the flash memory cell MC 100, and the drain region of the second memory transistor MD 130 is connected to the second electrode D of the flash memory cell MC 100, which may also be referred to as the drain D of the flash memory cell MC 100.

Those skilled in the art will recognize that the definition of the source and drain of a flash memory cell is defined herein for ease of description, however the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" are used interchangeably under different operating conditions.

Further, as shown in fig. 1, the first memory transistor MS 110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117, which are sequentially disposed in a vertical direction DR 2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 stacked in this order in the vertical direction. Further, the second memory transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask barrier 137, which are sequentially disposed in the vertical direction DR 2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 stacked in this order in the vertical direction.

According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two memory transistors MS110 and MD 130, and thus can implement a two-bit memory function.

According to an embodiment of the present disclosure, as shown in fig. 1, a flash memory cell MC100 for two-bit storage may be composed of three closely arranged transistors, namely a gate transistor MG 120 located in the middle of the flash memory cell MC100, a first storage transistor MS 110 located at a first end of the flash memory cell MC100, and a second storage transistor MD 130 located at a second end of the flash memory cell MC 100.

As shown in fig. 1, a flash memory cell MC 100 may be formed on a well region PW 102 within a semiconductor substrate 101. Furthermore, in order to isolate well region PW 102 from substrate 101 in order to apply a voltage to well region PW 102 under certain operating conditions, well region PW 102 may be formed in deep well region DNW 103, as shown in fig. 1.

As shown in fig. 1, a source region 140 formed by N-type doping is provided at a first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at a second end of the flash memory cell MC 100. The source region 140 is connected to the metal source 142, i.e., the first electrode S, located at the upper layer through the contact hole 141, and the drain region 150 is connected to the metal drain 152, i.e., the second electrode D, located at the upper layer through the contact hole 151.

According to embodiments of the present disclosure, the first electrode S and the second electrode D may include metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of metal, they may include at least one of aluminum, titanium nitride, copper, tungsten, cobalt, and manganese.

As described above, the gate structure of the first memory transistor MS 110 may have the channel region 111, the gate dielectric stack 112, the gate electrode 116, and the hard mask barrier 117 for sidewall self-alignment in order from bottom to top as shown in fig. 1. According to embodiments of the present disclosure, the gate electrode 116 may comprise, for example, polysilicon, a metal gate, a metal silicide material, or a combination thereof. The hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, a silicate glass material, or a combination thereof, according to embodiments of the present disclosure.

Further, as shown in fig. 1, the gate dielectric stack 112 has a first oxide layer (tunnel oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115, which are sequentially stacked in the vertical direction. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide, or the like.

According to embodiments of the present disclosure, the storage medium layer 114 may include one or more layers of storage media. Further, in accordance with embodiments of the present disclosure, the storage medium forming the storage medium layer 114 may include a mono-or poly-oxide such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, a mono-or poly-nitride such as silicon nitride, a mono-or poly-oxynitride such as silicon oxynitride, polysilicon or a nanocrystalline material, or a combination of the foregoing.

When the storage medium layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may form the gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium according to an embodiment of the present disclosure. At this time, the first memory transistor MS 110 may be a SONOS type memory transistor.

Furthermore, according to embodiments of the present disclosure, the first memory transistor MS 110 may be another trap charge-trapping memory transistor having a similar operation mechanism as a SONOS-type memory transistor, which uses a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, or the like, instead of the silicon nitride material in the SONOS memory as the memory medium layer 114.

Furthermore, according to embodiments of the present disclosure, the first memory transistor MS 110 may also be a floating gate memory transistor, which uses a polysilicon material instead of a silicon nitride material in a SONOS memory device to form a floating gate for storing charges as the memory medium layer 114.

Furthermore, according to an embodiment of the present disclosure, the first memory transistor MS 110 may also be a nano-crystalline memory transistor (nano-crystalline memory), which uses a nano-crystalline material with quantum dots (quantum dots) instead of a silicon nitride material in a SONOS memory as the memory medium layer 114.

According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first memory transistor MS 110 may be defined by the length of the hard mask barrier 117 disposed on the gate electrode 116 through a self-aligned process. It should be noted by those skilled in the art that reference herein to "length" means the dimension of the stated object in the horizontal direction DR 1.

According to the embodiment of the present disclosure, the second memory transistor MD 130 has the same structure as the first memory transistor MS 110 and may be manufactured by the same process as the first memory transistor MS 110 except that it is disposed at the opposite side of the gate transistor MG 120, and thus a detailed description of the structure of the second memory transistor MD 130 will be omitted herein for brevity.

The gate structure of the gate transistor MG 120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 in this order from bottom to top. According to an embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 thereof is defined by the process dimension of the photolithography process. According to embodiments of the present disclosure, gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, hafnium oxide, and the like. Further, according to embodiments of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials.

According to an embodiment of the present disclosure, the channel regions 111, 131 and 121 of the first memory transistor MS 110, the second memory transistor MD 130 and the gate transistor MG 120 may each have a first doping type, and the doping concentrations of the channel regions 111 and 131 of the first memory transistor MS 110 and the second memory transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gate transistor MG 120.

Further, according to an embodiment of the present disclosure, the channel regions 111 and 131 of the first and second memory transistors MS 110 and MD 130 may have a second doping type or be undoped intrinsic channel regions, and the channel region 121 of the gate transistor MG 120 may have a first doping type different from the second doping type.

For example, as shown in fig. 1, in the case where the first doping type is P-type and the second doping type is N-type, the doping concentrations of the P-type channels 111 and 131 of the first memory transistor MS 110 and the second memory transistor MD 130 are lower than the doping concentration of the P-type channel 121 of the gate transistor MG 120. Furthermore, channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions, according to embodiments of the present disclosure.

According to an embodiment of the present disclosure, the flash memory cell MC 100 further includes a first isolation portion 124 disposed between the first memory transistor MS 110 and the gate transistor MG120 in the horizontal direction DR1 for isolating the gate electrode 116 of the first memory transistor MS 110 and the gate electrode 123 of the gate transistor MG120, and a second isolation portion 125 disposed between the gate transistor MG120 and the second memory transistor MD 130 in the horizontal direction DR1 for isolating the gate electrode 123 of the gate transistor MG120 and the gate electrode 136 of the second memory transistor MD 130.

Specifically, as shown in fig. 1, the gate electrode 123 of the gate transistor MG 120 is provided on both sides with a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls for electrically isolating the gate electrode 116 of the first memory transistor MS 110 and the gate electrode 136 of the second memory transistor MD 130, respectively, with a certain isolation gap length. According to an embodiment of the present disclosure, the first and second spacers 124 and 125 may include the same material as the gate dielectric layer 122.

The flash memory cell according to the embodiment of the present disclosure can realize two memory transistors in one flash memory cell, so that the equivalent area of each memory bit can be greatly reduced, thereby achieving lower cost and higher integration density.

In addition, the memory transistor in the flash memory unit according to the embodiment of the disclosure can adopt a SONOS type device structure with a simple structure, and has the advantages of simple process, low gate electrode operation voltage and good data retention reliability.

In addition, in the flash memory cell according to the embodiment of the disclosure, the mutual influence of two storage bits is isolated through the gating transistor, and the distribution width and the lateral diffusion of stored charges are restrained, so that higher stored charge density can be obtained in the silicon nitride storage layer, the problems that the existing NROM storage cell which also adopts two-bit storage is wide in charge distribution, large in mutual interference, incapable of shrinking in gate length and the like are avoided, and the storage window and the data reliability are remarkably improved.

In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first memory transistor, the gate transistor, and the second memory transistor. As described above, the gate electrode length of the gate transistor is defined by the process feature size of the photolithographic process, which is typically about equal to or slightly greater than the critical feature size (Critical Feature Size) of the photolithographic process, which is typically denoted as F (or CF). In addition, gate electrode lengths of the first memory transistor and the second memory transistor are respectively defined by lengths of the self-aligned sidewall hard mask barrier portions, and thus may be smaller than F in size. Therefore, according to the embodiment of the disclosure, the smaller channel length of the flash memory unit can be obtained under the same process feature size, and the purposes of reducing the area and the manufacturing cost of the flash memory unit are achieved.

In addition, in the flash memory array composed of the flash memory cells according to the embodiment of the present disclosure, for the flash memory cells not selected to operate, the gate electrodes of the gate transistor and the first and second memory transistors are grounded, so that the entire serial channels of the flash memory cells are completely turned off, the equivalent channel length is enlarged, and thus the source-drain punch-through of the flash memory cells under the condition of high operation voltage can be avoided under the smaller process feature size, thereby overcoming the problem that the gate electrode length of the existing flash memory cells cannot be reduced with the reduction of the process feature size. Accordingly, the flash memory cell according to the embodiment of the present disclosure has better process miniaturization capability, and thus can obtain smaller cell area and manufacturing cost by shrinking the process feature size.

In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first memory transistor and the second memory transistor or designing them as N-type doped channel regions, the threshold voltage of the memory transistor and the gate electrode operating voltage at the time of erasing and reading operations can be reduced, and thus the reliability of the memory transistor can be improved. Meanwhile, by increasing the doping concentration of the P-type channel region of the gating transistor, the penetration resistance voltage of the flash memory unit can be increased, and the leakage current between the source region and the drain region of the unselected flash memory unit can be reduced.

Fig. 2 shows an equivalent circuit diagram of the flash memory cell MC 100 according to the embodiment of the present disclosure.

Specifically, as shown in fig. 2, the flash memory cell MC 100 includes a first memory transistor MS 110, a gate transistor MG 120, and a second memory transistor MD 130, which are sequentially connected in series. The gate transistor MG 120 may isolate the first and second memory transistors MS 110 and MD 130 and perform a gate operation on the first and second memory transistors MS 110 and MD 130.

Fig. 3 shows a circuit schematic of a flash cell pair 200 according to a first embodiment of the present disclosure. Fig. 4 shows a circuit schematic of a flash memory array according to a first embodiment of the present disclosure.

According to an embodiment of the present disclosure, a flash memory array may include a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction, a plurality of word line groups extending in the row direction, and a plurality of bit line groups extending in the column direction, wherein flash memory cell pairs including first and second flash memory cells adjacent in the row direction sharing the same bit line group are disposed at intersections of the word line groups and the bit line groups.

As shown in fig. 3 and 4, according to an embodiment of the present disclosure, a flash memory array may include a plurality of flash memory cells as shown in fig. 2, which may be arranged in an array of m×2n in a row direction and a column direction perpendicular to the row direction, where m and n are natural numbers greater than 1. Thus, the plurality of flash memory cells form an m row by 2n column flash memory array.

As shown in fig. 3, two flash memory cells adjacent in a row direction may constitute one flash memory cell pair 200 including a first flash memory cell 210 and a second flash memory cell 220 according to an embodiment of the present disclosure. For example, the first flash cell 210 may be a0 th row and 0 th column flash cell in the flash array, and the second flash cell 220 may be a0 th row and 1 st column flash cell in the flash array. Thus, according to embodiments of the present disclosure, a flash array may include pairs of flash memory cells arranged in m rows by n columns.

The first flash unit 210 includes a first memory transistor 211, a gate transistor 212, and a second memory transistor 213 sequentially connected in series in the column direction. The second flash memory cell 220 includes a first memory transistor 221, a gate transistor 222, and a second memory transistor 223 sequentially connected in series in a column direction.

According to an embodiment of the present disclosure, in the first flash memory cell 210, a source region of the first storage transistor 211 is connected to the first electrode S1 of the first flash memory cell 210, and a drain region of the second storage transistor 213 is connected to the second electrode D1 of the first flash memory cell 210.

Further, according to an embodiment of the present disclosure, in the second flash memory cell 220, the source region of the first storage transistor 221 is connected to the first electrode S2 of the second flash memory cell 220, and the drain region of the second storage transistor 223 is connected to the second electrode D2 of the second flash memory cell 220.

Further, according to an embodiment of the present disclosure, the flash cell pair 200, i.e., the pair of the first flash cell 210 and the second flash cell 220, shares a bit line group extending in the column direction, which includes a first bit line BSL0, an intermediate bit line BLM0, and a second bit line BLD0. According to the first embodiment of the present disclosure, the first bit line BSL0 may be connected to the first electrode S1 of the first flash memory cell 210, the second bit line BLD0 may be connected to the second electrode D2 of the second flash memory cell 220, and the intermediate bit line BLM0 may be connected to the second electrode D1 of the first flash memory cell 210 and the first electrode S2 of the second flash memory cell 220.

As described above, according to the embodiment of the present disclosure, the first flash memory cell 210 and the second flash memory cell 220 adjacent in the row direction are connected to the same first bit line BSL0, intermediate bit line BLM0, and second bit line BLD0. That is, in a flash array, pairs of flash memory cells share the same bit line group according to embodiments of the present disclosure. For example, column 0 flash memory cells and column 1 flash memory cells share a bit line group including a first bit line BLS0, an intermediate bit line BLM0, and a second bit line BLD0, and column 2 flash memory cells and column 3 flash memory cells share a bit line group including a first bit line BLS1, a meta line BLM1, and a second bit line BLD1, until column 2n-2 flash memory cells and column 2n-1 flash memory cells share a bit line group including a first bit line BLS < n-1>, an intermediate bit line BLM < n-1>, and a second bit line BLD < n-1 >.

Further, according to an embodiment of the present disclosure, the flash memory array further includes a plurality of word line groups extending in the row direction, each word line group including a first control line connected to a gate electrode of a first storage transistor of the flash memory cell pair, a word line connected to a gate electrode of a gate transistor of the flash memory cell pair, and a second control line connected to a gate electrode of a second storage transistor of the flash memory cell pair.

In accordance with embodiments of the present disclosure, in a flash memory array, flash memory cells (pairs) of the same row share the same word line group, i.e., a first control line, a word line, and a second control line.

As shown in fig. 3 and 4, taking the flash cell pair 200 as an example, the flash cell pair 200, i.e., the first flash cell 210 and the second flash cell 220, are located in row 0 and share the same word line group, i.e., the first control line MS0, the word line WL0, and the second control line MD0, with other flash cells (pairs) in row 0. The first control line MS0 is connected to gate electrodes of the first storage transistors 211 and 221 of the first and second flash memory cells 210 and 220, the word line WL0 is connected to gate electrodes of the gate transistors 212 and 222 of the first and second flash memory cells 210 and 220, and the second control line MD0 is connected to gate electrodes of the second storage transistors 213 and 223 of the first and second flash memory cells 210 and 220.

Similarly, the gate electrodes of the first memory transistors in the flash memory cells (pairs) of row 1 are commonly connected to the first control line MS1, the gate electrodes of the gate transistors in the flash memory cells of row 1 are commonly connected to the word line WL1, and the gate electrodes of the second memory transistors in the flash memory cells of row 1 are commonly connected to the second control line MD1. Similarly, the gate electrode of a first memory transistor in the flash memory cell of the m-2 th row is commonly connected to the first control line MS < m-2>, the gate electrode of a gate transistor in the flash memory cell of the m-2 th row is commonly connected to the word line WL < m-2>, and the gate electrode of a second memory transistor in the flash memory cell of the m-2 th row is commonly connected to the second control line MD < m-2>. Similarly, the gate electrode of a first memory transistor in the flash memory cell of the m-1 th row is commonly connected to the first control line MS < m-1>, the gate electrode of a gate transistor in the flash memory cell of the m-1 th row is commonly connected to the word line WL < m-1>, and the gate electrode of a second memory transistor in the flash memory cell of the m-1 th row is commonly connected to the second control line MD < m-1>.

It will be appreciated by those skilled in the art that the flash memory cells according to the embodiments of the present disclosure have a symmetrical structure, and thus the flash memory cells adjacent in the column direction are disposed opposite each other based on the connection relationship of the first control line, the word line, the second control line, the first bit line, the intermediate bit line, and the second bit line as described above, i.e., the first memory transistor of the flash memory cell of the current row is adjacent to the first memory transistor of the flash memory cell of the previous row in the column direction and the second memory transistor of the flash memory cell of the current row is adjacent to the second memory transistor of the flash memory cell of the next row in the column direction, or the second memory transistor of the flash memory cell of the current row is adjacent to the second memory transistor of the flash memory cell of the previous row and the first memory transistor of the flash memory cell of the next row is adjacent in the column direction.

According to an embodiment of the present disclosure, the first control line, the word line, and the second control line may be formed of at least one of polysilicon, silicide, and a metal gate. Further, according to embodiments of the present disclosure, the intermediate bit line may be formed of a first metal layer, and the first bit line and the second bit line may be formed of a second metal layer different from the first metal layer. In other words, the metal layer used to form the intermediate bit lines is different from the metal layer used to form the first bit lines and the second bit lines. In addition, the first bit line and the second bit line may be formed of the same metal layer.

According to embodiments of the present disclosure, the first metal layer and the second metal layer may include at least one of aluminum, titanium nitride, copper, tungsten, cobalt, and manganese.

According to embodiments of the present disclosure, the intermediate bit line may include a first portion extending in the column direction and a second portion extending in the row direction, and the first bit line and the second bit line extend in the column direction.

As shown in (a) of fig. 5, taking the flash memory cell pair 200 as an example, the first electrodes S1 and S2 and the second electrodes D1 and D2 of the first and second flash memory cells 210 and 220 may be formed of a first metal layer M1 disposed over, for example, the first control line MS0, the word line WL0, and the second control line MD0 of polysilicon. As shown in fig. 5, the first control line MS0, the word line WL0, and the second control line MD0 extend parallel to each other in the row direction.

Further, as shown in (a) of fig. 5, the intermediate bit line BLM0 is formed of the first metal layer M1 in a continuous zigzag manner in the column direction, and includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction. According to an embodiment of the present disclosure, the second portion P2 of the intermediate bit line BLM0 may overlap with the word line WL0 therebelow.

Further, as shown in (b) of fig. 5, the first and second bit lines BLS0 and BLD0 may be formed of the second metal layer M2 in the column direction and overlap the first portion P1 of the intermediate bit line BLM 0.

According to an embodiment of the present disclosure, the electrical connection between the first bit line BLS0 and the first electrode S1 of the first flash memory cell 210 may be achieved through the via V1 between the first metal layer M1 and the second metal layer M2, and the electrical connection between the second bit line BLD0 and the second electrode D2 of the second flash memory cell 220 may be achieved through the via V1 between the first metal layer M1 and the second metal layer M2.

According to the embodiment of the present disclosure, since the first portion P1 of the intermediate bit line may overlap the first bit line and the second bit line, and the second portion P2 of the intermediate bit line may overlap the word line of the polysilicon in the row direction, an area for additionally providing the intermediate bit line may be eliminated, thereby obtaining a more compact flash memory array. In addition, since the first bit line and the second bit line are both formed of metal, the need for providing a common source line in the prior art is eliminated, thereby further reducing the area of the flash memory array.

The embodiment shown in fig. 5 uses two metal layers to achieve the arrangement of the first bit line, the intermediate bit line and the second bit line. However, the present disclosure is not limited thereto. According to the embodiment of the disclosure, the first bit line, the middle bit line and the second bit line can be arranged by using more metal layers according to the application scene of the flash memory array.

Specifically, as shown in (a) of fig. 6, the first and second electrodes of the flash memory cell may be formed of a first metal layer M1 disposed over first, word and second control lines, e.g., polysilicon. Unlike fig. 5, as shown in (c) of fig. 6, the intermediate bit line may be formed of the third metal layer M3 in a continuous zigzag manner in the column direction. That is, the intermediate bit line includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction.

Further, as shown in (d) of fig. 6, the first bit line and the second bit line are formed by the fourth metal layer M4 in the column direction and overlap the first portion P1 of the intermediate bit line in the column direction. As shown in (b) of fig. 6, the electrical connection of the intermediate bit line with the first and second electrodes may be achieved through the second metal layer M2 between the first and third metal layers M1 and M3 and the vias V1 and V2 between the respective metal layers M1 to M3. Further, as shown in (b) and (c) of fig. 6, the electrical connection between the first bit line and the first electrode may be achieved through the second and third metal layers M2 and M3 between the first and fourth metal layers M1 and M4 and the through holes V1 to V3 between the respective metal layers M1 to M4. Further, as shown in (b) and (c) of fig. 6, the electrical connection between the second bit line and the second electrode may also be achieved by the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the vias V1 to V3 between the respective metal layers M1 to M4.

The four-layer metal bit line layout shown in fig. 6 may allow for greater flexibility in the layout of the first bit line, the intermediate bit line, and the second bit line than the two-layer metal bit line layout shown in fig. 5.

Further, those skilled in the art will recognize that at least two metal layers are required for the bit line arrangement of the flash memory array according to the present disclosure, and thus, although fig. 6 illustrates an embodiment in which the bit line arrangement of the flash memory array according to the present disclosure is implemented using four metal layers, the present disclosure is not limited thereto. The bit line arrangement of a flash memory array according to the present disclosure may be implemented using three metal layers or five or more metal layers by those skilled in the art in light of the teachings of the present disclosure.

Fig. 7 shows a circuit schematic of a flash cell pair 300 according to a second embodiment of the present disclosure. Fig. 8 shows a circuit schematic of a flash array according to a second embodiment of the present disclosure.

As shown in fig. 7, according to an embodiment of the present disclosure, two flash memory cells adjacent in a row direction may constitute one flash memory cell pair 300 including a first flash memory cell 310 and a second flash memory cell 320. For example, the first flash cell 310 may be a0 th row and 0 th column flash cell in a flash memory array, and the second flash cell 320 may be a0 th row and 1 st column flash cell in a flash memory array. Thus, according to embodiments of the present disclosure, a flash array may include pairs of flash memory cells arranged in m rows by n columns.

The first flash unit 310 includes a first memory transistor 311, a gate transistor 312, and a second memory transistor 313 sequentially connected in series in the column direction. The second flash memory cell 320 includes a first memory transistor 321, a gate transistor 322, and a second memory transistor 323 sequentially connected in series in the column direction.

According to an embodiment of the present disclosure, in the first flash memory cell 310, a source region of the first storage transistor 311 is connected to the first electrode S1 of the first flash memory cell 310, and a drain region of the second storage transistor 313 is connected to the second electrode D1 of the first flash memory cell 310.

Further, according to an embodiment of the present disclosure, in the second flash memory cell 320, the source region of the first storage transistor 321 is connected to the first electrode S2 of the second flash memory cell 320, and the drain region of the second storage transistor 323 is connected to the second electrode D2 of the second flash memory cell 320.

The flash cell pairs and flash arrays of the second embodiment of the present disclosure shown in fig. 7 and 8 are substantially the same as the flash cell pairs and flash arrays of the first embodiment of the present disclosure of fig. 3 and 4, except for the manner of connection of the bit line groups of the flash cell pairs.

Specifically, as shown in fig. 7 and 8, according to the second embodiment of the present disclosure, the first bit line BSL0 may be connected to the second electrode D1 of the first flash memory cell 310, the second bit line BLD0 may be connected to the second electrode D2 of the second flash memory cell 320, and the intermediate bit line BLM0 may be connected to the first electrode S1 of the first flash memory cell 310 and the first electrode S2 of the second flash memory cell 320.

Specifically, as shown in (a) of fig. 9, the first and second electrodes of the flash memory cell may be formed of a first metal layer M1 disposed over first, word and second control lines, e.g., polysilicon. As shown in (c) of fig. 9, the intermediate bit line may be formed of the third metal layer M3 in a continuous zigzag manner in the column direction. That is, the intermediate bit line includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction.

Further, as shown in (d) of fig. 9, the first bit line and the second bit line are formed by the fourth metal layer M4 in the column direction and overlap the first portion P1 of the intermediate bit line in the column direction. As shown in (b) of fig. 9, the electrical connection of the intermediate bit line to the first electrode may be achieved through the second metal layer M2 between the first metal layer M1 and the third metal layer M3 and the vias V1 and V2 between the respective metal layers M1 to M3. Further, as shown in (b) and (c) of fig. 9, the electrical connection between the first bit line and the second electrode may be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the through holes V1 to V3 between the respective metal layers M1 to M4. Further, as shown in (b) and (c) of fig. 9, the electrical connection between the second bit line and the second electrode may also be achieved by the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the vias V1 to V3 between the respective metal layers M1 to M4.

The flash memory array according to the above embodiments of the present disclosure may increase the arrangement density of bit lines and may reduce bit line parasitic resistance without increasing the array size. In addition, the flash memory array according to the present disclosure also has better process compatibility and miniaturization characteristics than the prior art flash memory array.

Further, according to an embodiment of the present disclosure, the first control lines or the second control lines adjacent in the column direction may be connected together by a metal layer. Fig. 10 shows a schematic diagram of a layout of control lines of a flash memory array according to an embodiment of the present disclosure.

As shown in fig. 10, for example, on the basis of the flash memory array shown in fig. 4, adjacent first control lines may be connected together in a column direction using first metal control lines MCS <0:m/2-1> formed by a metal layer. In addition, second control lines adjacent in the column direction may be connected together using second metal control lines MCD <1:m/2> formed through the metal layer.

According to embodiments of the present disclosure, the metal layers used to form the first metal control lines MCS <0:m/2-1> and the second metal control lines MCD <1:m/2> may be different from the metal layers used to form the bit lines (including the first bit lines, the intermediate bit lines, and the second bit lines). According to embodiments of the present disclosure, a metal layer for forming the first metal control line MCS <0:m/2-1> and the second metal control line MCD <1:m/2> may be disposed over a metal layer for forming bit lines (including the first bit line, the intermediate bit line, and the second bit line).

According to embodiments of the present disclosure, two flash memory cells adjacent in a column direction may share a control line (a first control line or a second control line) through a metal control line (a first metal control line or a second metal control line). By connecting the first control line and the second control line together using the first metal control line and the second metal control line, parasitic resistance of the first control line and the second control line, such as polysilicon, can be effectively reduced, thereby effectively improving the operation speed of the flash memory array. In addition, the first and second metal control lines are connected together by using the first and second metal control lines, so that the wiring density and the process complexity of the metal control lines can be reduced. In addition, such a flash memory array sharing control lines may also reduce the number of peripheral circuits of the flash memory array for driving the control lines, thereby reducing the area overhead of the peripheral circuits and the manufacturing cost of the memory chip.

Those skilled in the art will recognize that although the flash memory array of the present disclosure is described above in connection with the flash memory cell MC 100 shown in fig. 1, the flash memory array of the present disclosure is not limited to the flash memory cell MC 100 shown in fig. 1. It is contemplated by those skilled in the art in light of the teachings of this disclosure that the flash array of this disclosure may be applied to other types of flash memory cells, such as flash memory cells that include only one storage transistor or flash memory cells that use one storage transistor to store two bits of data, all of which are contemplated as falling within the scope of this disclosure.

Although the present disclosure has been described with reference to the embodiments thereof, those skilled in the art will understand that various modifications and changes may be made thereto without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Claims

1. A flash memory array, comprising:

A plurality of flash memory cells are arranged along a row direction and a column direction perpendicular to the row direction;

a plurality of word line groups extending along the row direction, each word line group comprising a first control line, a word line, and a second control line extending along the row direction; and

A plurality of bit line groups extending along the column direction, each bit line group comprising a first bit line, a middle bit line, and a second bit line;

Wherein, a flash memory cell pair is arranged at the intersection of the word line group and the bit line group, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell which are adjacent in the row direction and share the same bit line group;

The middle bit line is formed from a first metal layer, and

The first bit line and the second bit line are formed of a second metal layer different from the first metal layer;

The middle bit line includes a first portion extending in the column direction and a second portion extending in the row direction, and

The first bit line and the second bit line extend in the column direction;

A first portion of the middle bit line overlaps the first bit line and the second bit line, and a second portion overlaps the word line thereunder.

2. The flash memory array according to claim 1,

Each of the first flash memory cell and the second flash memory cell includes a first storage transistor, a gate transistor, and a second storage transistor sequentially connected in series in the column direction, and

In each of the first flash memory unit and the second flash memory unit, the source region of the first storage transistor is connected to the first electrode of the flash memory unit, and the drain region of the second storage transistor is connected to the second electrode of the flash memory unit.

3. The flash memory array according to claim 2,

Among them, the first bit line is connected to the first electrode of the first flash memory cell of the flash memory cell pair, the second bit line is connected to the second electrode of the second flash memory cell of the flash memory cell pair, and the middle bit line connects the second electrode of the first flash memory cell and the first electrode of the second flash memory cell.

4. The flash memory array according to claim 2,

Among them, the first bit line is connected to the second electrode of the first flash memory cell of the flash memory cell pair, the second bit line is connected to the second electrode of the second flash memory cell of the flash memory cell pair, and the middle bit line connects the first electrode of the first flash memory cell and the first electrode of the second flash memory cell.

5. The flash memory array according to claim 3 or 4, wherein:

The first control line is connected to the gate electrode of the first storage transistor, the word line is connected to the gate electrode of the selection transistor, and the second control line is connected to the gate electrode of the second storage transistor.

6. The flash memory array according to claim 5, wherein:

Two first control lines adjacent to each other in the column direction are connected together through a first common control line, and

Wherein, two second control lines adjacent to each other in the column direction are connected together through a second common control line.

7. The flash memory array according to claim 5, wherein:

The first control line, the word line and the second control line are formed of at least one of polysilicon, silicide and metal gate.

8. The flash memory array according to claim 6, wherein:

The first common control line and the second common control line are formed of a metal layer.

9. A flash memory array, comprising:

a plurality of word line groups extending along the row direction; and

A plurality of bit line groups extending along the column direction,

A flash memory cell pair is arranged at the intersection of the word line group and the bit line group, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell that are adjacent in the row direction and share the same bit line group.

Each bit line group includes a first bit line, a middle bit line, and a second bit line sequentially arranged in the row direction.

Each of the first flash memory unit and the second flash memory unit comprises a first storage transistor, a gate transistor and a second storage transistor connected in series in the column direction, respectively.

wherein, in the first flash memory cell, a source region of the first storage transistor is connected to the first bit line, and a drain region of the second storage transistor is connected to the middle bit line, and

Wherein, in the second flash memory cell, the source region of the first storage transistor is connected to the middle bit line, and the drain region of the second storage transistor is connected to the second bit line;

in,

Each word line group includes a first control line, a word line, and a second control line arranged sequentially in the column direction;

The first control line is connected to the gate electrodes of the first storage transistors in the first flash memory cell and the second flash memory cell, the word line is connected to the gate electrodes of the selection transistors in the first flash memory cell and the second flash memory cell, and the second control line is connected to the gate electrodes of the second storage transistors in the first flash memory cell and the second flash memory cell.