CN113678188A

CN113678188A - Output driver of display device

Info

Publication number: CN113678188A
Application number: CN201980095418.6A
Authority: CN
Inventors: 李玟宰
Original assignee: Aconic Inc
Current assignee: Aconic Inc
Priority date: 2019-05-21
Filing date: 2019-05-28
Publication date: 2021-11-19
Anticipated expiration: 2039-05-28
Also published as: KR102112328B1; WO2020235731A1; CN113678188B

Abstract

An output driver of a display device according to an embodiment of the present invention includes: a digital-to-analog converter for generating a coarse tuning voltage and a fine tuning voltage; a control unit for alternately charging the first capacitor and the second capacitor based on a voltage difference between the coarse adjustment voltage and the fine adjustment voltage; and an amplifier unit that alternately receives the respective charging voltages charged in the first capacitor and the second capacitor and continuously outputs an output voltage, wherein the control unit outputs a second charging voltage charged in the second capacitor to an output node of the amplifier unit during a first charging time in which the first capacitor is charged with the first charging voltage.

Description

Output driver of display device

Technical Field

The present application relates to an output driver of a display device.

Background

Recently, as the size and resolution of the display panel increase, a flexible gamma curve setting and an increase in color depth are required. In order to satisfy the above requirements, an output driver occupying a larger area should be used in a driving circuit of a display device.

Further, the capacities of the load resistor and the load capacitor connected to the output driver increase, and accordingly, the target voltage of the image signal increases. In particular, the slew rate (slew rate) of the amplifier of the output driver may be reduced due to the increase of the load resistance and the load capacity.

Therefore, there is a need for an output driver of a display device that can increase the slew rate of an amplifier by pre-emphasis (pre-emphasic) operation and reduce decoding time and circuit area.

Disclosure of Invention

Therefore, an object of the present invention is to provide an output driver of a display device which can realize high-speed driving by performing sampling work and driving work in parallel; providing an output driver of a display device capable of performing a pre-emphasis operation; an output driver for providing a display device that can support high resolution and can be embodied in a small area; an output driver of a display device is provided that can reduce inter-channel deviation by at least two-step decoding.

Means for solving the problems

The output driver of the embodiment of the present invention includes: a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage; a control unit that alternately charges the first capacitor and the second capacitor based on a voltage difference between the first voltage and the second voltage; and an amplifier unit that alternately receives and outputs the respective charging voltages charged in the first capacitor and the second capacitor, wherein the control unit outputs a second charging voltage charged in the second capacitor to an output node of the amplifier unit during a first charging time in which the first capacitor is charged with the first charging voltage.

In an embodiment, the control section connects one side of the second capacitor to the inverting input terminal of the amplifying section, and connects the other side of the second capacitor to the output node.

In an embodiment, the control portion outputs the charging voltage charged to the first capacitor to the output node during a second charging time in which the second capacitor is charged.

In an embodiment, the control section connects one side of the first capacitor to the inverting input terminal of the amplifying section and connects the other side of the first capacitor to the output node during the second charging time.

In an embodiment, the amplifying part receives the second charging voltage through an inverting input terminal, receives a preset medium voltage through a non-inverting input terminal, and outputs through the output node.

In an embodiment, the control portion electrically connects the non-inverting input terminal and the inverting input terminal between the first charging time and the second charging time.

In an embodiment, the present invention further includes a delay unit for delaying a time for outputting the output voltage to the display panel by a predetermined time.

In an embodiment, the control section further includes a pre-emphasis control section that switches the medium voltage applied to the non-inverting input terminal to one of the first voltage and the second voltage at each of the first charging time and the second charging time.

The output driver of the embodiment of the present invention includes: a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage; a control unit that sequentially charges the first to fourth capacitors with a charging voltage based on a voltage difference between the first voltage and the second voltage; and an amplifying section for outputting to an output node a charging voltage charged to the first to fourth capacitors, wherein the control section connects the second capacitor to the output node of the amplifying section during charging of the first capacitor, and connects the fourth capacitor to the output node of the amplifying section during charging of the third capacitor.

According to an embodiment, the control section connects the third capacitor to the output node of the amplifying section during charging of the second capacitor, and connects the first capacitor to the output node of the amplifying section during charging of the fourth capacitor.

Effects of the invention

In the output driver of the display device according to an embodiment of the present invention, the time required for decoding can be reduced and high-speed driving can be performed by performing the sampling work and the driving work in parallel.

In the output driver of the display device according to an embodiment of the present invention, a pre-emphasis operation may be supported and a Slew Rate (Slew Rate) based on a distance between the data driver and the display panel may be increased.

In the output driver of the display device according to the embodiment of the present invention, the influence due to the parasitic effect of the capacitor can be reduced by connecting one end of the capacitor to the inverting input terminal of the amplifier serving as the virtual ground.

In the output driver of the display device according to an embodiment of the present invention, although there is a deviation between the first capacitor and the second capacitor, an output voltage corresponding to a desired driving voltage can be realized.

In the output driver of the display device according to the embodiment of the invention, a desired data voltage may be stored in one capacitor by the coarse decoder and the fine decoder, and the data voltage in the pixel of the display device may be output by the amplifying part. In this case, since the data voltage is stored in one capacitor, an error of the data voltage in one channel is eliminated. Thus, output deviation in a driver including a plurality of channels can be reduced.

Drawings

Fig. 1 is a block diagram of an output driver of a display device according to an embodiment of the present invention.

Fig. 2 is a circuit diagram specifically illustrating an output driver of the display device of fig. 1.

Fig. 3 is a diagram of the operation timing of the control unit in fig. 2.

Fig. 4 is a first equivalent circuit diagram of the control unit in the reset section of fig. 3.

Fig. 5 is a second equivalent circuit diagram of the control part in the first charging period of fig. 3.

Fig. 6 is a third equivalent circuit diagram of the control part in the first charging period of fig. 3.

Fig. 7 is a circuit diagram of still another embodiment of the control part of fig. 1.

Fig. 8 is a diagram of the operation timing of the delay unit of fig. 7.

Fig. 9 is a circuit diagram of another embodiment of the control section of fig. 1.

Fig. 10 is a diagram showing the operation timing of the pre-emphasis control unit shown in fig. 9.

Fig. 11 is a circuit diagram of still another embodiment of the pre-emphasis control section of fig. 10.

Fig. 12A is a circuit diagram of another embodiment of the pre-emphasis control section of fig. 10.

Fig. 12B is a circuit diagram of still another embodiment of the pre-emphasis control section of fig. 10.

Fig. 13 is a circuit diagram of still another embodiment of the control section of fig. 2.

Fig. 14 is a diagram of the operation timing of the control unit in fig. 13.

Fig. 15 is a first equivalent circuit diagram of the control unit in the first charging section of fig. 14.

Fig. 16 is a second equivalent circuit diagram of the control section in the second charging section of fig. 14.

Fig. 17 is a third equivalent circuit diagram of the control unit in the third charging interval of fig. 14.

Fig. 18 is a fourth equivalent circuit diagram of the control unit in the fourth charging interval of fig. 14.

Fig. 19 is a diagram showing a display device to which an output driver is applied.

Fig. 20 is a diagram of an example of an output driver to which the control unit and the amplifying unit described in fig. 1 to 18 are applied.

Fig. 21 is a diagram of the digital-to-analog converter of fig. 20 in more detail.

Detailed Description

The output driver of the embodiment of the present invention includes: a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage; a control unit that alternately charges the first capacitor and the second capacitor based on a voltage difference between the first voltage and the second voltage; and an amplifier unit that alternately receives and outputs the respective charging voltages charged in the first capacitor and the second capacitor, wherein the control unit outputs a second charging voltage charged in the second capacitor to an output node of the amplifier unit during a first charging time in which the first capacitor is charged with the first charging voltage. The output driver of the display device according to an embodiment of the present invention can reduce the time required for decoding and realize high-speed driving by performing sampling operation and driving operation together.

The specific structures and functions of the embodiments of the inventive concept disclosed in the present specification are illustrated for the purpose of describing the embodiments of the inventive concept, and the embodiments of the inventive concept can be implemented in various forms and are not limited to the embodiments described in the present specification.

Various embodiments of the inventive concept can be variously modified and have various forms, and therefore, the various embodiments are exemplified in the drawings and described in detail in the present specification. However, the embodiments of the present inventive concept are not limited to the specific disclosed forms, but include all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

Although the terms "first" or "second" may be used to describe various structural elements, the structural elements are not limited to the terms. The terms are only used to distinguish one structural element from another structural element, for example, a first structural element may be named a second structural element, and similarly, a second structural element may be named a first structural element without departing from the scope of the inventive concept.

When a certain component is referred to as being "connected" or "in contact with" another component, it is to be understood that the other component may be directly connected or in contact with the certain component, but the other component may be interposed therebetween. On the contrary, when a certain structural element is referred to as being "directly connected" or "directly contacting" with another structural element, it is to be understood that no other structural element exists therebetween. That is, other expressions for describing the relationship between the constituent elements, such as "between", "directly between", "adjacent to", "directly adjacent to", and the like, should be similarly explained.

The terminology used in the description is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless otherwise expressly stated in context, singular expressions include plural expressions. It should be understood that the terms "comprises" or "comprising," or any other variation thereof, in this specification are used solely to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, and do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries should be interpreted as having the same meaning as a meaning of a context in which the related art has been written, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of an output driver 500 of a display device according to an embodiment of the invention.

Referring to fig. 1, the output driver 500 may include a digital-to-analog converter 100, a control part 200, and an amplification part 300.

First, the DAC 100 generates a coarse tuning voltage V_COARSEAnd a trimming voltage V_FINE。

Wherein the voltage V is coarsely adjusted_COARSECan be a wide range of voltage regions regulated in units above a preset voltageCorresponding voltage, trimming voltage V_FINEMay be a voltage corresponding to a voltage interval in a local range adjusted in less than a preset voltage unit. For example, coarse tuning the voltage V_COARSEThe trimming voltage V may correspond to one voltage (e.g., 3V) among voltages (e.g., 0V to 10V) adjusted in a unit of 1V voltage_FINEMay correspond to a coarse tuning voltage V at 3V_COARSETo a voltage of 0.1V unit (e.g., 0.5V).

In the following description, the digital-to-analog converter 100 will be described in further detail with reference to fig. 20.

Then, the voltage is roughly adjusted by the voltage V generated by the digital-to-analog converter 100_COARSEAnd a trimming voltage V_FINEVoltage difference V between_COARSE-V_FINEThe control unit 200 may alternately charge the first capacitor 201 and the second capacitor 202. Wherein the first capacitor 201 and the second capacitor 202 can apply a coarse tuning voltage V to one side_COARSEApplying a trimming voltage V to the other side_FINE。

Specifically, by coarse adjustment of voltage V_COARSEAnd a trimming voltage V_FINEVoltage difference V between_COARSE-V_FINEBased on this, the control portion 200 may set the first charging voltage V during the first charging time H1_C1Charging the first capacitor 201 and a second charging voltage V during a second charging time H2_C2The second capacitor 202 is charged. For example, as shown in fig. 3, the first charging time H1 for charging the first capacitor 201 and the second charging time H2 for charging the second capacitor 202 may be complementary.

Subsequently, the amplifying part 300 may alternately receive the respective charging voltages V charged to the first and

second capacitors

201 and 202_C1、V_C2To continuously output an output voltage V_OUT. Specifically, the amplifying part 300 may receive the second charging voltage V from the control part 200 through the inverting input terminal (-) for the first charging time H1_C2The first charging voltage V may be received from the control part 200 through the input terminal (-) during the second charging time H2_C1。

The amplifying unit 300 may be connected to the non-inverting input terminalSon (+) receives a preset medium voltage V_MID. Wherein the preset medium voltage V_MIDMay be less than the coarse tuning voltage V_COARSEAnd a trimming voltage V_FINEThe voltage of (c).

In this case, at a preset medium voltage V received through the non-inverting input terminal (+)_MIDAnd a charging voltage V alternately received through the inverting input terminals (-) respectively_C1、V_C2On the basis, the amplifying section 300 may alternately generate the first output voltage V_OUT1And a second output voltage V_OUT2. That is, according to the respective charging voltages V alternately received through the inverting input terminal (-)_C1、V_C2The amplifying part 300 can continuously generate the output voltage V_OUT。

In an embodiment of the technical idea of the present invention, the control unit 200 may output the second charging voltage V charged in the second capacitor 202 to the output node 301 of the amplifying unit 300 during the first charging time H1 in which the first capacitor 201 is charged_C2. Furthermore, during the second charging time H2 in which the second capacitor 202 is charged, the control unit 200 may output the first charging voltage V charged in the first capacitor 201 to the output node 301 of the amplifying unit 300_C1。

Thus, the control section 200 can perform the sampling operation of charging the first capacitor 201 and output the second charging voltage (e.g., V) charged in the second capacitor 202 to the output node 301 of the amplifying section 300 in parallel_C2) To realize high-speed driving and to reduce the circuit area for decoding.

Fig. 2 is a circuit diagram for specifically illustrating the control unit 200 of fig. 1, fig. 3 is a diagram illustrating operation timings of the control unit 200 of fig. 2, fig. 4 is a first equivalent circuit diagram of the control unit 200 in the reset period RST of fig. 3, fig. 5 is a second equivalent circuit diagram of the control unit 200 in the first charging time H1 of fig. 3, and fig. 6 is a third equivalent circuit diagram of the control unit 200 in the second charging time H2 of fig. 3.

Referring to fig. 2, the control section 200 may include a first capacitor 201, a second capacitor 202, first to sixth main switches SW1 to SW6, a first sub switch 211_1, a second sub switch 211_2, and a plurality of reset switches SWrst _1 to SWrst _ 3.

First, as shown in fig. 4, when the plurality of reset switches SWrst _1 to SWrst _3 are switched according to the reset signal RST in the interval T0 to T1, the control unit 200 may form a first equivalent circuit.

Specifically, the plurality of reset switches SWrst _1 to SWrst _3 can reset the parasitic capacitances based on the reset signal RST. The reset signal RST may be a control signal for resetting a parasitic capacitance of at least one of the first capacitor 201 and the second capacitor 202.

For example, as shown in fig. 4, the first reset switch SWrst _1 of the plurality of reset switches SWrst _1 to SWrst _3 can connect the other side of the first capacitor 201 to a preset middle voltage V based on the reset signal RST_MIDSo that the parasitic capacitance of the Vy node connected to the first capacitor 201 is reset to the medium voltage V_MID。

And, the second reset switch SWrst _2 can connect the other side of the second capacitor 202 to a preset middle voltage V based on the reset signal RST_MIDSo that the parasitic capacitance of the Vx node connected to the second capacitor 202 is reset to the medium voltage V_MID. The third reset switch SWrst _3 can connect the inverting input terminal (-) of the amplifying unit 300 to the medium voltage V through the non-inverting input terminal (+) based on the reset signal RST_MID。

Next, as shown in fig. 5, in a section H1 from T1 to T2, when the first main switch SW1, the second main switch SW2, the third main switch SW3, and the first sub switch 211_1 are switched according to the first main control signal Φ 1 and the first sub control signal Φ 1e, the control section 200 may form a second equivalent circuit.

Specifically, in the interval H1 from T1 to T2, the first main switch SW1 and the first sub switch 211_1 can apply the coarse adjustment voltage V to the first capacitor 201 based on the first main control signal Φ 1 and the first sub control signal Φ 1e_COARSEAnd a trimming voltage V_FINEVoltage difference V between_COARSE-V_FINETo generate a charging voltage V_C1。

Wherein the first main control signal Φ 1 and the first sub control signal Φ 1e serve as control signals for charging the first capacitor 201, and a time for activating the first sub control signal Φ 1e may be less than a time for activating the first main control signal Φ 1, so that the first capacitor 201 is easily charged.

As shown in fig. 5, the first main switch SW1 can connect one side of the first capacitor 201 to the coarse voltage node 111_1 based on the first main control signal Φ 1 during a period H1 from T1 to T2. In the H1 interval T1 to T2, the first sub switch 211_1 can connect the other side of the first capacitor 201 to the trimming voltage node 121_1 based on the first sub control signal Φ 1 e. That is, the first main switch SW1 and the first sub-switch 211_1 apply the coarse tuning voltage V to the first capacitor 201 during the interval T1 to T2_COARSEAnd a trimming voltage V_FINE。

In this case, in a section H1 from T1 to T2, the second main switch SW2 and the third main switch SW3 can apply the second charging voltage V charged in the second capacitor 202 to the inverting input terminal (-) of the amplifying unit 300 and the output node 301 of the amplifying unit 300 based on the first main control signal Φ 1_C2。

The first main control signal Φ 1 of an embodiment of the present invention may be a voltage for applying a second charging voltage V, which charges the second capacitor 202, to the inverting input terminal (-) of the amplifying part 300 and the output node 301 of the amplifying part 300_C2The control signal of (2).

As shown in fig. 5, the second main switch SW2 can connect one side of the second capacitor 202 to the inverting input terminal (-) of the amplifying section 300 based on the first main control signal Φ 1. Also, the third main switch SW3 can connect the other side of the second capacitor 202 to the output node 301 based on the first main control signal Φ 1.

In contrast, in the interval H1 from T1 to T2, the amplifying part 300 may output the second charging voltage V through the output node 301_C2And for a preset medium voltage V_MIDFirst output voltage V_OUT1. Wherein the first output voltage V_OUT1May be the second charging voltage V applied to the amplifying section 300_C2And a preset medium voltage V applied to the amplifying part 300_MIDThe sum (V)_COARSE-V_FINE+V_MID). That is, in the interval H1 from T1 to T2, the first main switch SW1 and the first sub-switch 211_1 may charge the first capacitor 201, and the second main switch SW2 and the third main switch 210_3 may output the first output voltage V through the amplifying part 300_OUT1。

Thereafter, the plurality of reset switches SWrst _1 to SWrst _3 can reset the parasitic capacitance of at least one of the first capacitor 201 and the second capacitor 202 based on the reset signal RST in the interval T2 to T3, similarly to the interval T0 to T1. For example, the plurality of reset switches SWrst _1 to SWrst _3 are switched according to the reset signal RST, so that the equivalent circuit similar to the first equivalent circuit of fig. 4 can be formed.

Next, as shown in fig. 6, in a section H2 from T3 to T4, when the fourth main switch SW4, the fifth main switch SW5, the sixth main switch SW6 and the second sub-switch 211_2 are switched by the second main control signal Φ 2 and the second sub-control signal Φ 2e, the control section 200 may form a third equivalent circuit.

Specifically, the fourth main switch SW4 and the second sub switch 211_2 can apply the coarse tuning voltage V to the second capacitor 202 based on the second main control signal Φ 2 and the second sub control signal Φ 2e_COARSEAnd a trimming voltage V_FINEVoltage difference V between_COARSE-V_FINEAnd generates a charging voltage V_C2。

Where the second main control signal Φ 2 and the second sub control signal Φ 2e are control signals for charging the second capacitor 202, the time for activating the second sub control signal Φ 2e may be less than the time for activating the second main control signal Φ 2, so that the second capacitor 202 is easily charged.

As shown in fig. 6, in a period H2 from T3 to T4, the fourth main switch SW4 can connect one side of the second capacitor 202 to the coarse voltage node 111_1 based on the second main control signal Φ 2. In the interval T3 to T4, the second sub switch 211_2 can connect the other side of the second capacitor 202 to the trimming voltage node 121_1 based on the second sub control signal Φ 2 e. That is, in the interval from T3 to T4, the fourth main switch SW4 and the second sub-switch 211_2 can be operated by applying the coarse adjustment voltage V to both sides of the second capacitor 202_COARSEAnd a trimming voltage V_FINETo charge with a charging voltage V_C2And charging is carried out.

In this case, in the interval H2 from T3 to T4, the fifth main switch SW5 and the sixth main switch SW6 can output the first charging voltage V charged in the first capacitor 202 to the output node 301 of the amplifying unit 300 based on the second main control signal Φ 2_C1。

The second main control signal Φ 2 of an embodiment may be a voltage V for outputting the first charging voltage V charged into the first capacitor 201 to the output node 301 of the amplifying section 300_C1The control signal of (2).

Specifically, the fifth main switch SW5 can connect one side of the first capacitor 201 to the inverting input terminal (-) of the amplifying section 300 on the basis of the second main control signal Φ 2. Also, the sixth main switch SW6 can connect the other side of the first capacitor 201 to the output node 301 based on the second main control signal Φ 2. In contrast, in the interval H2 from T3 to T4, the amplifying part 300 may output the first charging voltage V through the output node 301_C1And for a preset medium voltage V_MIDSecond output voltage V_OUT2. Wherein the second output voltage V_OUT2May be the first charging voltage V applied to the amplifying section 300_C1And a preset medium voltage V applied to the amplifying part 300_MIDThe sum (V)_COARSE-V_FINE+V_MID). That is, in the interval T3 to T4, the fourth main switch SW4 and the second sub-switch 211_2 may be used to charge the second capacitor 202, and at the same time, the fifth main switch SW5 and the sixth main switch SW6 may output the second output voltage V through the amplifying part 300_OUT2。

Next, similarly to the interval T0 to T1, the plurality of reset switches SWrst _1 to SWrst _3 can reset the parasitic capacitance of at least one of the first capacitor 201 and the second capacitor 202 based on the reset signal RST in the interval T4 to T5.

Subsequently, in a period H1 from T5 to T6, the first main switch SW1 and the first sub-switch 211_1 can be based on the first main control signal Φ 1 and the first sub-control signal Φ 1e based on the first charging voltage V_C1The first capacitor 201 is charged. Meanwhile, a second main switch SW2 and a fourth main switchThe three-main switch SW3 can output a first output voltage V via the amplifying unit 300 based on the first main control signal Φ 1_OUT1。

Fig. 7 is a circuit diagram of still another embodiment of the control unit 200 of fig. 1, and fig. 8 is a diagram illustrating an operation timing of the delay unit 240 of fig. 7.

Referring to fig. 7 and 8, the control section 200 may include a first capacitor 201, a second capacitor 202, first to sixth main switches SW1 to SW6, a first sub switch 211_1, a second sub switch 211_2, a plurality of reset switches SWrst _1 to SWrst _3, and a delay section 240.

The circuit of fig. 7 is similar to the circuit of fig. 2. Here, for convenience of explanation, the repeated explanation of the same reference numerals explained in fig. 1 to 6, for example, the first capacitor 201, the second capacitor 202, the first to sixth main switches SW1 to SW6, the first sub switch 211_1, the second sub switch 211_2, and the plurality of reset switches 230_1 to 230_3, will be omitted.

The delay part 240 may output the first output voltage V to the display panel 700 through the amplifying part 300_OUT1Or the second output voltage V_OUT2The output time of (2) is delayed by a prescribed time.

More specifically, as shown in fig. 8, the delay section 240 can electrically connect the output node 301 of the amplifying section 300 and the display panel 700 to each other on the basis of the delay signal HIGH _ Z _ SW. Wherein the delay signal HIGH _ Z _ SW may be for the first output voltage V_OUT1Or the second output voltage V_OUT2Is delayed by a predetermined time and is activated at a predetermined time point in each of the activation periods of the first switching signal Φ 1 and the second switching signal Φ 2.

For example, as shown in fig. 8, delay unit 240 may electrically short output node 301 of amplifying unit 300 and display panel 700 to a predetermined time point (e.g., T1.5) in the interval from T1 to T2, and may electrically connect output node 301 of amplifying unit 300 and display panel 700 to each other from the predetermined time point (e.g., T1.5) to T2.

That is, the delay unit 240 may switch to the first switching signal Φ 1 and the second switching signal Φ 2 in response to the delay signal HIGH _ Z _ SW activated at a predetermined time point in each activation period of the first switching signal Φ 1 and the second switching signal Φ 2The display panel 700 outputs the first output voltage V output through the amplifying part 300_OUT1Or the second output voltage V_OUT2。

Fig. 9 to 12 are views illustrating another embodiment of the control part 200 of fig. 1. For example, unlike the circuits illustrated in fig. 2-8, the circuits of fig. 9-12 may also support pre-emphasis operation.

Specifically, fig. 9 is a diagram showing the control unit 200 including the pre-emphasis control unit 250, and fig. 10 is a diagram showing the operation timing of the pre-emphasis control unit 250 of fig. 9. Fig. 11 is a circuit diagram of a further embodiment of the pre-emphasis control unit 250 of fig. 9, and fig. 12 is a circuit diagram of another embodiment of the pre-emphasis control unit 250 of fig. 9.

First, referring to fig. 9 and 10, the control part 200 may include a first capacitor 201, a second capacitor 202, first to sixth main switches SW1 to SW6, a first sub-switch 211_1, a second sub-switch 211_2, a plurality of reset switches 230_1 to 230_3, and a pre-emphasis control part 250.

Hereinafter, for convenience of explanation, a repetitive explanation of the same reference numerals explained in fig. 2 to 7, for example, the first capacitor 201, the second capacitor 202, the first to sixth main switches SW1 to SW6, the first sub switch 211_1, the second sub switch 211_2, and the plurality of reset switches 230_1 to 230_3 will be omitted.

Pre-emphasis control part 250 of an embodiment may include a first pre-emphasis switch 251 and a second pre-emphasis switch 252.

According to an embodiment, the pre-emphasis control part 250 may control the pre-emphasis by applying a preset middle voltage V to the non-inverting input terminal (+) of the amplifying part 300_MIDSwitching to a coarse tuning voltage V_COARSESo as to carry out the operation for the first output voltage V_OUT1And a second output voltage V_OUT2Pre-emphasis operation of (1).

Specifically, the first pre-emphasis switch 251 can electrically connect the non-inverting input terminal (+) of the amplifying section 300 with the coarse voltage node 111_1 based ON the pre-emphasis control signal PREM _ ON. The pre-emphasis control signal PREM _ ON may be a signal activated for a predetermined time according to the reset signal RST. In this case, the second pre-emphasis switch 252 can short-circuit the non-inverting input terminal (+) of the amplifying section 300 and the middle voltage node 250_1 to each other based ON the pre-emphasis control signal PREM _ ON.

Then, the second pre-emphasis switch 252 can make the non-inverting input terminal (+) of the amplifying section 300 and the applying medium voltage V based ON the pre-emphasis reverse signal/PREM _ ON_MIDIs electrically connected to the medium voltage node 250_ 1. Wherein, the pre-emphasis inversion signal/PREM _ ON may be an inversion signal for the pre-emphasis control signal PREM _ ON. In this case, the first pre-emphasis switch 251 can short-circuit the non-inverting input terminal (+) of the amplifying section 300 and the middle voltage node 250_1 to each other based ON the pre-emphasis reverse signal/PREM _ ON.

As shown in fig. 9, pre-emphasis control unit 250 can apply coarse adjustment voltage V to non-inverting input terminal (+) based ON pre-emphasis control signal PREM _ ON_COARSE. Thus, the amplifying section 300 may output the first pre-emphasis voltage V_PREOUT1. Wherein the first pre-emphasis voltage V_PREOUT1May be greater than the second output voltage V_OUT2Voltage (V) of_COARSE-V_FINE+V_COARSE)。

On the other hand, the above description is illustrative, and the technical idea of the present invention is not limited thereto. For example, pre-emphasis using a coarse voltage is illustratively shown in fig. 9 and 10. However, according to still another embodiment, the pre-emphasis control section 250 may also perform the pre-emphasis operation using the trimming voltage. I.e. to achieve a voltage V for the first output voltage_OUT1And a second output voltage V_OUT2Pre-emphasis operation of (1), the pre-emphasis control section 250 may apply a preset intermediate voltage V to the non-inverting input terminal (+) of the amplifying section 300_MIDSwitching to a trimming voltage V_FINE。

For example, as shown in fig. 11, the first pre-emphasis switch 251 can electrically connect the non-inverting input terminal (+) of the amplifying section 300 with the fine tuning voltage node 121_1 ON the basis of the pre-emphasis control signal PREM _ ON. In this case, the second pre-emphasis switch 252 can short-circuit the non-inverting input cell (+) of the amplifying section 300 and the fine tuning voltage node 121_1 to each other based ON the pre-emphasis control signal PREM _ ON.

Then, secondThe pre-emphasis switch 252 can cause the non-inverting input terminal (+) of the amplifying section 300 to apply a preset medium voltage V based ON the pre-emphasis inversion signal/PREM _ ON_MIDIs electrically connected to the medium voltage node 250_ 1. In this case, the first pre-emphasis switch 251 can short-circuit the non-inverting input terminal (+) of the amplifying section 300 and the trimming voltage node 121_1 to each other with the pre-emphasis reverse signal/PREM _ ON.

That is, pre-emphasis control unit 250 can apply trimming voltage V to non-inverting input terminal (+) based ON pre-emphasis control signal PREM _ ON_FINE. Thus, the amplifying part 300 may output the second pre-emphasis voltage V_PREOUT2. Wherein the second pre-emphasis voltage V_PREOUT2May be greater than the second output voltage V_OUT2Voltage (V) of_COARSE-V_FINE+V_FINE)。

Also, in another embodiment of the present invention, the pre-emphasis control unit 250 may perform the pre-emphasis operation by selecting one of the coarse tuning voltage and the fine tuning voltage. That is, pre-emphasis control unit 250 may apply a preset intermediate voltage V to non-inverting input terminal (+)_MIDSwitching to a coarse tuning voltage V_COARSEAnd a trimming voltage V_FINEOne of them.

For example, as shown in fig. 12A, the pre-emphasis control unit 250 may further include a first selection switch 253_1 and a second selection switch 253_ 2. Specifically, the first selection switch 253_1 and the second selection switch 253_2 can connect one of the trim voltage node 111_1 and the trim voltage node 121_1 to the second pre-emphasis switch 252 by the first selection signal SEL1 and the second selection signal SLE 2.

That is, pre-emphasis control unit 250 can apply coarse adjustment voltage V to non-inverting input cell (+) based on first selection signal SEL1 and second selection signal SLE2_COARSEAnd a trimming voltage V_FINEOne voltage of (2). Thus, the amplifier 300 can adjust the voltage V roughly_COARSEAnd a trimming voltage V_FINEGenerates a pre-emphasis voltage based on one of the voltages.

On the other hand, it should be understood that the above description is illustrative, and the technical idea of the present invention is not limited thereto. For example, performing pre-emphasis operation with a coarse tuning voltage and a fine tuning voltage is illustrated in fig. 9-12A. In this case, the coarse tuning voltage may be a voltage output by the coarse tuning digital-to-analog converter, and the fine tuning voltage may be a voltage output by the fine tuning digital-to-analog converter. However, in another embodiment of the present invention, the control unit may utilize an additional circuit to generate the voltage for pre-emphasis operation instead of the coarse tuning dac or the fine tuning dac.

For example, the control part of still another embodiment of the present invention may further include an additional circuit for generating the pre-emphasis voltage. In this case, as shown in fig. 12B, the control section may also perform the pre-emphasis operation by the pre-emphasis voltage received by the additional circuit.

On the other hand, it is illustrated in fig. 2 to 12 that the control section includes two capacitors. However, it should be understood that this is merely an example, and the technical idea of the present invention is not limited thereto. For example, the control unit according to still another embodiment of the present invention may also include 4 or more than 4 capacitors, which will be described in further detail below with reference to fig. 13 to 18.

Fig. 13 is a circuit diagram illustrating still another embodiment of the control unit 200 of fig. 2, and fig. 14 is a diagram illustrating operation timings of the control unit 200 of fig. 13. FIG. 15 shows the first charging interval T Φ in FIG. 14_PRE1Fig. 16 is a first equivalent circuit diagram of control unit 200 in fig. 14, showing a second charging interval T Φ_PRE2Fig. 17 is a second equivalent circuit diagram of the control unit 200 in fig. 14, in the third charging interval T Φ_PRE3Fig. 18 is a third equivalent circuit diagram of the control unit 200 in fig. 14, showing a fourth charging interval T Φ_PRE4The fourth equivalent circuit diagram of the control section 200 in (1).

Referring to fig. 13 to 18, the control part 200 may include first to fourth capacitors C1 to C4, first to tenth synchronous main switches SW _ P1 to SW _ P10, first to fourth synchronous sub-switches 211_3 to 211_6, a reset switch 230_1, and first to fourth reference voltage switches 260_1 to 260_ 4.

First, in the interval from T0 to T1, the reset switch 230_1 can reset the parasitic capacitance of the capacitor based on the reset signal RST.

Next, as shown in FIG. 15, in the interval T1-T2, T Φ_PRE1When the first through third synchronous main switches SW _ P1 through SW _ P3 and the first synchronous sub-switch 211_3 are operated according to the first synchronous control signal Φ_PRE1When switching, the control unit 200 may form a fourth equivalent circuit.

Specifically, T phi is in the interval of T1-T2_PRE1The first synchronous main switch SW _ P1 and the first synchronous sub-switch 211_3 can be controlled by the first synchronous control signal Φ_PRE1Based on a first charging voltage V_C1The first capacitor C1 is charged.

In this case, the second and third synchronous main switches SW _ P2 and SW _ P3 can be controlled by the first synchronous control signal Φ_PRE1Applying a second charging voltage V charged in a second capacitor 202 to the inverting input terminal (-) of the amplifying section 300 and the output node 301 of the amplifying section 300 on the basis_C2. Thus, the amplifying part 300 may output the first output voltage V_OUT1. In this case, similarly to the case described above, the first output voltage V_OUT1Can have V_COARSE-V_FINE+V_MIDThe voltage level of (c).

Subsequently, in the interval T2 to T3, the reset switch 230_1 can reset the parasitic capacitance of the capacitor based on the reset signal RST.

Then, as shown in FIG. 16, in the interval T phi from T3 to T4_PRE2When the fourth through sixth synchronous main switches SW _ P4 through SW _ P5 and the second synchronous sub-switch 211_4 are operated according to the second synchronous control signal Φ_PRE2When switching, the control unit 200 may form a fifth equivalent circuit.

Specifically, T phi is in the interval of T3-T4_PRE2The fourth synchronous main switch SW _ P4 and the second synchronous sub switch 211_4 can be controlled by the second synchronous control signal Φ_PRE2Based on a third charging voltage V_C3The third capacitor 203 is charged. The interval T1 to T4 may correspond to the first charging interval H1 of fig. 1.

In this case, the fifth and sixth synchronous main switches SW _ P5 and SW _ P6 may sum up to the inverting input terminal (-) of the amplifying section 300Output node 301 of large part 300 applies fourth charging voltage V that charges fourth capacitor 204_C4. Thus, the amplifying part 300 can output the second output voltage V_OUT2。

In this case, as shown in fig. 14, the first output voltage V_OUT1May be greater than the second output voltage V_OUT2The voltage level of (c). That is, in the interval T1 to T2, the pre-emphasis operation can be performed.

Thereafter, in the interval T4 to T5, the reset switch 230_1 can reset the parasitic capacitance of the capacitor based on the reset signal RST.

Next, as shown in FIG. 17, in the interval T5-T6, T Φ_PRE3When the first through ninth synchronous main switches SW _ P7 through SW _ P9 and the third synchronous sub switch 211_5 are operated according to the third synchronous control signal Φ_PRE3When switching is performed, the control unit 200 may form a sixth equivalent circuit.

Specifically, T phi is in the interval of T5-T6_PRE3The seventh synchronous master switch SW _ P7 and the third synchronous slave switch 211_5 can be controlled by the third synchronous control signal Φ_PRE3Based on a second charging voltage V_C2Charging the second capacitor C2.

And, in the interval T5-T6, T phi_PRE3The eighth and ninth synchronous master switches SW _ P8 and SW _ P9 can be controlled by the third synchronous control signal Φ_PRE3First charging voltage V charged to first capacitor C1 is applied to inverting input terminal (-) of amplifying unit 300 and output terminal 301 of amplifying unit 300 on the basis_C1。

Subsequently, in the interval T6 to T7, the reset switch 230_1 can reset the parasitic capacitance of the capacitor based on the reset signal RST.

Then, as shown in FIG. 18, in the interval T Φ T7 to T8_PRE4When the tenth through twelfth sync main switches SW _ P10 through SW _ P12 and the fourth sync sub switch 211_6 are operated according to the fourth sync control signal Φ_PRE4When switching is performed, the control section 200 may form a seventh equivalent circuit.

Specifically, T phi is in the interval of T7-T8_PRE4The tenth synchronous main switch SW _ P10 and the fourth synchronous sub-switch 211_6 can be controlled by a fourth synchronization control signal phi_PRE4Based on a fourth charging voltage V_C4The fourth capacitor 204 is charged. The interval T5 to T8 may correspond to the second charging interval H2 of fig. 1.

In this case, the eleventh and twelfth synchronous main switches SW _ P11 and SW _ P12 may apply the third charging voltage V charged into the third capacitor 203 to the inverting input terminal (-) of the amplifying part 300 and the output node 301 of the amplifying part 300_C3. Thus, the amplifying part 300 may output the fourth output voltage V_OUT4。

Fig. 19 is a diagram showing a display device 1000 to which the output driver illustrated in fig. 1 to 18 is applied. Referring to fig. 19, the display apparatus 1000 may include an output driver 1100, a data driver 1200, and a display panel 1300.

The data driver 1200 may receive pixel data for driving the display panel 1300 and transmit a digital signal to the output driver 1100. For example, the digital signal may be a signal for generating a coarse tuning voltage and a fine tuning voltage.

The display panel 1300 can display an image in a frame unit based on the output voltage received through the output driver 1100. For example, the display panel 1300 may be a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display, an Organic Light Emitting Diode (OLED) display, an active-matrix organic light emitting diode (AMOLED) display, a flexible display (flexible) display, or other types of flat panel displays.

In an embodiment of the technical idea of the present invention, the output driver 1100 may be driven by the output driver illustrated in fig. 1 to 18.

Fig. 20 is a diagram showing an example of an output driver to which the control section and the amplifying section described in fig. 1 to 18 are applied, and fig. 21 is a diagram showing the digital-analog converter 2300 in fig. 20 in more detail.

As shown in fig. 20, the output driver 2000 may include a shift register 2100, a data latch 2200, a Digital-to-Analog Converter 2300 (DAC), and an output buffer 2400.

The shift register 2100 may include a plurality of stages (not shown) that are attached. The plurality of stages may receive a data clock signal. The horizontal start signal may be applied to a first stage of the plurality of stages. If the operation of the first stage is started by the horizontal start signal, the plurality of stages may sequentially output control signals in response to the data clock signal (CLK).

Data latch 2200 may comprise a plurality of latch circuits. The plurality of latch circuits may sequentially receive control signals from the plurality of stages. The data latch 2200 can store the image data (RGB) in units of pixel lines. The plurality of latch circuits may store the image data corresponding to the image data (RGB) in response to the control signals, respectively. The latch 320 may provide the digital-to-analog converter 2300 with the image data (RGB) corresponding to the pixel row size stored as described above.

The digital-to-analog converter 2300 may receive the reference demodulation voltage generated from the gradation voltage generation part. The digital-to-analog converter 2300 may include a plurality of digital-to-analog converter circuits corresponding to the plurality of data latch circuits. The digital-analog converter 2300 may convert the image data of the pixel row amount supplied from the data latch 2200 into a gradation voltage.

The output buffer 2400 receives the demodulation voltage from the digital-to-analog converter 2300. The output buffer 2400 may buffer the above-described gradation voltages and supply them to the data lines.

In an embodiment of the technical idea of the present invention, the output buffer 2400 may include the control portion and the amplifying portion illustrated in fig. 1 to 18.

Referring to fig. 21, the digital-to-analog converter 2300 may include an M-bit decoder 2310 and an N-bit decoder 2320. For example, the M-bit decoder 2310 may generate the coarse tuning voltages illustrated in fig. 1-18. The N-bit decoder 2320 may generate the trimming voltages illustrated in fig. 1-18.

For example, the M-bit decoder 2310 may generate a coarse adjustment voltage by a voltage distribution method based on the data signal received from the gamma generating part 3000 and output the generated coarse adjustment voltage. The N-bit decoder 2320 can generate a trimming voltage by a voltage distribution method based on the data signal received from the gamma generating unit 3000 and output the generated trimming voltage.

As described above, the output driver of the display device according to an embodiment of the present invention can reduce the time required for decoding and can drive at high speed by performing the sampling work and the driving work in parallel. Further, the present invention has an advantage in that since the feedback factor in the feedback amplifier configuration is "1", the bandwidth of the amplifier can be maximally utilized, thereby realizing high-speed driving.

Also, the output driver of the display device according to an embodiment of the present invention may support a pre-emphasis operation and may increase a Slew Rate (Slew Rate) based on a distance between the data driver and the display panel.

In addition, the output driver of the display device according to the embodiment of the invention can reduce the influence due to the parasitic effect of the capacitor by connecting one end of the capacitor to the inverting input terminal of the amplifier serving as the virtual ground.

In addition, the output driver of the display device according to the embodiment of the present invention can realize an output voltage corresponding to a desired driving voltage despite a deviation between the first capacitor and the second capacitor.

In addition, the output driver of the display device according to an embodiment of the present invention may store a desired data voltage in one capacitor through the coarse decoder and the fine decoder, and output the data voltage in the pixel of the display device through the amplifying part. In this case, since the data voltage is stored in one capacitor, an error of the data voltage in one channel is eliminated. Thus, output deviation in a driver including a plurality of channels can be reduced.

The embodiments of the present invention disclosed in the specification and the drawings are only specific examples provided for easily explaining technical contents of the present invention and helping understanding of the present invention, and do not limit the scope of the present invention. It is apparent that those skilled in the art to which the present invention pertains can implement other modifications based on the technical idea of the present invention, in addition to the embodiments disclosed herein.

Industrial applicability

The present invention relates to an output driver of a display device, which can reduce decoding time and realize high-speed driving and has industrial applicability.

Claims

1. An output driver, comprising:

a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage;

a control unit that alternately charges the first capacitor and the second capacitor based on a voltage difference between the first voltage and the second voltage; and

an amplifying section that alternately receives and outputs the respective charging voltages charged in the first capacitor and the second capacitor,

wherein the control section outputs a second charging voltage charged in the second capacitor to an output node of the amplifying section for a first charging time in which the first capacitor is charged with a first charging voltage.

2. The output driver of claim 1,

the control section connects one side of the second capacitor to the inverting input terminal of the amplifying section and connects the other side of the second capacitor to the output node during the first charging period.

3. The output driver of claim 1,

the control portion outputs the charging voltage charged in the first capacitor to the output node for a second charging time in which the second capacitor is charged.

4. The output driver of claim 3,

the control unit connects one side of the first capacitor to the inverting input terminal of the amplifying unit and connects the other side of the first capacitor to the output node during the second charging period.

5. The output driver of claim 1,

the amplifying part receives the second charging voltage through an inverting input terminal and receives a preset medium voltage through a non-inverting input terminal to be output through the output node.

6. The output driver of claim 5,

the control portion electrically connects the non-inverting input terminal and the inverting input terminal between the first charging time and the second charging time.

7. The output driver of claim 5,

the display device further includes a delay unit for delaying a time for outputting the output voltage to the display panel by a predetermined time.

8. The output driver of claim 5,

the control section further includes a pre-emphasis control section that switches the medium voltage applied to the non-inverting input terminal to one of the first voltage and the second voltage every the first charging time and the second charging time.

9. An output driver, comprising:

a control section sequentially charging the first to fourth capacitors with a charging voltage based on a voltage difference between the first voltage and the second voltage; and

an amplifying section for outputting the charging voltages charged in the first to fourth capacitors to an output node,

wherein the control section connects the second capacitor to the output node of the amplifying section during charging of the first capacitor, and connects the fourth capacitor to the output node of the amplifying section during charging of the third capacitor.

10. The output driver of claim 9,

the control section connects the third capacitor to the output node of the amplifying section during charging of the second capacitor, and connects the first capacitor to the output node of the amplifying section during charging of the fourth capacitor.