CN113676057A - A LLC Synchronous Rectifier Circuit Based on Secondary Current Simulation - Google Patents

Abstract

The invention provides an LLC (logic link control) synchronous rectification drive circuit for simulating secondary current. The method aims at the problem that the duty ratio is lost due to the fact that parasitic inductance exists in an actual synchronous rectification MOS drain-source electrode, and the difference between the driving turn-off moment and an ideal driving state is large. The auxiliary winding of resonant inductor and the auxiliary winding of transformer are connected in series at the secondary side, the output signal is input into the integrating circuit, and the output signal v of the integrating circuit_iSRThe rectified signal is the rectified current i of the secondary side_SRA proportional voltage signal. Using this voltage signal instead of v_{ds_SR}The SR driving signal is generated, the problem that the duty ratio of the SR driving signal is lost due to parasitic inductance can be effectively solved, the loss of the synchronous rectification MOS is reduced, and the efficiency of the converter is improved.

Description

A LLC Synchronous Rectifier Circuit Based on Secondary Current Simulation

technical field

The invention relates to the field of electronic technology, in particular to an LLC synchronous rectification circuit based on secondary current simulation.

Background technique

At present, with the miniaturization of consumer electronics and IT equipment, higher requirements are placed on the miniaturization and high efficiency of DC-DC power supplies. Because the LLC circuit topology has many advantages, especially the zero-voltage turn-on (ZVS) of the primary switch and the zero-current turn-off (ZCS) of the secondary rectifier can be achieved without adding any auxiliary circuits, which can reduce the Switching losses of small switches and rectifiers. Therefore, LLC circuit topology can easily obtain higher efficiency, and can be widely used in various power supplies.

In order to further improve the LLC topology efficiency, in the case of a large load current, a synchronous rectification technology is usually used, that is, a low-voltage synchronous rectification MOS transistor (SR) is used to replace the rectifier diode. Taking advantage of the very small on-resistance of the low-voltage MOS transistor, its on-state voltage drop is much smaller than that of the rectifier diode. However, the synchronous rectifier MOS tube needs a driving circuit during the conduction period to make it work. For the synchronous rectification driving problem, there are many driving methods, but the most widely used in business is to detect the voltage across the synchronous rectification MOS transistor D (drain) S (source) to obtain the driving signal, as shown in Figure 1 . Figure 2 is the ideal waveform of its work. When a current flows through the synchronous rectification diode, a relatively large negative voltage drop V _ds is generated across the DS of the synchronous rectification MOS. When the V _ds voltage is lower than the driving turn-on voltage V _{th_on} , the driver chip generates the driving of the synchronous rectification MOS. signal V _{gs_SR} . At this time, the voltage drop of the synchronous rectification MOS is V _ds =i _SR ·R _on , where i _SR is the current of the synchronous rectification MOS, and R _on is the on-resistance of the synchronous rectification MOS. As the synchronous rectifier MOS transistor i _SR drops close to zero, the V _ds voltage is also close to zero. When V _ds is greater than the turn-off voltage V _{th_off} , the drive signal V _{gs_SR is} turned off, and V _{th_off} is a voltage close to zero volts. In this way, the turn-on time of the diode of the synchronous rectifier MOS can be reduced to a very small extent.

However, there are various parasitic inductances in the actual synchronous rectification MOS drain, including MOS package inductance and PCB trace inductance, etc. The model is shown in Figure 3. _LSR is the total parasitic inductance of the synchronous rectification MOS. The actually detected DS terminal voltage of the synchronous rectifier MOS transistor is V _d's .

所以实际检测到的V_d′s比理想的V_ds更早达到驱动关断阀值电压V_{th_off}。因此，实际的同步整流MOS管的驱动信号V′_{gs_SR}比理想的驱动信号V_{gs_SR}更早关断，造成占空比丢失。导致同步整流MOS管二极管导通时间增加，增加了同步整流MOS的损耗，这样情况在高频和重载情况下更为严重。The driving waveform turn-on process is the same as that in FIG. 2 and will not be repeated here. But the drive off moment is very different from the ideal drive. Since the induced voltage of the parasitic inductance L _SR is reversed when the synchronous rectification MOS current i _SR decreases, the actually detected DS terminal voltage of the synchronous rectification MOS is

So the actual detected V _d's reaches the drive-off threshold voltage V _{th_off} earlier than the ideal V _ds . Therefore, the actual driving signal V' _{gs_SR} of the synchronous rectification MOS transistor is turned off earlier than the ideal driving signal V _{gs_SR} , resulting in a loss of duty cycle. As a result, the conduction time of the synchronous rectifier MOS tube diode is increased, and the loss of the synchronous rectifier MOS is increased, which is more serious in the case of high frequency and heavy load.

SUMMARY OF THE INVENTION

Aiming at the problem that there is parasitic inductance in the drain-source electrode of the actual synchronous rectifier MOS, which leads to a big difference between the drive off moment and the ideal drive state, resulting in the loss of the duty cycle, the present invention proposes an LLC synchronous rectifier control circuit for simulating secondary current. . The auxiliary winding of the resonant inductor and the auxiliary winding of the transformer are connected in series on the secondary side, and the output signal is input to the integrating circuit. The output signal v _iSR of the integrating circuit is rectified and the signal is a voltage signal proportional to the rectified current i _SR on the secondary side. . This voltage signal is used to replace V _{ds_SR} to generate the drive signal of the synchronous rectifier MOS, thereby effectively solving the problem of the loss of the duty cycle of the SR drive signal due to parasitic inductance, reducing the loss of the synchronous rectifier MOS and improving the efficiency of the converter.

Specifically, a LLC synchronous rectifier circuit based on secondary current simulation proposed by the present invention includes: the power circuit includes: a DC input voltage V _in , two main power transistors Q ₁ and Q ₂ of the half-bridge circuit, and a resonant capacitor C _r , resonant inductor L _r , LLC main transformer T ₁ , secondary side synchronous rectifier tubes S ₁ and S ₂ , output capacitor C _o and load;

The control part includes: resonant inductor auxiliary winding L _aux , transformer auxiliary winding W _aux , integrating circuit and synchronous rectification driving circuit;

The synchronous rectification drive circuit includes: a drive generation circuit for the synchronous rectification MOS transistor S1 and _a drive generation circuit for the synchronous rectification MOS transistor S2 _;

Among them, the positive pole of the DC input voltage V _in is connected to the drain of the switch Q1 _; the source of the switch Q1 is connected to _one end of the resonant capacitor Cr _; the other end of the resonant capacitor Cr is connected to the same-named end of the resonant inductor L _{r ;} The synonymous end of _r is connected to the synonymous end of the main transformer T1 _; the synonymous end _of the main transformer T1 is connected to the source of the switch tube _Q2 and the negative pole of the input power V _in ; the _{synonymous end of the secondary winding W s1 of} the transformer T1 Connect to the drain of the synchronous rectifier MOS transistor S1 _; the same name terminal _of the secondary winding W _s2 of the transformer T1 is connected to the drain of the synchronous rectifier MOS transistor S2 _; the different name terminal of the secondary winding W _s2 is connected to the same name terminal of W _s1 and the output capacitor The positive pole of C _o is connected to one end of the load; the negative pole of the output capacitor C _o is connected to the other end of the load and the source of the synchronous rectifier tubes S ₁ and S ₂ ;

The same name terminal of the auxiliary winding L _aux of the resonant inductor L _r is connected to the same name terminal of the auxiliary winding W _aux of the transformer T1 _; the different name terminal of L _aux is connected to the input terminal of the integrating circuit, and the output of the integrating circuit is connected to the input of the synchronous rectification driving circuit; synchronous rectification The driving circuit generates the driving signal V _{gs_SR1} of the synchronous rectifier transistor S ₁ and the driving signal V _{gs_SR2} of S ₂ .

Preferably, the load is a post-stage circuit.

Preferably, the integrating circuit includes an operational amplifier OP, an input resistor R ₁ , a feedback resistor R ₂ and a feedback capacitor C ₁ . in:

_One end of the input resistor R1 is connected to the output end of the synthetic voltage source, the other end of the input resistor R1 is connected to the negative input end of the operational amplifier OP, _one end of the feedback resistor _R2 and one end of the feedback capacitor _C1 , and the other end of the operational amplifier OP The positive input terminal is connected to the secondary side ground GND _- S, the output terminal of the operational amplifier OP is connected to the other end of the feedback resistor R2 and the other end of the feedback capacitor _C1 , and the output terminal of the operational amplifier OP outputs a voltage signal v _iSR .

Preferably, the integrating circuit includes: a resistor R ₁ and a capacitor C ₁ ; one end of the resistor R ₁ is connected to the output end of the synthesized voltage source; the other end of the resistor R ₁ is connected to one end of the capacitor C ₁ ; the other end of the capacitor C ₁ is connected to The secondary side ground GND-S; between the resistor R ₁ and the capacitor C ₁ is the output voltage signal v _iSR of the integrating circuit.

Preferably, the synchronous rectification drive circuit includes _: a drive generation circuit of the synchronous rectification MOS transistor S1 and _a drive generation circuit of the synchronous rectification MOS transistor S2.

Preferably, the driving and generating circuit of the synchronous rectification MOS transistor S1 includes: a comparator ₁ , a comparator 2, an RS flip-flop 1, a driving circuit 1; the positive input terminal of the comparator 1 is connected to the operational amplifier OP of the integrating circuit 501 The output terminal of the comparator 1 and the negative input terminal of the comparator 2; the negative input terminal of the comparator 1 is connected to the voltage source V _{th_SR1} ; the positive input terminal of the comparator 2 is grounded; the output terminal of the comparator 1 is connected to the SET terminal of the RS flip-flop 1; The output terminal of the device 2 is connected to the RESET terminal of the RS flip-flop 1; the output Q terminal of the RS flip-flop 1 is connected to the input terminal of the driving circuit 1; the output terminal of the driving circuit ₁ is connected to the gate of the synchronous rectification MOS transistor S1.

Preferably, the driving and generating circuit of the synchronous rectification MOS transistor S1 includes: a comparator ₁ , a comparator 2, an RS flip-flop 1, and a driving circuit 1; the positive input terminal of the comparator 1 is connected to the negative voltage source V _{th_on} , and the The negative input terminal of the comparator ₁ is connected to the drain of the synchronous rectification MOS transistor S1; the output terminal of the operational amplifier OP of the integrating circuit 501 is connected to the negative input terminal of the comparator 2, and the positive input terminal of the comparator 2 is grounded; the output terminal of the comparator 1 is connected to the ground; The terminal is connected to the SET terminal of the RS flip-flop 1; the RESET terminal of the RS flip-flop 1 is connected to the output terminal of the comparator 2; the output Q terminal of the RS flip-flop 1 is connected to the input terminal of the driving circuit 1; the output terminal of the driving circuit 1 is connected to the synchronous rectification terminal _The gate of MOS tube S1.

Preferably, the driving and generating circuit of the synchronous rectification MOS transistor S ₂ includes: a comparator 3 , a comparator 4 , an RS flip-flop 2 , and a driving circuit 2 . The negative input terminal of the comparator 3 is connected to the output terminal of the operational amplifier OP of the integrating circuit 501 and the positive input terminal of the comparator 4; the positive input terminal of the comparator 3 is connected to the voltage source V _{th_SR2} ; the output terminal of the comparator 3 is connected to the RS trigger The SET terminal of the comparator 2; the RESET terminal of the RS flip-flop 2 is connected to the output of the comparator 4; the negative input terminal of the comparator 4 is grounded; the output terminal Q of the RS flip-flop 2 is connected to the input terminal of the driving circuit 2; the output of the driving circuit 2 Connect to the gate of the synchronous rectifier MOS tube _S2 .

Preferably, the driving and generating circuit of the synchronous rectification MOS transistor S ₂ includes: a comparator 3 , a comparator 4 , an RS flip-flop 2 , and a driving circuit 2 . The positive input terminal of the comparator 3 is connected to the negative voltage source V _{th_on} , the negative input terminal of the comparator 3 is connected to the drain of the synchronous rectification MOS transistor S ₂ ; the output terminal of the operational amplifier OP of the integrating circuit 501 is connected to the positive input terminal of the comparator 4 , the negative input terminal of the comparator 4 is grounded; the output terminal of the comparator 3 is connected to the SET terminal of the RS flip-flop 2; the RESET terminal of the RS flip-flop 2 is connected to the output of the comparator 4; the output terminal Q of the RS flip-flop 2 is connected to the driving circuit The input end of 2; the output of the drive circuit 2 is connected to the gate of the synchronous rectification MOS transistor S2.

Preferably, the LLC synchronous rectification control circuit based on secondary current simulation can be used in LLC resonant converters, LC resonant converters or LCC resonant converters.

The substantial advantage of the present invention is that: the LLC synchronous rectifier circuit based on secondary current simulation proposed by the present invention can effectively solve the problem of loss of duty ratio of the driving signal of the secondary side synchronous rectifier tube caused by parasitic inductance, and can achieve high precision The synchronous rectification of the drive signal improves the efficiency of the LLC. It has the characteristics of simple structure, low circuit cost and high reliability.

Description of drawings

Figure 1 shows a schematic block diagram of detecting the voltage across the DS of the synchronous rectifier MOS tube to generate its driving signal;

Figure 2 shows the ideal waveform of the drive signal generated by detecting the voltage across the synchronous rectifier MOS transistor DS;

Figure 3 shows a model of a synchronous rectifier MOS tube with parasitic inductance;

Fig. 4 shows the principle block diagram of the LLC synchronous rectification control circuit based on secondary current simulation of the present invention;

FIG. 5 shows the first specific embodiment of the LLC synchronous rectification control circuit based on secondary current simulation of the present invention;

Fig. 6 shows the second specific embodiment of the LLC synchronous rectification control circuit based on secondary current simulation of the present invention;

FIG. 7 shows the third specific embodiment of the LLC synchronous rectification control circuit based on secondary current simulation of the present invention;

Figure 8 shows the comparison between the actual waveform and the ideal waveform of the drive signal generated by detecting the voltage across the synchronous rectifier MOS transistor DS;

In the figure: 400, synthetic voltage source, 401, integrating circuit, 402, synchronous rectification drive circuit, 4021, drive generation circuit _of synchronous rectification MOS transistor SR1, ₄₀₂₂ , drive generation circuit of synchronous rectification MOS transistor SR2.

Detailed ways

In order to make the technical solutions and advantages of the present invention clearer, the details of the present invention are further elaborated below with reference to the accompanying drawings, and those skilled in the art can fully understand the present invention without the description of these details.

FIG. 4 shows the principle block diagram of the LLC synchronous rectification control circuit based on secondary current simulation proposed by the present invention. For ease of understanding, the figure also shows the electrical connection between the synchronous rectification circuit control circuit and the LLC resonant converter main circuit .

Referring to FIG. 4 , the synchronous rectification control circuit includes: an auxiliary winding L _aux of the resonant inductor L _r , an auxiliary winding W _aux of the transformer T ₁ , an integrating circuit 401 and a synchronous rectification driving circuit 402 ;

The auxiliary winding L _aux of the resonant inductor L _r is connected in series with the auxiliary winding W _aux of the transformer T ₁ to form a combined voltage source 400 , wherein the auxiliary winding L _aux of the resonant inductor L _r is terminated with the same name as the auxiliary winding of the transformer T ₁ . The same-named end of the winding W _aux , one end of the synthetic voltage source 400 is connected to the secondary side ground GND-S, the other end of the synthetic voltage source 400 is connected to the input end of the integrating circuit 401, and the output end of the integrating circuit 401 is connected to the At the input end of the synchronous rectification driving circuit 402, the synchronous rectification driving circuit 402 generates the driving signals v _{gs_SR1} and v _{gs_SR2} of the synchronous rectification MOS transistors.

The LLC resonant converter main circuit includes a DC input voltage V _in , two main power transistors Q ₁ and Q ₂ constituting a half-bridge circuit, a resonant capacitor C _r , a resonant inductor L _r , a transformer T ₁ , and a secondary side synchronous rectifier Tubes SR ₁ and SR ₂ , as well as the output capacitor C _o and the load. Among them, the end of the same name of the primary side winding of the resonant inductor L _r is connected to the end of the same name of the primary side winding of the transformer T ₁ .

The principle of the present invention is briefly described below

The resonant inductor L _r auxiliary winding L _aux voltage v _Lr is expressed as follows:

Where L _r is the resonant inductance, n _Lr is the turns ratio of the primary side winding of the resonant inductance L _r with respect to the auxiliary winding L _aux , and i _Lr is the resonant current.

The transformer T ₁ auxiliary winding W _aux voltage v _aux is expressed as follows:

Among them, L _m is the primary side excitation inductance of the transformer, n _T is the turns ratio of the primary side winding of the transformer T ₁ relative to the auxiliary winding W _aux , and i _Lm is the excitation current.

Referring to FIG. 4, the output voltage v1 _of the combined voltage source 400 is represented as follows:

v ₁ = -(v _Lr -v _aux ) (3)

From the basic LLC working principle, the following current relationship can be obtained:

i _Lr -i _Lm = i _SR /n _T (4)

Among them, i _SR is the sum of the rectified current of the secondary side synchronous rectification MOS tube.

Simultaneous equations (1) to (3), the output signal v _iSR of the integrating circuit 401 can be expressed as follows:

The designed circuit parameters satisfy L _r /n _Lr =L _m /n _T , combined with equation (4), equation (5) can be simplified as follows:

where k=L _r /(n _{Lrn T} ), is the proportional coefficient between the absolute value of the output signal v _iSR of the integrating circuit 401 and the synchronous rectification current i _SR .

It can be seen from equation (6) that the absolute value of the output signal v _iSR of the integrating circuit 401 is proportional to the synchronous rectification current i _SR , that is, the rectified signal waveform of the output signal v _iSR and the synchronous rectification current i _SR form a proportional relationship , the waveform of v _iSR is consistent with the zero-crossing point of the waveform of i _SR . Therefore, the driving signal of the synchronous rectification MOS can be generated by detecting v _iSR . Compared with the traditional synchronous rectification scheme, which detects the voltage across the DS of the synchronous rectification MOS tube to generate the driving signal of the synchronous rectification MOS tube, this scheme, especially the turn-off signal of the synchronous rectification MOS tube, is no longer affected by the parasitic inductance.

FIG. 5 shows the first specific embodiment of the LLC synchronous rectification control circuit based on secondary current simulation of the present invention, and specifically, shows a specific implementation of the integrating circuit 401 and the synchronous rectification driving circuit 402 . Also for ease of understanding, FIG. 5 also shows the electrical connection between the control circuit of the synchronous rectification circuit and the main circuit of the LLC resonant converter.

Referring to Fig. 5, the different name _of the auxiliary winding W _aux of the transformer T1 is connected to the secondary side ground GND-S, the same name is connected to the same name end of the auxiliary winding L _aux of the resonant inductor L _r , and the auxiliary winding L _aux of the resonant inductor L _r is connected with the same name. The synonym terminal outputs the output signal v ₁ of the synthesized voltage source 400 .

The integrating circuit 401 includes an operational amplifier OP, an input resistor R ₁ of the operational amplifier OP, a feedback resistor R ₂ and a feedback capacitor C ₁ of the operational amplifier OP. _One end of the input resistor R1 of the operational amplifier OP is connected to the synonymous end of the auxiliary winding L _aux of the resonant inductor _{Lr ;} the other end of R1 is connected to the negative input end of the operational amplifier OP, _one end of the feedback resistor R2 and _one end of the feedback capacitor C1; The positive input terminal of the operational amplifier OP is connected to the secondary side ground GND-S; the output terminal of the operational amplifier OP is connected to the other end of the feedback resistor R ₂ and the other end of the feedback capacitor C ₁ . The integrating circuit 401 module integrates the output voltage signal v ₁ of the combined voltage source 400 to output a signal v _iSR .

The frequency domain relationship between the output v _iSR of the integrating circuit 401 and the secondary side synchronous rectification current i _SR is expressed as follows:

Wherein, f _L =1/2πR ₂ C ₁ is the low frequency corner frequency of the integrating circuit 401 . When the operating frequency f _s >> f _L , the time domain relationship between v _iSR and i _SR can be simplified as follows:

Wherein, K=L _r /(R ₁ C ₁ n _{Lrn T} ). Comparing formulas (8) and (6), it can be seen that the specific embodiment of the integrating circuit 401 shown in FIG. 5 can realize the required functions of the integrating circuit 401 .

_The synchronous rectification drive circuit 402 includes _a drive generation circuit 4021 of the synchronous rectification MOS transistor SR1 and a drive generation circuit 4022 of the synchronous rectification MOS transistor SR2. in,

The drive generation circuit 4021 of the synchronous rectification MOS transistor SR1 includes a comparator ₁ , a comparator 2 , an RS flip-flop 1 , and a drive circuit 1 . The positive input terminal of the comparator 1 is connected to the output terminal of the operational amplifier OP of the integrating circuit 401 and the negative input terminal of the comparator 2; the negative input terminal of the comparator 1 is connected to a small positive voltage source V _{th_SR1} , and the comparator 2 The positive input terminal of the 1 is connected to the secondary side ground GND-S, the output terminal of the comparator 1 is connected to the SET terminal of the RS flip-flop 1; the RESET terminal of the RS flip-flop 1 is connected to the output terminal of the comparator 2; the output Q of the RS flip-flop 1 The terminal is connected to the input terminal of the driving circuit 1; the output terminal of the driving circuit ₁ is connected to the gate of the synchronous rectification MOS transistor SR1.

The specific working process _of the drive generation circuit 4021 of the synchronous rectification MOS transistor SR1 is as follows: when the output signal v _iSR of the integrating circuit 401 is higher than V _{th_SR1} , the comparator 1 outputs a high level, so that the output terminal Q of the RS flip-flop 1 is set to a high level level, the drive signal v _{gs_SR1} of the synchronous rectifier tube S1 is _turned from a low level to a high level. When the output signal v _iSR of the integrating circuit 401 decreases and crosses zero, the comparator 2 outputs a high level so that the output terminal Q of the RS flip-flop ₁ is reset to a low level, and the drive signal v _{gs_SR1} of the synchronous rectifier MOS transistor S1 changes from a low level to a low level. Flip to high level.

The drive generation circuit 4022 of the synchronous rectification MOS transistor SR2 includes a comparator ₃ , a comparator 4 , an RS flip-flop 2 , and a drive circuit 2 . The negative input terminal of the comparator 3 is connected to the output terminal of the operational amplifier OP of the integrating circuit 501 and the positive input terminal of the comparator 4; the positive input terminal of the comparator 3 is connected to a small negative voltage voltage source V _{th_SR2} , the comparator The negative input terminal of 4 is connected to the secondary side ground GND-S; the output terminal of the comparator 3 is connected to the SET terminal of the RS flip-flop 2; the RESET terminal of the RS flip-flop 2 is connected to the output of the comparator 4; the output terminal of the RS flip-flop 2 Q is connected to the input end of the drive circuit 2; the output of the drive circuit ₂ is connected to the gate of the synchronous rectification MOS transistor SR2.

_The specific working process of the drive generation circuit 4022 of the synchronous rectification MOS transistor SR2 is as follows: when the output signal v _iSR of the integrating circuit 401 is smaller than V _{th_SR2} , the comparator 3 outputs a high level to set the output terminal Q of the RS flip-flop 2 to a high level level, the drive signal v _{gs_SR2} of the synchronous rectifier tube S ₂ is turned from a low level to a high level. When the output signal v _iSR of 401 increases and crosses zero, the comparator 4 outputs a high level so that the output terminal Q of the RS flip-flop 2 is reset to a low level, and the driving signal v _{gs_SR2} of the synchronous rectifier MOS transistor SR ₂ becomes a high level Flat flips low.

FIG. 6 shows a second specific embodiment of the LLC synchronous rectification control circuit based on secondary current simulation of the present invention. Compared with the first specific embodiment shown in FIG. 5 , the difference of the second specific embodiment shown in FIG. 6 lies in the implementation of the synchronous rectification driving circuit 402 .

Referring to FIG. ₆ , the synchronous rectification drive circuit 402 includes _a drive generation circuit 4021 of the synchronous rectification MOS transistor SR1 and a drive generation circuit 4022 of the synchronous rectification MOS transistor SR2. in,

The driving and generating circuit of the synchronous rectification MOS transistor SR1 includes: a comparator ₁ , a comparator 2, an RS flip-flop 1, a driving circuit 1; the positive input terminal of the comparator 1 is connected to the negative voltage source V _{th_on} , and the The negative input terminal is connected to the drain of the synchronous rectification MOS transistor SR1 _; the output terminal of the operational amplifier OP of the integrating circuit 501 is connected to the negative input terminal of the comparator 2, and the positive input terminal of the comparator 2 is connected to the secondary side ground GND-S; The output terminal of the device 1 is connected to the SET terminal of the RS flip-flop 1; the RESET terminal of the RS flip-flop 1 is connected to the output terminal of the comparator 2; the output Q terminal of the RS flip-flop 1 is connected to the input terminal of the driving circuit 1; the output terminal of the driving circuit 1 Terminate the gate _of the synchronous rectifier MOS transistor SR1.

The specific working process _of the drive generation circuit 4021 of the synchronous rectification MOS transistor SR1 is as follows: when the drain voltage of the synchronous rectification MOS transistor SR1 is lower than V _{th_on} , the comparator ₁ outputs a high level so that the output terminal Q of the RS flip-flop 1 is set When it becomes a high level, the drive signal v _{gs_SR1} of the synchronous rectifier tube S1 is _turned from a low level to a high level. When the output signal v _iSR of the integrating circuit 401 decreases and crosses zero, the comparator 2 outputs a high level so that the output terminal Q of the RS flip-flop ₁ is reset to a low level, and the drive signal v _{gs_SR1} of the synchronous rectifier MOS transistor S1 changes from a low level to a low level. Flip to high level.

_The drive generation circuit 4022 of the synchronous rectification MOS transistor SR2 includes: a comparator 3 , a comparator 4 , an RS flip-flop 2 , and a drive circuit 2 . The positive input terminal of the comparator 3 is connected to the negative voltage source V _{th_on} , the negative input terminal of the comparator 3 is connected to the drain of the synchronous rectification MOS transistor SR ₂ ; the output terminal of the operational amplifier OP of the integrating circuit 401 is connected to the positive input terminal of the comparator 4 , the negative input terminal of the comparator 4 is connected to the secondary side ground GND-S; the output terminal of the comparator 3 is connected to the SET terminal of the RS flip-flop 2; the RESET terminal of the RS flip-flop 2 is connected to the output of the comparator 4; the RS flip-flop 2 The output Q is connected to the input of the drive circuit 2; the output of the drive circuit ₂ is connected to the gate of the synchronous rectification MOS transistor SR2.

_The specific working process of the drive generation circuit 4022 of the synchronous rectification MOS transistor SR2 is as follows: when the drain voltage of the synchronous rectification MOS transistor SR2 is lower _than V _{th_on} , the comparator 3 outputs a high level to set the output terminal Q of the RS flip-flop 2 When it becomes a high level, the driving signal v _{gs_SR2} of the synchronous rectifier _SR2 is turned from a low level to a high level. When the output signal v _iSR of the integrator 401 increases and crosses zero, the comparator 4 outputs a high level so that the output terminal Q of the RS flip-flop 2 is reset to a low level, and the driving signal v _{gs_SR2} of the synchronous rectifier MOS transistor SR ₂ changes from a high level to a high level. Flat flips low.

FIG. 7 shows a third specific embodiment of the LLC synchronous rectification scheme based on secondary current simulation of the present invention. Specifically, this embodiment shows another simpler implementation of the integrating circuit 401 . Among them, the auxiliary winding L _aux of the resonant inductor L _r is terminated to the secondary side ground GND-S, the same name is terminated to the same name terminal of the auxiliary winding W _aux of the transformer T ₁ , and the other name terminal of the auxiliary winding W _aux of the transformer T ₁ is used as a synthetic voltage source. The output of 400 outputs the signal v ₁ . The integrating circuit 401 includes a resistor R _a1 and a capacitor C _a1 . _One end of the resistor Ra1 is connected to the other end of the transformer auxiliary winding W _aux , the other end of the resistor _Ra1 is connected to one end of the capacitor C _a1 and outputs a signal v _iSR , and the other end of the capacitor C ₁ is connected to the secondary side ground GND-S.

_The time domain representation of the output signal v1 of the synthesized voltage source 400 of the integrating circuit 401 is as follows:

If the design parameters satisfy R _a1 >>1/(2πf _s C ₁ ), the time domain relationship between the output voltage v _iSR and i _SR of the capacitor C _a1 can be simplified as follows;

Wherein K=L _r /(R _a1 C _a1 n _{Lrn T} ) is the proportional coefficient between the output signal v _iSR of the integrating circuit 401 and the synchronous rectification current i _SR . This relationship is the same as equation (10), so the driving signal of the synchronous rectifiers S _R1 and S _R2 can be generated by detecting v _iSR instead of i _SR , and this signal is not affected by parasitic inductance.

Further, the implementation of the synchronous rectification driving circuit 402 in the second specific embodiment of the present invention shown in FIG. 6 can be used to replace the synchronous rectification driving circuit 402 in the third specific embodiment of the present invention shown in FIG. 7 to form a new Examples are not described in detail here.

Further, the implementation of the synthetic voltage source 400 shown in the first specific embodiment of the present invention shown in FIG. 5 and the second specific embodiment of the present invention shown in FIG. 6 may be the same as the third embodiment of the present invention shown in FIG. 7 . Embodiments The implementations of the synthetic voltage source 400 are replaced with each other, and the corresponding implementations of the synchronous rectification driving circuit 402 are adjusted to a certain extent, so as to form a new example, which will not be described in detail here.

The claims of the present invention are mainly used to define and protect the main contents and ideas proposed by the present invention. For the circuit structure proposed by the present invention, the present invention covers any substitutions, modifications, equivalent methods and solutions made within the spirit and scope of the present invention. The embodiments selected and specifically described in this specification are to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and make modifications on the basis of the present invention. The foregoing detailed descriptions of embodiments of the present invention are not intended to be exhaustive or to limit the invention to the precise forms described above. The details of the above-mentioned circuit structure and its control method can be changed accordingly in the actual implementation process, but they are still included in the present invention.

As noted above, it should be noted that specific terms used in describing certain features or aspects of the invention should not be used to imply that the terms are redefined herein to limit certain features, characteristics or aspects of the invention to which the terms are associated. Program. In sum, the terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the invention is intended not only to include the disclosed embodiments, but also to be encompassed by the claims.

Claims (7)

1. The utility model provides a LLC synchronous rectification circuit based on secondary current simulation which characterized in that includes: a power circuit and a control section;

the power circuit includes: DC input voltage V_inTwo main power transistors Q of a half-bridge circuit₁And Q₂Resonant capacitor C_rResonant inductance L_rLLC main transformer T₁Secondary side synchronous rectifier tube S₁And S₂And an output capacitor C_oAnd a load;

the control section includes: resonant inductor auxiliary winding L_auxAuxiliary winding W of transformer_auxAn integrating circuit and a synchronous rectification drive circuit;

the synchronous rectification drive circuit comprises: synchronous rectification MOS tube S₁Drive generation circuit and synchronous rectification MOS tube S₂The drive generation circuit of (1);

wherein the DC input voltage V_inThe positive pole is connected with a switching tube Q₁A drain electrode; switch tube Q₁Source electrode of the capacitor is connected with a resonance capacitor C_rOne end of (a); resonant capacitor C_rThe other end of the resonant inductor L is connected with_rThe same name end of (1); resonant inductor L_rThe different name end of T is connected with the main transformer₁The same name end of (1); main transformer T₁Different name end connected switch tube Q₂Source and input power supply V_inThe negative electrode of (1); transformer T₁Secondary winding W_s1Different name end-connected synchronous rectification MOS tube S₁A drain electrode of (1); transformer T₁Secondary winding W_s2Is connected with a synchronous rectification MOS tube S₂A drain electrode of (1); secondary winding W_s2Different name ends W_s1End of same name and output capacitor C_oThe positive electrode and the load end of (1); output capacitor C_oNegative pole of the rectifier is connected with the other end of the load and the synchronous rectifier tube S₁、S₂A source electrode of (a);

resonant inductor L_rOf the auxiliary winding L_auxEnd-connected transformer T of the same name₁Auxiliary winding W of_auxA homonymous terminal;

L_auxthe synonym end of the integrating circuit is connected with the input end of the integrating circuit, and the output end of the integrating circuit is connected with the input end of the synchronous rectification drive circuit; synchronous rectification driving circuit for generating synchronous rectification tube S₁Drive signal V of_{gs_SR1}And S₂Drive signal V of_{gs_SR2}。

2. The LLC synchronous rectification circuit based on secondary current simulation of claim 1, wherein said load is a post-stage circuit.

3. The LLC synchronous rectification circuit based on secondary current simulation of claim 1, wherein the integration circuit comprises an operational amplifier OP, an input resistor R of the operational amplifier OP₁Feedback resistor R of operational amplifier OP₂And a feedback capacitor C₁；

OP input resistor R of operational amplifier₁One end of is connected with a resonant inductor L_rAuxiliary winding L_auxA synonym terminal; r₁The other end of the operational amplifier is connected with the negative input end of the operational amplifier OP and the feedback resistor R₂And a feedback capacitor C₁One end of (a); the positive input end of the operational amplifier OP is connected with the secondary side ground GND-S; the output end of the operational amplifier OP is connected with a feedback resistor R₂Another terminal of (1), feedback capacitance C₁And the other end of the synchronous rectification MOS tube S₁Drive generation circuit of (1) and synchronous rectification MOS tube S₂The input terminal of the drive generation circuit is electrically connected.

4. The LLC synchronous rectification circuit based on secondary current simulation of claim 1, wherein the integration circuit comprises: resistance R₁And a capacitor C₁(ii) a Resistance R₁One end is connected with the auxiliary winding W of the transformer_auxA synonym terminal; resistance R₁The other end is connected with a capacitor C₁One end of (a); capacitor C₁The other end is connected with a secondary side ground GND-S; resistance R₁And a capacitor C₁Between the output voltage v of the integrating circuit_iSR。

5. The LLC synchronous rectification circuit based on secondary current simulation of claim 1, wherein the integration circuit comprises:

operational amplifiers OP1, OP2 and OP3, operational amplifier OP1 input resistor R₁Feedback resistance R₂Feedback capacitance C₁Input resistor R of operational amplifier OP2₃Feedback resistance R₄Feedback capacitance C₂Input resistance R of operational amplifier OP3₅And R₇Feedback resistance R₈Divider resistor R₆The operational amplifiers OP1 and OP2 form an integrator form, and the operational amplifier OP3 forms a differential operational amplifier form;

wherein the positive input terminal of the operational amplifier OP1 is grounded; the negative input end of the operational amplifier OP1 is connected with a resistor R₁The other end, a feedback capacitor C₁One terminal and a feedback resistor R₂One end; the output end of the operational amplifier OP1 is connected with a feedback resistor R₂The other end, a feedback capacitor C₁The other end and R₇One end; the positive input end of the operational amplifier OP2 is grounded; the negative input end of the operational amplifier OP2 is connected with the input resistor R₃Another terminal, feedback resistor R₄One terminal and a feedback capacitor C₂One end; the output end of the operational amplifier OP2 is connected with a feedback resistor R₄The other end, a feedback capacitor C₂The other end and a resistor R₅One end; the negative input end of the operational amplifier OP3 is connected with the input resistor R₇The other end and a feedback resistor R₈One end; the positive input end of the operational amplifier OP3 is connected with the input resistor R₅The other end and a divider resistor R₆One end; voltage dividing resistor R₆The other end is grounded; the output end of the operational amplifier OP3 is connected with a feedback resistor R₈The other end and a synchronous rectification MOS tube S₁Drive generation circuit of (1) and synchronous rectification MOS tube S₂The input terminal of the drive generation circuit is electrically connected.

6. The LLC synchronous rectification circuit based on secondary current simulation of claim 3, 4 or 5, wherein said synchronous rectification MOS transistor S₁The drive generation circuit of (1), comprising: the circuit comprises a comparator 1, a comparator 2, an SR trigger 1 and a driving circuit 1; the positive input end of the comparator 1 is connected with the output end of the operational amplifier OP of the integrating circuit 501 and the negative input end of the comparator 2; the negative input end of the comparator 1 is connected with a voltage source; the output end of the comparator 1 is connected with the SET end of the SR trigger 1; the RESST of the SR trigger 1 is connected with the output end of the comparator 2; the negative input end of the comparator 2 is grounded; the output Q end of the SR trigger 1 is connected with the input end of the driving circuit 1; the output end of the drive circuit 1 is connected with a synchronous rectification MOS tube S₁A gate electrode of (2).

7. The LLC synchronous rectification circuit based on secondary current simulation of claim 3, 4 or 5, wherein said synchronous rectification MOS transistor S₂The drive generation circuit of (1), comprising:

a comparator 3, a comparator 4, an SR flip-flop 2, a driving circuit 2; wherein the negative input terminal of the comparator 3 is connected to the output terminal of the operational amplifier OP of the integrating circuit 501 and the positive input terminal of the comparator 4; the positive input end of the comparator 3 is connected with a voltage source; the output end of the comparator 3 is connected with the SET end of the SR trigger 2; the RESET end of the SR trigger 2 is connected with the output of the comparator 4; the negative input terminal of the comparator 4 is grounded; the output end Q of the SR trigger 2 is connected with the input end of the driving circuit 2; the output of the driving circuit 2 is connected with the gate of the synchronous rectification MOS tube S2.

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