CN113675266A

CN113675266A - Negative capacitance L-type gate tunneling field effect transistor and preparation method thereof

Info

Publication number: CN113675266A
Application number: CN202110845266.6A
Authority: CN
Inventors: 陈树鹏; 张�浩; 刘红侠; 王树龙
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2021-07-26
Filing date: 2021-07-26
Publication date: 2021-11-19

Abstract

The invention belongs to the technical field of microelectronic devices, and discloses a negative capacitance L-type gate tunneling field effect transistor and a preparation method thereof. Including: buried oxide layer, P ^- substrate, N ⁺ type interlayer, P ⁺ type source region, gate oxide dielectric, ferrodielectric layer, gate and drain regions, P ⁺ type source region and N ⁺ type interlayer from top to bottom The bottom is located on the upper left of the P ^- substrate, the gate oxide dielectric is located on the right side of the N ⁺ type interlayer, the gate region is located on the top of the gate oxide layer, the drain region is located on the right side of the P ^- substrate, and the buried oxide layer is located on the P ^- Sink Below the bottom, a stacked structure of metal //Hf _0.5 Zr _0.5 O/HfO ₂ /Si is formed on the left side of the P ⁺ source region to increase the gate control capability, thereby increasing the surface potential of the channel and improving the tunneling field effect transistor TFET The on-state current of ; generates an N ⁺ interlayer and P ⁺ source region on the left side of the gate region, increasing the tunneling area, in order to form line tunneling.

Description

Negative capacitance L-shaped gate tunneling field effect transistor and preparation method thereof

Technical Field

The invention relates to the technical field of microelectronic devices, in particular to a negative-capacitance L-shaped gate tunneling field effect transistor and a preparation method thereof, which can be used for preparing electronic devices with large on-state current and low power consumption.

Background

In the process of miniaturization of complementary MOS technology, adjusting the supply voltage is the most effective way to reduce power consumption. However, it is no longer feasible to employ this approach in nanoscale circuits. The low threshold voltage can cause the leakage current of the device to increase sharply, further increasing the static power consumption of the device. As a breakthrough, the tunneling field effect transistor TFET with gate controlled reverse biased p-i-n diode structure is one of the candidates for next generation low power devices due to its lower leakage current and steep sub-threshold slope. To achieve ultra-low power operation, tunneling field effect transistors TFETs with steep sub-threshold swings have been widely studied. At present, some gate/channel/source overlapping structures are proposed, which increase the on-state current and improve the sub-threshold characteristics by increasing the effective tunneling area; others using, for example, Si/Ge_xSi₁-x to form a shorter tunneling path to achieve a steeper sub-threshold swing SS and a larger on-current. The above methods all change the sub-threshold swing SS based on the inter-band tunneling mechanism to obtain better sub-threshold characteristics.

However, limited by the innovation of the device structure and the diversity of heterogeneous materials, the improvement of the device characteristics is limited, and the tunneling probability of the traditional L-channel tunneling field effect transistor LG-TFET is difficult to increase. For this reason, ferroelectric materials are introduced into the device as a gate stack to increase the channel surface potential, thereby increasing the tunneling probability of the device, in order to expect a larger on-state current and a steeper subthreshold slope.

Disclosure of Invention

Aiming at the problems in the prior art, the invention aims to provide a negative-capacitance L-type gate tunneling field effect transistor and a preparation method thereof, so as to reduce off-state current and sub-threshold swing amplitude SS, and further improve the switching performance of a digital circuit by increasing tunneling probability and on-state current.

In order to achieve the purpose, the invention is realized by adopting the following technical scheme.

A negative capacitance L-type gate tunneling field effect transistor comprises: p^-Substrate, P⁺Source region, gate region and drain region of the type, wherein P^-An oxygen buried layer, P, is disposed under the substrate^-The left upper part of the substrate is deposited with N⁺Type interlayer, P^-The right side of the substrate is etched with a lower step, the drain region is positioned at the upper part of the lower step, and the thickness and the P of the drain region are equal^-The substrates are the same;

N⁺the upper part of the upper step is deposited with P⁺Source region of type, P^-A gate oxide layer medium is deposited on the right upper part of the substrate, a gate region is arranged on the upper part of the gate oxide layer medium, and an HfZrO ferroelectric medium layer is arranged between the gate oxide layer medium and the gate region to enhance the L-type tunneling field effect transistor P⁺Right side N of source region⁺The electric potential at the interlayer increases the tunneling probability of the electron band.

Further, said P⁺The height of the source region is 40 +/-1 nm, the length is 65 +/-1 nm, and the doping concentration is 10²⁰/cm³；

Said N is⁺The height of the interlayer is 40 + -1 nm, the length is 5 + -0.5 nm, and the doping concentration is 5 × 10¹⁸/cm³；

The drain region is N⁺A drain region with a height of 20 + -1 nm, a length of 65 + -1 nm and a doping concentration of 10¹⁸/cm³。

Further, said P⁺Source region of the pattern, N⁺Type interlayer, N⁺And the type drain regions are respectively prepared from silicon materials.

Further, said N⁺The drain region is formed by the gate electrode in P^-The right portion of the patterned substrate had an implant energy of 10 + -0.5 Kev and a dose of 1X 10¹⁸/cm³Ar element (b) of (1).

Furthermore, the shape of the gate oxide layer medium is L-shaped and adopts HfO₂The thickness of the material is 2 +/-0.2 nm.

Further, the height of the gate region is 68 +/-1 nm, and the length of the gate region is 45 +/-2 nm.

Further, the HfZrO ferroelectric medium layer is made of Hf_0.5Zr_0.5O, the thickness is 3 +/-0.2 nm.

(II) a preparation method of a negative capacitance L-shaped gate tunneling field effect transistor, which comprises the following steps:

1) growing a layer of 45 +/-1 nm thick, 182 +/-1 nm long and 1X 10 doping concentration on the substrate by adopting a vapor phase epitaxy process¹⁵/cm³P of^-A molding region;

2) at P^-Coating photoresist on the left side of the pattern region, and coating photoresist on P^-A first region with the height of 25 +/-1 nm and the length of 112 +/-1 nm is generated on the right side of the molding region by using a reactive ion etching process;

3) removing the photoresist at P^-The left side of the pattern region is grown by a vapor phase epitaxy process to form a layer with the height of 45 +/-1 nm, the length of 70 +/-1 nm and the doping concentration of 5 multiplied by 10¹⁸/cm³N of (A)⁺A mold sandwich;

4) at generation of N⁺The second area with the height of 40 +/-1 nm and the length of 65 +/-1 nm is generated in the type interlayer area by using a reactive ion etching process;

5) in the second region, a layer with height of 40 + -1 nm, length of 65 + -1 nm and doping concentration of 1 × 10 is grown by vapor phase epitaxy process²⁰/cm³P of⁺A source region;

6) at P⁺Depositing a layer of HfO with the thickness of 2 +/-0.2 nm by utilizing an atomic layer deposition process in the source region and the first region₂Thin films, i.e., gate oxide dielectrics;

7) depositing a layer of Hf with the thickness of 3 +/-0.2 nm on a gate oxide layer medium by adopting an atomic layer deposition process_0.5Zr_0.5A ferroelectric dielectric film of O;

8) removing the ferroelectric dielectric film in the horizontal direction by using a reactive ion etching process to obtain a vertical ferroelectric dielectric layer;

9) depositing a metal gate region with the thickness of 68nm on the right side of the vertical ferroelectric dielectric layer by utilizing an atomic layer deposition process;

10) removing the gate oxide layer media above the source region and the P-type substrate by using a reactive ion etching process to form an L-shaped HfO2 thin film structure;

11) at P^-The right portion of the patterned substrate had an implant energy of 10 + -0.5 Kev and a dose of 1X 10¹⁸/cm³Form N with a height of 20 + -1 nm and a length of 65 + -1 nm⁺A drain region;

12) at P⁺Over the source region, N⁺And respectively depositing a source electrode, a drain electrode and a grid electrode above the drain region and at the top of the grid region by adopting a chemical vapor deposition method, and finishing the manufacture of the device.

Further, in steps 1), 3) and 5), the process conditions of the vapor phase epitaxy process are as follows: the growth temperature is 780 ℃, and the reactant source gas is SiH₄The protective gas is He, and the pressure in the reaction chamber is 760 mT.

Further, in the steps 2), 4), 8) and 10), the process conditions of the reactive ion etching process are as follows: the reaction gas is Cl₂And O₂(ii) a The pressure in the reaction chamber was 10mT and the power was 20W.

Further, in step 6), the process conditions of the atomic layer deposition process are as follows: adopting a hafnium source as a precursor molecule; ozone is taken as a reactant, and nitrogen is taken as a carrier gas; the temperature of the reaction cavity is 250 ℃; the pressure of the hafnium source is 3X 10^-4Pa; the ozone pressure is 2 x 10^-1Pa。

Further, in step 7), the process conditions of the atomic layer deposition process are as follows: adopting hafnium and zirconium as precursor molecules; ozone is taken as a reactant, and nitrogen is taken as a carrier gas; the heating temperature of the reaction precursor is 75-80 ℃, and Hf: the molar ratio of Zr is 0.5; the temperature of the cavity is 250-280 ℃; the ozone pressure is 2 x 10^-1Pa。

Further, in step 9), the process conditions of the atomic layer deposition process are as follows: adopting a copper source as a precursor molecule; with H₂Argon is used as a carrier gas; the temperature of the reaction cavity is 250 ℃; the gas pressure of the copper source is 3 x 10^-4pa；H₂Air pressure of 2X 10^-1Pa。

Compared with the prior art, the invention has the beneficial effects that:

(1) the invention introduces the ferroelectric material HZO as the gate stack on the basis of the traditional LTFET, can greatly increase the surface potential of the device channel, and can greatly increase the surface potential of the device channel in N⁺The interlayer has a large band-to-band tunneling rate, and can obtain larger on-state current.

(2) Compared with the conventional heavily doped N⁺Interlayer, the invention adopts lightly doped N⁺The interlayer enables the device to keep a smaller sub-threshold slope on the basis of a large on-state current, and lower power consumption is achieved.

Drawings

The invention is described in further detail below with reference to the figures and specific embodiments.

FIG. 1 is a block diagram of a negative capacitance L-gate tunneling field effect transistor NC-LTFET of the present invention;

FIG. 2 is a schematic flow chart of the present invention for fabricating a negative capacitance L-gate tunneling field effect transistor NC-LTFET;

fig. 3 is a graph comparing transmission characteristics of a conventional LG-TFET and a negative-capacitance L-gate tunneling field effect transistor of the present invention.

In the above figures, 1, P^-A substrate; 2. n is a radical of⁺A mold sandwich; 3. p⁺A source region; 4. a gate oxide dielectric; 5. a ferroelectric dielectric layer; 6. a gate region; 7. a drain region; 8. and an oxygen burying layer.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention.

Referring to fig. 1, a negative capacitance L-gate tunneling field effect transistor according to the present invention includes: the P-type gate structure comprises a P-substrate 1, a P + type source region 3, a gate region 6 and a drain region 7, wherein an oxygen buried layer 8 is arranged below the P-substrate 1, an N + type interlayer 2 is deposited on the left upper part of the P-substrate 1, a lower step is etched on the right side of the P-substrate 1, and the drain region 7 is located on the upper part of the lower step and has the same thickness as the P-substrate 1;

an upper step is etched on the N + type interlayer 2, a P + type source region 3 is deposited on the upper portion of the upper step, a gate oxide layer medium 4 is deposited on the right upper portion of the P-substrate 1, a gate region 6 is arranged on the upper portion of the gate oxide layer medium 4, and an HfZrO ferroelectric medium layer 5 is arranged between the gate oxide layer medium 4 and the gate region 6 so as to enhance the electric potential of the N + type interlayer 2 on the right side of the P + type source region 3 of the L-type tunneling field effect transistor and increase the tunneling probability of an electron band.

In this embodiment, the N + type interlayer 2 has a height of 45 + -1 nm, a length of 5 + -0.5 nm, and a doping concentration of 5 × 10¹⁸/cm³Which is located at the upper left of the P-substrate 1;

the height of the P + type source region 3 is 40 +/-1 nm, the length is 65 +/-1 nm, and the doping concentration is 10²⁰/cm³Which is positioned at the upper left of the N + type interlayer 2;

the gate oxide layer medium 4 is made of high-K dielectric material (HfO) with the thickness of 2nm +/-0.2 nm₂) Which is positioned between the N + type interlayer 2 and the ferroelectric dielectric layer 5;

the thickness of the ferroelectric medium layer 5 is 3 +/-0.2 nm, and the ferroelectric medium layer is positioned between the gate oxide layer medium 4 and the gate region 6;

N⁺the height of the drain region 7 is 20 +/-1 nm, the length is 65 +/-1 nm, and the doping concentration is 10¹⁸/cm³Which is located on the right part of the P-substrate 1.

Referring to fig. 2, the steps of manufacturing the negative capacitance L-type gate tunneling field effect transistor of the present invention are as follows:

step 1, selecting SiO₂And oxidizing the layer and epitaxially growing a P-type silicon layer above the oxide layer.

1a) Putting the silicon dioxide layer into molecular beam epitaxial film growth equipment, opening a gas cylinder, introducing protective gas He gas into the equipment, and setting the pressure in a reaction growth furnace to be 760 mT;

1b) heating the reaction growth furnace to 700 ℃, and then maintaining the growth temperature at 700 ℃;

1c) SiH is introduced into the reaction growth furnace through a particle sputtering source₄Growing a layer with height of 45nm, length of 182nm and doping concentration of 1 × 10 on the silicon dioxide layer¹⁵/cm³P of (a)^-Epitaxial layer, fig. 2 (a);

1d) after growth of P^-After the epitaxial layer is formed, the temperature is reduced compactly for 1 hour in a reaction growth furnace.

Step 2, by reversingApplying an ion etching process to make P^-Silicon epitaxial layer right side recess

2a) At P^-Coating photoresist with the thickness of 100nm on the upper surface of the molded substrate, developing, then flushing for 90 seconds under the liquid level of ultrapure water, and flushing in a nitrogen atmosphere;

2b) p after photoetching and developing treatment^-The substrate is fed into a plasma etching machine, the pressure of the etching cavity is manually set to be 10mT, the power is 20W, and 50sccm Cl is input into the etching cavity through a gas supply system₂And 20sccm of O₂Performing reactive ion etching, and forming a first region with a height of 25nm and a length of 112nm on the left side of the substrate after etching, as shown in FIG. 2 (b);

2c) and after etching, using stripping liquid to carry out organic cleaning on the device, and removing the residual photoresist.

Step 3, forming N by vapor phase epitaxy process growth⁺And (4) forming the interlayer.

3a) P after completion of etching^-Putting the type substrate into molecular beam epitaxial film growth equipment, opening a gas cylinder, introducing protective gas He gas into the equipment, and setting the pressure in a reaction growth furnace to be 760 mT;

3b) heating the reaction growth furnace to 700 ℃, and then maintaining the growth temperature at 700 ℃;

3c) SiH is introduced into the reaction growth furnace through a particle sputtering source₄At P^-A layer with the height of 45nm, the length of 70nm and the doping concentration of 5 multiplied by 10 is grown on the left upper part of the area¹⁸/cm³N of (A)⁺Type interlayer, as shown in fig. 2 (c);

3d) after growth of N⁺After the interlayer is formed, the temperature is reduced compactly for 1 hour in a reaction growth furnace.

Step 4, enabling N to be generated through a reactive ion etching process⁺The left side of the interlayer region is concave.

4a) In the growing of N⁺Coating photoresist with the thickness of 100nm on the upper surface of the interlayer, developing, then flushing for 90 seconds under the liquid level of ultrapure water, and flushing in a nitrogen atmosphere;

4b) sending the device subjected to photoetching development into a plasma etching machine, and manually setting the pressure of an etching cavity to be10mT, 20W, and 50sccm Cl into the etching chamber through the gas supply system₂And 20sccm of O₂Performing reactive ion etching, and forming a region with the height of 40nm and the length of 65nm on the right side of the substrate after etching, as shown in FIG. 2 (d);

4c) and after etching, using stripping liquid to carry out organic cleaning on the device, and removing the residual photoresist.

Step 5, growing P by vapor phase epitaxy process⁺And a source region.

5a) Putting the etched device into molecular beam epitaxial film growth equipment, opening a gas cylinder, introducing protective gas He gas into the equipment, and setting the pressure in a reaction growth furnace to be 760 mT;

5b) heating the reaction growth furnace to 700 ℃, and then maintaining the growth temperature at 700 ℃;

5c) SiH is introduced into the reaction growth furnace through a particle sputtering source₄In N at⁺A layer with the height of 40nm, the length of 65nm and the doping concentration of 1 multiplied by 10 is grown on the left upper part of the interlayer²⁰/cm³P of⁺Source region, as shown in FIG. 2 (e);

5d) after growth of P⁺And after the source region is formed, compactly cooling for 1 hour in a reaction growth furnace.

Step 6, depositing HfO above the channel by utilizing an atomic layer deposition process₂A film.

6a) Transferring the etched device into an atomic layer deposition system using HfCl with a purity of 99.95%₄O with high purity is used as the first precursor hafnium source₃As a second precursor oxygen source, pure nitrogen is used as a carrier, a first precursor hafnium source and the second precursor oxygen source are introduced into the reaction chamber, HCl is led out through the nitrogen, the temperature of the reaction chamber is set to be 250 ℃, and HfCl is set₄Air pressure of 3X 10^-4pa、O₃Air pressure of 2X 10^-1Pa, growing a layer of HfO with the thickness of 2nm on the channel₂Film, fig. 2 (f).

Step 7, depositing Hf on the channel by utilizing an atomic layer deposition process_0.5Zr_0.5O₂A ferroelectric thin film.

7a) Make itBy atomic layer deposition techniques using a hafnium source (HfCl)₄) And a source of zirconium (C)₈H₂₄N₄Zr) as a reaction precursor, ozone as an oxygen source, the temperature of the cavity is 250-280 ℃, the heating temperature of the reaction precursor is 75-80 ℃, and Hf: zr mole ratio of 0.5, preparing ferroelectric film with molecular formula of Hf_0.5Zr_0.5O₂Growing a layer of HfO with the thickness of 3nm on the oxide dielectric layer₂Film, FIG. 2 (g).

7b) Adopting a rapid annealing furnace (RTP), carrying out high annealing rate heat treatment in a nitrogen atmosphere at the temperature of 450-550 ℃ and the retention time of 20-60 s to change the zirconium element-doped hafnium oxide dielectric film into a ferroelectric film, wherein the annealing process is mainly divided into three stages: heating at high speed in nitrogen atmosphere, preserving heat for a short time and naturally cooling.

Step 8, removing the redundant ferroelectric dielectric layer above the device through a reactive ion etching process, and only remaining N⁺And the strip-shaped ferroelectric film on the right side of the interlayer/oxide dielectric layer.

8a) Sending the device subjected to ALD deposition and annealing into a plasma etcher, manually setting the pressure of an etching cavity to be 10mT and the power to be 20W, inputting 50sccm Cl2 and 20sccm O2 into the etching cavity through an air supply system, performing reactive ion etching, and performing reactive ion etching on the device in N⁺Forming a 3nm strip-shaped ferroelectric film on the right side of the interlayer/oxide dielectric layer as shown in FIG. 2 (h);

and 9, depositing a Cu metal gate region on the channel by utilizing an atomic layer deposition process.

9a) Transferring the etched device into an atomic layer deposition system, using CuN with the purity of 99.95% as a first precursor copper source, and using H with higher purity₂As a second precursor hydrogen source, pure Ar gas was used as a carrier, and the first precursor hafnium source and the second precursor hydrogen source were introduced into the reaction chamber while NH was derived from Ar gas₄At position P^-A metal gate region with a thickness of 68nm was deposited over the oxide dielectric layer over the substrate, as shown in fig. 2 (i).

And step 10, removing the redundant oxide dielectric layer through a reactive ion etching process.

10a) Placing the device after depositing the gate region into an etching system, manually setting the pressure of an etching cavity to be 10mT and the power to be 20W, and inputting C1 of 50sccm into the etching cavity through a gas supply system₂And 20sccm of O₂Performing reactive ion etching to completely etch the oxide dielectric layers above the source region and the drain region, as shown in fig. 2 (j);

step 11, growing P^-Forming N on the right part of the epitaxial layer by an ion implantation process⁺And a drain region.

At P^-The bottom implantation energy of the substrate is 10Kev, and the doping concentration is 1 × 10¹⁸/cm³Ar element (2) to form N with a thickness of 20nm and a length of 65nm⁺And a drain region, as shown in FIG. 2 (k).

Step 12, at P⁺Over the source region, over the gate region, N⁺And depositing corresponding electrodes above the drain regions by using a chemical vapor deposition process.

12a) Simultaneously flowing 20sccm SiH into the reaction chamber at 200 deg.C by chemical vapor deposition₄And N at a flow rate of 10sccm₂O is respectively at P⁺Over the source region, over the gate region, N⁺Depositing a layer of aluminum metal film above the drain region to form a source electrode and a drain electrode; a layer of polysilicon is deposited over the gate region to form a gate, as shown in fig. 2 (1).

12b) And washing the residual stripping solution by using ethanol and acetone to finish the preparation of the negative-capacitance L-type tunneling field effect transistor NC-LTFET device.

The effect of the present invention can be further illustrated by the following simulation results:

the transmission characteristics of the negative-capacitance L-gate tunneling field effect transistor NC-LTFET of the present example and the conventional L-channel tunneling field effect transistor LG-TFET were simulated under the condition that the drain voltage was 0.5V, and the result is fig. 3.

It can be found from fig. 3 that: when the grid voltage is 0.5V, the on-state current of the negative-capacitance L-shaped grid tunneling field effect transistor NC-LTFET is four times larger than that of the existing L-shaped channel tunneling field effect transistor, because the negative electricity of the inventionIntroducing metal/Hf to L-shaped gate tunneling field effect transistor NC-LTFET_0.5Zr_0.5O₂/HfO₂a/Si gate stack structure; the introduction of the gate stack also allows the NC-LTEFT to have a lower subthreshold slope. When the grid voltage is 0.05V, the negative capacitance L-shaped gate tunneling field effect transistor NC-LTFET is turned on, and the working voltage range of the NC-LTFET in the digital circuit is further expanded.

The invention is realized by introducing metal/Hf_0.5Zr_0.5O₂/HfO₂the/Si gate stack structure improves the on-state current of the tunneling field effect transistor TFET; generating an N on the left side of the gate region⁺Interlayer and P⁺The source region is used for increasing the tunneling area so as to hopefully form linear tunneling; while the introduced ferroelectric material can enhance N⁺The potential of the interlayer region, which will increase the tunneling probability of the device; in addition, having the aforementioned low concentration N⁺A sandwich structured device will have a smaller subthreshold slope in addition to a large on-current.

Although the present invention has been described in detail in this specification with reference to specific embodiments and illustrative embodiments, it will be apparent to those skilled in the art that modifications and improvements can be made thereto based on the present invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims

1. a negative capacitance L-type gate tunneling field effect transistor, comprising: P ^- substrate, P ⁺ type source region, gate region and drain region, it is characterized in that, described P ^- substrate below is provided with buried oxide layer , the upper left of the P ^- substrate is deposited with an N ⁺ -type interlayer, the right side of the P ^- substrate is etched with a lower step, and the drain region is located at the upper part of the lower step, and its thickness is the same as that of the P ^- substrate;

An upper step is etched on the N ⁺ type interlayer, a P ⁺ type source region is deposited on the upper part of the upper step, and a gate oxide layer dielectric is deposited on the upper right of the P ^- substrate. An HfZrO ferrodielectric layer is arranged between the dielectric and the gate region to enhance the potential at the N ⁺ -type interlayer on the right side of the P ⁺ -type source region of the L-type tunneling field effect transistor and increase the electron band-band tunneling probability.

2. The negative capacitance L-type gate tunneling field effect transistor according to claim 1, characterized in that,

The height of the P ⁺ type source region is 40±1 nm, the length is 65±1 nm, and the doping concentration is 10 ²⁰ /cm ³ ;

The height of the N ⁺ type interlayer is 40±1 nm, the length is 5±0.5 nm, and the doping concentration is 5×10 ¹⁸ /cm ³ ;

The drain region is an N ⁺ type drain region, the height of which is 20±1 nm, the length is 65±1 nm, and the doping concentration is 10 ¹⁸ /cm ³ ;

The P ⁺ -type source region, the N ⁺ -type interlayer, and the N ⁺ -type drain region are respectively prepared with silicon materials.

3 . The negative capacitance L-type gate tunneling field effect transistor according to claim 2 , wherein the gate oxide layer dielectric has an “L” shape, is made of HfO ₂ material, and has a thickness of 2±0.2 nm. 4 .

4 . The negative capacitance L-type gate tunneling field effect transistor according to claim 3 , wherein the gate region has a height of 68±1 nm and a length of 45±2 nm. 5 .

5 . The negative capacitance L-gate tunneling field effect transistor according to claim 4 , wherein the material of the HfZrO ferroelectric dielectric layer is Hf _0.5 Zr _0.5 O, and the thickness is 3±0.2 nm. 6 .

6. a preparation method of negative capacitance L-type gate tunneling field effect transistor, is characterized in that, comprises the following steps:

1) A layer of P ^- type region with a thickness of 45±1nm, a length of 182±1nm and a doping concentration of 1×10 ¹⁵ /cm ³ is grown on the substrate by a vapor phase epitaxy process;

2) Apply photoresist on the left side of the P ^- type region, and use a reactive ion etching process to generate a first region with a height of 25±1nm and a length of 112±1nm on the right side of the P ^- type region;

3) Remove the photoresist, and use a vapor phase epitaxy process to grow an N ⁺ type interlayer with a height of 45±1 nm, a length of 70±1 nm, and a doping concentration of 5×10 ¹⁸ /cm ³ on the left side of the P ^- type region;

4) using the reactive ion etching process to generate a second region with a height of 40 ± 1 nm and a length of 65 ± 1 nm in the generated N ⁺ type interlayer region;

5) In the second region, a layer of P ⁺ type source region with a height of 40±1 nm, a length of 65±1 nm and a doping concentration of 1×10 ²⁰ /cm ³ is grown by a vapor phase epitaxy process;

6) In the P ⁺ type source region and the first region, use the atomic layer deposition process to deposit a layer of HfO ₂ thin film with a thickness of 2±0.2 nm, that is, the gate oxide layer dielectric;

7) On the gate oxide layer dielectric, deposit a layer of Hf _0.5 Zr _0.5 O ferroelectric thin film with a thickness of 3±0.2 nm by using an atomic layer deposition process;

8) using a reactive ion etching process to remove the ferroelectric thin film in the horizontal direction to obtain a vertical ferroelectric layer;

9) depositing a metal gate region with a thickness of 68 nm on the right side of the vertical ferrodielectric layer using an atomic layer deposition process;

10) using reactive ion etching process to remove the gate oxide layer dielectric above the source region and the P ^- type substrate to form an "L" type HfO2 thin film structure;

11) Implant Ar element with energy of 10±0.5Kev and dose of 1×10 ¹⁸ /cm ³ into the right part of the P-type substrate to form an N ⁺ drain region with a height of 20±1nm and a length of 65±1nm;

12) The source electrode, the drain electrode and the gate electrode are respectively deposited by chemical vapor deposition on the top of the P ⁺ type source region, the top of the N ⁺ drain region and the top of the gate region to complete the device fabrication.

7. The preparation method of the negative capacitance L-type gate tunneling field effect transistor according to claim 6, wherein in steps 1), 3) and 5), the process condition of the vapor phase epitaxy process is: growth temperature is 780° C., the reaction source gas is SiH ₄ , the protective gas is He, and the pressure in the reaction chamber is 760 mT.

8. The preparation method of the negative capacitance L-type gate tunneling field effect transistor according to claim 6, wherein in steps 2), 4), 8) and 10), the process of the reactive ion etching process The conditions are: the reaction gas is Cl ₂ and O ₂ ; the pressure in the reaction chamber is 10mT, and the power is 20W.

9. The preparation method of the negative capacitance L-type gate tunneling field effect transistor according to claim 6, wherein in step 6), the process condition of the atomic layer deposition process is: using a hafnium source as a precursor Ozone is used as reactant and nitrogen is used as carrier gas; the temperature of the reaction chamber is 250℃; the pressure of hafnium source is 3×10 ^-4 Pa; the pressure of ozone is 2×10 ^-1 Pa;

In step 7), the process conditions of the atomic layer deposition process are: using hafnium and zirconium as precursor molecules; using ozone as a reactant, using nitrogen as a carrier gas; the heating temperature of the reaction precursor is 75-80 ° C, The molar ratio of Hf:Zr is 0.5; the temperature of the reaction chamber is 250-280° C.; the gas pressure of ozone is 2×10 ^-1 Pa.

10. The preparation method of the negative capacitance L-type gate tunneling field effect transistor according to claim 6, wherein in step 9), the process condition of the atomic layer deposition process is: using a copper source as the precursor H ₂ was used as the reactant, and argon was used as the carrier gas; the temperature of the reaction chamber was 250°C; the pressure of the copper source was 3×10 ^-4 Pa; the pressure of H ₂ was 2×10 ^-1 Pa.