CN113675195B - Semiconductor device and method for forming the same - Google Patents

Abstract

A semiconductor device including an air spacer formed in a backside interconnect structure and a method for forming the same are disclosed. In an embodiment, the device includes: a first transistor structure; a frontside interconnect structure located on the front side of the first transistor structure; and a backside interconnect structure located on the back side of the first transistor structure, the backside interconnect structure including: a first dielectric layer located on the back side of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent to the first conductive line in a direction parallel to the back side of the first dielectric layer.

Description

Semiconductor device and method for forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background Art

Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be solved.

Summary of the invention

Some embodiments of the present application provide a semiconductor device, including: a first transistor structure; a front-side interconnect structure located on the front side of the first transistor structure; and a back-side interconnect structure located on the back side of the first transistor structure, the back-side interconnect structure including: a first dielectric layer located on the back side of the first transistor structure; a first through-hole extending through the first dielectric layer, the first through-hole electrically coupled to the source/drain region of the first transistor structure; a first wire electrically coupled to the first through-hole; and an air spacer adjacent to the first wire in a direction parallel to the back side of the first dielectric layer.

Other embodiments of the present application provide a semiconductor device, comprising: a transistor structure; a front-side interconnect structure located on the front side of the transistor structure; and a back-side interconnect structure located on the back side of the transistor structure, the back-side interconnect structure comprising: a conductive line electrically coupled to a source/drain region of the transistor structure through a back-side through hole; a first dielectric layer contacting a side of the conductive line; and an air gap adjacent to the first dielectric layer, wherein the side of the first dielectric layer defines a first boundary of the air gap.

Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first transistor on a first substrate; exposing a first epitaxial material, wherein exposing the first epitaxial material comprises thinning the back side of the first substrate; replacing the first epitaxial material with a back side via, wherein the back side via is electrically coupled to a source/drain region of the first transistor; forming a conductive wire above the back side via, wherein the conductive wire is electrically coupled to the back side via; forming a dummy spacer adjacent to the conductive wire; etching the dummy spacer to form a first groove; and sealing the first groove to form an air spacer.

BRIEF DESCRIPTION OF THE DRAWINGS

When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be increased or reduced at will.

FIG. 1 illustrates an example of a nanostructured field effect transistor (nanoFET) in a three-dimensional view, according to some embodiments.

Figure 2, Figure 3, Figure 4, Figure 5, Figure 6A, Figure 6B, Figure 6C, Figure 7A, Figure 7B, Figure 7C, Figure 8A, Figure 8B, Figure 8C, Figure 9A, Figure 9B, Figure 9C, Figure 10A, Figure 10B, Figure 10C, Figure 11A, Figure 11B, Figure 11C, Figure 11D, Figure 12A, Figure 12B, Figure 12C, Figure 12D, Figure 12E, Figure 13A, Figure 13B, Figure 13C, Figure 14A, Figure 14B , Figure 14C, Figure 15A, Figure 15B, Figure 15C, Figure 16A, Figure 16B, Figure 16C, Figure 17A, Figure 17B, Figure 17C, Figure 18A, Figure 18B, Figure 18C, Figure 19A, Figure 19B, Figure 19C, Figure 20A, Figure 20B, Figure 20C, Figure 20D, Figure 21A, Figure 21B, Figure 21C, Figure 22A, Figure 22B, Figure 22C, Figure 23A, Figure 23B, Figure 23C , Figure 24A, Figure 24B, Figure 24C, Figure 25A, Figure 25B, Figure 25C, Figure 26A, Figure 26B, Figure 26C, Figure 26D, Figure 27A, Figure 27B, Figure 27C, Figure 28A, Figure 28B, Figure 28C, Figure 29A, Figure 29B, Figure 29C, Figure 30A, Figure 30B, Figure 30C, Figure 31A, Figure 31B, Figure 31C, Figure 32A, Figure 32B, Figure 32C, Figure 33 A, Figure 33B, Figure 33C, Figure 34A, Figure 34B, Figure 34C, Figure 35A, Figure 35B, Figure 35C, Figure 36A, Figure 36B, Figure 36C, Figure 37A, Figure 37B, Figure 37C, Figure 38A, Figure 38B, Figure 38C, Figure 39A, Figure 39B, Figure 39C, Figure 40A, Figure 40B and Figure 40C are cross-sectional views of intermediate stages in the manufacture of nanoFETs according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and/or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

Various embodiments provide semiconductor devices including air spacers formed in a backside interconnect structure and methods for forming the same. The air spacers may be formed adjacent to a conductor in the backside interconnect structure, which is used for routing power lines, electrical ground lines, and the like. The air spacers may provide improved isolation between the conductors, which reduces capacitive coupling and allows the use of increased device speeds. The air spacers may be formed by depositing a sacrificial dielectric layer over the conductors; removing the sacrificial dielectric layer to form a groove; and sealing the groove with an additional dielectric layer.

Some embodiments discussed herein are described in the context of dies including nanoFETs. However, various embodiments may be applied to dies including other types of transistors (eg, fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanoFETs.

FIG. 1 shows an example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, etc.) in a three-dimensional view according to some embodiments. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) located above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 is used as a channel region for the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. A shallow trench isolation (STI) region 68 is disposed between adjacent fins 66 that may protrude above and between adjacent STI regions 68. Although the STI region 68 is described/illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or to a combination of a semiconductor substrate and an STI region. In addition, although the bottom of the fin 66 is shown as a single, continuous material like the substrate 50, the bottom of the fin 66 and/or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to a portion extending between adjacent STI regions 68.

Gate dielectric layer 100 is located over the top surface of fin 66 and along the top surface, sidewalls and bottom surface of nanostructure 55. Gate electrode 102 is located over gate dielectric layer 100. Epitaxial source/drain regions 92 are disposed on fin 66 on opposite sides of gate dielectric layer 100 and gate electrode 102.

1 also shows reference cross sections used in subsequent figures. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, e.g., perpendicular to the direction of current flow between the epitaxial source/drain regions 92 of the nanoFETs. Cross section B-B' is parallel to cross section A-A' and extends through the epitaxial source/drain regions 92 of a plurality of nanoFETs. Cross section C-C' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fins 66 of the nanoFETs and in a direction of current flow between the epitaxial source/drain regions 92 of the nanoFETs. For clarity, subsequent figures refer to these reference cross sections.

Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Moreover, some embodiments contemplate aspects used in planar devices such as planar FETs or in fin field effect transistors (FinFETs).

Figures 2 to 39C are cross-sectional views of intermediate stages in the fabrication of a nanoFET according to some embodiments. Figures 2 to 5, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A, 30A, 31A, 32A, 33A, 34A, 35A, 36A, 37A, 38A, and 39A show reference cross section A-A' shown in Figure 1. Figures 6B, 7B, 8B, 9B, 10B, 11B, 12B, 12D, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, 28B, 29B, 30B, 31B, 32B, 33B, 34B, 35B, 36B, 37B, 38B and 39B show the reference section B-B’ shown in Figure 1. Figures 7C, 8C, 9C, 10C, 11C, 11D, 12C, 12E, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 20D, 21C, 22C, 23C, 24C, 25C, 26C, 26D, 27C, 28C, 29C, 30C, 31C, 32C, 33C, 34C, 35C, 36C, 37C, 38C and 39C show the reference section C-C’ shown in Figure 1.

In FIG. 2 , a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.

The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type nano FET, and the p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type nano FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

Further in FIG. 2 , a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustration purposes, and as discussed in more detail below, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of the nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the n-type region 50N and the p-type region 50P.

For illustrative purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanoFET (such as silicon germanium, etc.), and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanoFET (such as silicon, silicon carbon, etc.). For illustrative purposes, the multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for a p-type nanoFET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an n-type nanoFET.

The first semiconductor material and the second semiconductor material can be materials with high etching selectivity to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

Referring now to FIG. 3 , in accordance with some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64 . In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50 , respectively, by etching trenches in multilayer stack 64 and substrate 50 . Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. Etching may be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 may further define first nanostructures 52A-52C (collectively referred to as first nanostructures 52 ) from first semiconductor layer 51 , and define second nanostructures 54A-54C (collectively referred to as second nanostructures 54 ) from second semiconductor layer 53 . First nanostructures 52 and second nanostructures 54 may be collectively referred to as nanostructures 55 .

The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, the fins 66 and nanostructures 55 may be patterned using one or more photolithography processes including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the generation of patterns with, for example, a pitch smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.

For illustrative purposes, FIG. 3 shows the fins 66 in the n-type region 50N and the p-type region 50P as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or thinner than the width of the fins 66 in the p-type region 50P. In addition, while each of the fins 66 and nanostructures 55 is shown as having a uniform width throughout, in other embodiments, the fins 66 and/or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and/or nanostructures 55 increases continuously in a direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have different widths and be trapezoidal in shape.

In FIG. 4 , a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide, a nitride, or the like, such as silicon oxide, or a combination thereof, and can be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 50, the fin 66, and the nanostructure 55. Thereafter, a filling material such as those discussed above may be formed over the liner.

Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be used. The planarization process exposes the nanostructure 55 so that after the planarization process is completed, the top surface of the nanostructure 55 and the insulating material are flush.

The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (such as a groove) as shown, or a combination thereof. The top surface of the STI region 68 may be formed to be flat, convex and/or concave by appropriate etching. The STI region 68 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 66 and the nanostructure 55). For example, oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.

The processes described above with respect to FIGS. 2 to 4 are merely one example of how fins 66 and nanostructures 55 may be formed. In some embodiments, fins 66 and/or nanostructures 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form fins 66 and/or nanostructures 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may eliminate previous and/or subsequent implants, but in situ and implant doping may be used together.

In addition, for illustration purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials, or may be formed in a different order in the p-type region 50P and the n-type region 50N.

Further in FIG. 4 , appropriate wells (not shown separately) may be formed in the fin 66, the nanostructure 55, and/or the STI region 68. In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P may be implemented using a photoresist or other mask (not shown separately). For example, a photoresist may be formed over the fin 66 and the STI region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is implemented in the p-type region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., at a concentration in the range of about 10 ¹³ atoms/cm ³ to about 10 ¹⁴ atoms/cm ³ implanted in the region. After implantation, the photoresist is removed, such as by an acceptable ashing process.

After or before the p-type region 50P is implanted, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., at a concentration in the range of about 10 ¹³ atoms/cm ³ to about 10 ¹⁴ atoms/cm ³ injected in the region. After the implantation, the photoresist can be removed, such as by an acceptable ashing process.

After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate implanted p-type and/or n-type impurities. In some embodiments, the growing material of the epitaxial fin may be doped in situ during growth, which may eliminate implantation, but in situ and implantation doping may be used together.

In FIG. 5 , a pseudo dielectric layer 70 is formed on the fin 66 and/or the nanostructure 55. The pseudo dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A pseudo gate layer 72 is formed above the pseudo dielectric layer 70, and a mask layer 74 is formed above the pseudo gate layer 72. The pseudo gate layer 72 may be deposited above the pseudo dielectric layer 70 and then planarized, such as by CMP. A mask layer 74 may be deposited above the pseudo gate layer 72. The pseudo gate layer 72 may be a conductive material or a non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (poly silicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The pseudo gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The pseudo gate layer 72 may be made of other materials having high etching selectivity from the etching isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that for illustration purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

6A to 18C illustrate various additional steps in manufacturing an embodiment device. FIG. 6A to 18C illustrate components in any one of the n-type region 50N or the p-type region 50P. In FIG. 6A to 6C, a mask layer 74 (see FIG. 5) may be patterned using acceptable photolithography and etching techniques to form a mask 78. The pattern of the mask 78 may then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 may be used to physically separate each of the dummy gates 76 from the adjacent dummy gates 76. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66.

In FIGS. 7A to 7C , a first spacer layer 80 and a second spacer layer 82 are formed over the structure shown in FIGS. 6A to 6C . The first spacer layer 80 and the second spacer layer 82 will then be patterned to serve as spacers for forming self-aligned source/drain regions. In FIGS. 7A to 7C , a first spacer layer 80 is formed on the top surface of the STI region 68 ; a first spacer layer 80 is formed on the top surface and sidewalls of the fin 66 , the nanostructure 55 , and the mask 78 ; and a first spacer layer 80 is formed on the sidewalls of the dummy gate 76 and the dummy gate dielectric 71 . A second spacer layer 82 is deposited over the first spacer layer 80 . The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or may be deposited by CVD, ALD, etc. The second spacer layer 82 may be formed of a material having a different etch rate than the material of the first spacer layer 80 , such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be deposited by CVD, ALD, etc.

After forming the first spacer layer 80 and before forming the second spacer layer 82, an implantation for a lightly doped source/drain (LDD) region (not shown separately) may be performed. In embodiments with different device types, similar to the implantation discussed above in FIG. 4, a mask such as a photoresist may be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source/drain regions may have an impurity concentration in a range from about 1×10 ¹⁵ atoms/cm ³ to about 1×10 ¹⁹ atoms/cm ^3. Annealing may be used to repair implantation damage and activate implanted impurities.

In FIGS. 8A to 8C , the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source/drain regions, and to protect the sidewalls of the fin 66 and/or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that the first spacer layer 80 can be used as an etching stop layer when patterning the second spacer layer 82, and so that the second spacer layer 82 can be used as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 may be etched using an anisotropic etching process, wherein the first spacer layer 80 serves as an etch stop layer, wherein the remaining portion of the second spacer layer 82 forms a second spacer layer 83 as shown in FIG8B . Thereafter, the second spacer 83 serves as a mask while etching the exposed portion of the first spacer layer 80, thereby forming the first spacer 81 as shown in FIGS. 8B and 8C .

As shown in Fig. 8B, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and/or the nanostructure 55. As shown in Fig. 8C, in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 60. In other embodiments, a portion of the second spacer layer 82 can remain above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, steps in different sequences may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, and the like. In addition, n-type and p-type devices may be formed using different structures and steps.

In FIGS. 9A to 9C , according to some embodiments, first recesses 86 and second recesses 87 are formed in fin 66, nanostructure 55, and substrate 50. An epitaxial source/drain region will be subsequently formed in first recess 86, and a first epitaxial material and an epitaxial source/drain region will be subsequently formed in second recess 87. First recess 86 and second recess 87 may extend through first nanostructure 52 and second nanostructure 54, and extend into substrate 50. As shown in FIG. 9B , the top surface of STI region 58 may be flush with the bottom surface of first recess 86. In various embodiments, fin 66 may be etched so that the bottom surface of first recess 86 is disposed below the top surface of STI region 68, etc. The bottom surface of second recess 87 may be disposed below the bottom surface of first recess 86 and the top surface of STI region 68. First recess 86 and second recess 87 may be formed by etching fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first groove 86 and the second groove 87, the first spacer 81, the second spacer 83 and the mask 78 mask the fin 66, the nanostructure 55 and the portion of the substrate 50. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55 and/or the fin 66. After the first groove 86 and the second groove 87 reach the desired depth, a timed etching process can be used to stop etching. The second groove 87 can be etched by the same process used to etch the first groove 86 and an additional etching process before or after etching the first groove 86. In some embodiments, the area corresponding to the first groove 86 can be masked while the additional etching process for the second groove 87 is implemented.

In FIGS. 10A to 10C , portions of the sidewalls of the layers of the multilayer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first recess 86 and the second recess 87 are etched to form sidewall recesses 88. Although the sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 are shown as straight in FIG. 10C , the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process such as wet etching. In embodiments where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, a dry etching process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH ₄ OH), or the like may be used to etch the sidewalls of the first nanostructure 52.

In FIGS. 11A to 11D , a first internal spacer 90 is formed in the sidewall recess 88. The first internal spacer layer 90 can be formed by depositing an internal spacer layer (not shown separately) over the structure shown in FIGS. 10A to 10C . The first internal spacer 90 serves as an isolation member between the subsequently formed source/drain regions and the gate structure. As will be discussed in more detail below, the source/drain regions and the epitaxial material will be formed in the first recess 86 and the second recess 87, while the first nanostructure 52 will be replaced by the corresponding gate structure.

The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized such as any low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 or be recessed from the sidewalls of the second nanostructure 54.

In addition, although the outer sidewalls of the first inner spacer 90 are shown as straight in FIG. 11C , the outer sidewalls of the first inner spacer 90 may be concave or convex. As an example, FIG. 11D shows an embodiment in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. The inner spacer layer may be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions 92 discussed below with respect to FIGS. 12A to 12E ) by subsequent etching processes (such as etching processes used to form gate structures).

In FIGS. 12A to 12E , a first epitaxial material 91 is formed in the second recess 87 , and an epitaxial source/drain region 92 is formed in the first recess 86 and the second recess 87 . In some embodiments, the first epitaxial material 91 may be a sacrificial material that is subsequently removed to form a backside via (such as the backside via 130 discussed below with respect to FIGS. 26A to 26D ). As shown in FIGS. 12B to 12E , the top surface of the first epitaxial material 91 may be flush with the bottom surface of the first recess 86 . However, in some embodiments, the top surface of the first epitaxial material 91 may be disposed above or below the bottom surface of the first recess 86 . The first epitaxial material 91 may be epitaxially grown in the second recess 87 using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), and the like. The first epitaxial material 91 may include any acceptable material, such as silicon germanium, and the like. The first epitaxial material 91 may be formed of a material having a high etch selectivity to the material of the epitaxial source/drain regions 92, the substrate 50, and dielectric layers (such as the STI regions 68 and the second dielectric layer 125 discussed below with respect to FIGS. 24A to 24C ). Thus, the first epitaxial material 91 may be removed and replaced with the backside vias without significantly removing the epitaxial source/drain regions 92 and the dielectric layers.

Then, epitaxial source/drain regions 92 are formed over the first epitaxial material 91 in the first recess 86 and the second recess 87. In some embodiments, the epitaxial source/drain regions 92 can exert stress on the second nanostructure 54, thereby improving performance. As shown in FIG. 12C , the epitaxial source/drain regions 92 are formed in the first recess 86 and the second recess 87 so that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source/drain regions 92. In some embodiments, the first spacer 81 is used to separate the epitaxial source/drain regions 92 from the dummy gate 76, and the first internal spacer 90 is used to separate the epitaxial source/drain regions 92 from the nanostructure 55 by an appropriate lateral distance so that the epitaxial source/drain regions 92 do not short circuit with the subsequently formed gate of the resulting nanoFET.

The epitaxial source/drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the epitaxial source/drain region 92 is epitaxially grown in the first groove 86 and the second groove 87 in the n-type region 50N. The epitaxial source/drain region 92 may include any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructure 54 is silicon, the epitaxial source/drain region 92 may include a material that applies tensile strain on the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source/drain region 92 may have a surface protruding from the corresponding upper surface of the nanostructure 55, and may have a small facet.

The epitaxial source/drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). Then, the epitaxial source/drain region 92 is epitaxially grown in the first groove 86 and the second groove 87 in the p-type region 50P. The epitaxial source/drain region 92 may include any acceptable material suitable for a p-type nano FET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source/drain region 92 may include a material that applies compressive strain on the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source/drain region 92 may also have a surface that protrudes from the corresponding surface of the multilayer stack 56 and may have a small facet.

The epitaxial source/drain region 92, the first nanostructure 52, the second nanostructure 54, and/or the substrate 50 may be implanted with dopants to form the source/drain region, similar to the process previously discussed for forming the lightly doped source/drain region, followed by annealing. The source/drain region may have an impurity concentration between about 1×10 ¹⁹ atoms/cm ³ and about 1×10 ²¹ atoms/cm ^3. The n-type and/or p-type impurities used for the source/drain region may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain region 92 may be doped in situ during growth.

Due to the epitaxial process used to form the epitaxial source/drain region 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source/drain region 92 has a small facet that extends laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small facets merge adjacent epitaxial source/drain regions 92 of the same nanoFET, as shown in FIG. 12B. In other embodiments, as shown in FIG. 12D, after the epitaxial process is completed, adjacent epitaxial source/drain regions 92 remain separated. In the embodiments shown in FIG. 12B and FIG. 12D, the first spacer 81 can form the top surface of the STI region 68, thereby preventing epitaxial growth. In some other embodiments, the first spacer 81 can cover a portion of the sidewall of the nanostructure 55, thereby further preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material to allow the epitaxially grown area to extend to the surface of the STI region 58.

The epitaxial source/drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source/drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source/drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment where the epitaxial source/drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited above the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited above the second semiconductor material layer 92B.

12E shows an embodiment in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. As shown in FIG12E, the epitaxial source/drain regions 92 may be formed to contact the first inner spacer 90 and may extend over the sidewalls of the second nanostructure 54.

In FIGS. 13A to 13C , a first interlayer dielectric (ILD) 96 is deposited over the structure shown in FIGS. 12A to 12C . The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD) or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source/drain regions 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material having an etch rate different from that of the material of the first ILD 96 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

In FIGS. 14A to 14C , a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

In FIGS. 15A to 15C , the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps, thereby forming a third recess 98. The portion of the dummy gate dielectric 60 located in the third recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each of the third recesses 98 exposes and/or covers a portion of the nanostructure 55, which is used as a channel region in a subsequently completed nanoFET. The portion of the nanostructure 55 used as a channel region is disposed between adjacent pairs of epitaxial source/drain regions 92. During removal, the dummy gate dielectric 60 can be used as an etch stop layer when etching the dummy gate 76. The dummy gate dielectric 60 can then be removed after removing the dummy gate 76.

16A to 16C , the first nanostructure 52 is removed to extend the third recess 98. The first nanostructure 52 may be removed by performing an isotropic etching process such as a wet etch using an etchant selective to the material of the first nanostructure 52, and the second nanostructure 54, the substrate 50, and the STI region 58 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH ₄ OH), or the like may be used to remove the first nanostructure 52.

In FIGS. 17A to 17C , a gate dielectric layer 100 and a gate electrode 102 are formed for replacing the gate. The gate dielectric layer 100 is conformally deposited in the third recess 98. The gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68 and on the sidewalls of the first spacer 81 and the first inner spacer 90.

According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer located above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

A gate electrode 102 is deposited over the gate dielectric layer 100, respectively, and the remaining portion of the third recess 98 is filled. The gate electrode 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. For example, although a single-layer gate electrode 102 is shown in FIGS. 17A and 17C , the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filling materials. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, so that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, so that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, so that the gate dielectric layer 100 may be a different material and/or have a different number of layers, and/or the gate electrode 102 in each region may be formed by a different process, so that the gate electrode 102 may be a different material and/or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

After filling the third recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 100 and the material of the gate electrode 102, which are located above the top surface of the first ILD 96. Thus, the gate electrode 102 and the remaining portions of the material of the gate dielectric layer 100 form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure".

18A to 18C , the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102 thereon) is recessed so that a groove is formed directly above the gate structure and between the opposing portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.) is filled in the groove, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. A subsequently formed gate contact (such as the gate contact 114 discussed below with reference to FIGS. 20A to 20C ) penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

18A to 18C , a second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

In FIGS. 19A to 19C , the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a fourth recess 108 that exposes the surface of the epitaxial source/drain region 92 and/or the gate structure. The fourth recess 108 may be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the fourth recess 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process; the fourth recess 108 may be etched through the gate mask 104 using a second etching process; and then the fourth recess 108 may be etched through the CESL 94 using a third etching process. A mask such as a photoresist may be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the fourth recess 108 extends into the epitaxial source/drain region 92 and/or the gate structure, and the bottom of the fourth recess 108 may be flush with (e.g., at the same level, or having the same distance from the substrate 50) or lower than (e.g., closer to the substrate 50) the epitaxial source/drain region 92 and/or the gate structure. Although FIG. 19C shows the fourth recess 108 as exposing the epitaxial source/drain region 92 and the gate structure in the same cross section, in various embodiments, the epitaxial source/drain region 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of shorting of subsequently formed contacts.

After forming the fourth recess 108, a first silicide region 110 is formed over the epitaxial source/drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown separately) that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source/drain region 92 to form a silicide or germanide region (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) over the exposed portion of the epitaxial source/drain region 92, and then performing a thermal annealing process to form the first silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, the first silicide region 110 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide). In an embodiment, the first silicide region 110 includes TiSi and has a thickness ranging from about 2 nm to about 10 nm.

In FIGS. 20A to 20C , source/drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed in the fourth recess 108. The source/drain contacts 112 and the gate contacts 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the source/drain contacts 112 and the gate contacts 114 each include a barrier layer and a conductive material, and each is electrically coupled to the underlying conductive component (e.g., the gate electrode 102 and/or the first silicide region 110). The gate contact 114 is electrically coupled to the gate electrode 102, and the source/drain contact 112 is electrically coupled to the first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106. The epitaxial source/drain regions 92, the second nanostructure 54, and the gate structure (including the gate dielectric layer 100 and the gate electrode 102) may be collectively referred to as a transistor structure 109. A first interconnect structure (such as the front-side interconnect structure 120 discussed below with respect to FIGS. 21A to 21C) may be formed over the front side of the transistor structure 109, and a second interconnect structure (such as the back-side interconnect structure 164 discussed below with respect to FIGS. 39A to 39C) may be formed over the back side of the transistor structure 109. Although the transistor structure 109 is described as including a nanoFET, other embodiments may include a transistor structure 109 including different types of transistors (e.g., planar FETs, FinFETs, thin film transistors (TFTs), etc.).

Although FIGS. 20A-20C show source/drain contacts 112 extending to each of the epitaxial source/drain regions 92, the source/drain contacts 112 may be omitted from certain epitaxial source/drain regions 92. For example, as explained in more detail below, a conductive feature (e.g., a backside via or power rail) may be subsequently attached through the backside of one or more epitaxial source/drain regions 92. For these particular epitaxial source/drain regions 92, the source/drain contacts 112 may be omitted or may be dummy contacts that are not electrically connected to any overlying conductive lines (such as the first conductive features 122 discussed below with reference to FIGS. 21A-21C).

FIG. 20D shows a cross-sectional view along section C-C' of FIG. 1 of the device according to some embodiments. The embodiment of FIG. 20D may be similar to the embodiment described above with respect to FIG. 20A to FIG. 20C, where the same reference numerals indicate the same elements formed using the same process. However, in FIG. 20D, the source/drain contacts 112 may have a composite structure, and each may include a first contact 112A in the first ILD 96 and a second contact 112B in the second ILD 106. In some embodiments, the first contact 112A may be formed in the first ILD 96 before the second ILD 106 is deposited. The first contact 112A may be recessed from the top surface of the first ILD 96. After the first contact 112A is recessed, an insulating mask 117 may be deposited to cover the first contact 112A. The first contact 112A may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), combinations thereof, and the like, and may have a thickness ranging from about 1 nm to about 50 nm (e.g., measured between opposing sidewalls). The insulating mask 117 may include silicon oxide (SiO), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), combinations thereof, and the like. In some embodiments, the material of the insulating mask 117 may be different from that of the gate mask 104 so that the insulating mask 117 and the gate mask 104 may be selectively etched relative to each other. In this way, the second contact 112B and the gate contact 114 may be formed independently of each other.

Subsequently, the second ILD 106 is deposited over the insulating mask 117 and the first contact 112A as described above. After the second ILD 106 is deposited, the second contact 112B may be formed to extend through the second ILD 106 and the insulating mask 117 and electrically coupled to the first contact 112A. The second contact 112B may further partially extend into the first contact 112A and be embedded in the first contact 112A. The second contact 112B may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), combinations thereof, etc., and may have a thickness ranging from about 1 nm to about 50 nm (e.g., measured between opposing sidewalls). The thickness of the second contact 112B may be the same as or different from the thickness of the first contact 112A, and the material of the second contact 112B may be the same as or different from the material of the first contact 112A. Thus, a composite source/drain contact 112 including a first contact 112A and a second contact 112B may be formed. For ease of illustration, subsequent process steps are described with respect to the embodiment of FIGS. 20A to 20C ; however, it should be understood that they are equally applicable to the embodiment of FIG. 20D . In some embodiments, other configurations of the source/drain contact 112 are also possible.

21A to 39C illustrate intermediate steps in forming a front-side interconnect structure and a back-side interconnect structure on transistor structure 109. The front-side interconnect structure and the back-side interconnect structure may each include a conductive feature electrically connected to a nanoFET formed on substrate 50. In FIGS. 21A to 39C, the figures ending with "A" illustrate a cross-sectional view along line A-A' of FIG. 1, the figures ending with "B" illustrate a cross-sectional view along line B-B' of FIG. 1, and the figures ending with "C" illustrate a cross-sectional view along line C-C' of FIG. 1. The process steps described in FIGS. 21A to 29C may be applied to n-type region 50N and p-type region 50P. As noted above, a back-side conductive feature (e.g., a back-side via or power rail) may be connected to one or more of epitaxial source/drain regions 92. Thus, source/drain contacts 112 may be optionally omitted from epitaxial source/drain regions 92.

21A-21C , a front side interconnect structure 120 is formed on the second ILD 106. The front side interconnect structure 120 may be referred to as a front side interconnect structure because it is formed on the front side of the transistor structure 109 (e.g., the side of the transistor structure opposite to the substrate 50 on which the transistor structure 109 is formed).

The front-side interconnect structure 120 may include one or more layers of first conductive features 122 formed in one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 may include a dielectric material, such as a low-k dielectric material, an ultra-low-k (ELK) dielectric material, etc. The first dielectric layer 124 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc.

The first conductive component 122 may include conductive wires and conductive vias that interconnect the conductive wire layers. The conductive vias may extend through the corresponding first dielectric layer 124 to provide vertical connections between the conductive wire layers. The first conductive component 122 may be formed by any acceptable process (e.g., a damascene process, a dual damascene process, etc.).

In some embodiments, the first conductive component 122 can be formed using a damascene process, in which the corresponding first dielectric layer 124 is patterned using a combination of photolithography and etching techniques to form a groove corresponding to the desired pattern of the first conductive component 122. An optional diffusion barrier layer and/or an optional adhesion layer can be deposited, and the groove can then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, and the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like. In an embodiment, the first conductive component 122 can be formed by depositing a seed layer of copper or a copper alloy and filling the groove by electroplating. A chemical mechanical planarization (CMP) process or the like can be used to remove excess conductive material from the surface of the corresponding first dielectric layer 124, and planarize the surfaces of the first dielectric layer 124 and the first conductive component 122 for subsequent processing.

21A to 21C show five layers of first conductive features 122 and first dielectric layers 124 in the front-side interconnect structure 120. However, it should be understood that the front-side interconnect structure 120 may include any number of first conductive features 122 disposed in any number of first dielectric layers 124. The front-side interconnect structure 120 may be electrically connected to the gate contact 114 and the source/drain contact 112 to form a functional circuit. In some embodiments, the functional circuit formed by the front-side interconnect structure 120 may include a logic circuit, a memory circuit, an image sensor circuit, etc.

22A to 22C , a carrier substrate 180 is bonded to the top surface of the front-side interconnect structure 120 by a first bonding layer 182A and a second bonding layer 182B (collectively referred to as bonding layers 182). The carrier substrate 180 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The carrier substrate 180 may provide structural support during subsequent processing steps and in a completed device.

In various embodiments, the carrier substrate 180 may be bonded to the front side interconnect structure 120 using a suitable technique such as dielectric-to-dielectric bonding. The dielectric-to-dielectric bonding may include depositing a first bonding layer 182A on the front side interconnect structure 120. In some embodiments, the first bonding layer 182A includes silicon oxide (e.g., high density plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. The second bonding layer 182B may also be an oxide layer formed on the surface of the carrier substrate 180 before bonding, for example, using CVD, ALD, PVD, thermal oxidation, etc. Other suitable materials may be used for the first bonding layer 182A and the second bonding layer 182B.

The dielectric to dielectric bonding process may further include applying a surface treatment to one or more of the first bonding layer 182A and the second bonding layer 182B. The surface treatment may include a plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more of the bonding layers 182. Then, the carrier substrate 180 is aligned with the front side interconnect structure 120, and the two are pressed against each other to start the pre-bonding of the carrier substrate 180 to the front side interconnect structure 120. Pre-bonding may be implemented at room temperature (e.g., between about 21°C and about 25°C). After pre-bonding, an annealing process may be applied by, for example, heating the front side interconnect structure 120 and the carrier substrate 180 to a temperature of about 170°C.

22A-22C , after the carrier substrate 180 is bonded to the front side interconnect structure 120 , the device may be flipped so that the back side of the transistor structure 109 is facing upward. The back side of the transistor structure 109 may refer to the side opposite the front side of the transistor structure 109 .

In FIGS. 23A to 23C , a thinning process may be applied to the back side of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, CMP, etc.), an etch-back process, a combination thereof, etc. The thinning process may expose a surface of the first epitaxial material 91 opposite to the front-side interconnect structure 120. In addition, after the thinning process, a portion of the substrate 50 may remain above the gate structure (e.g., the gate electrode 102 and the gate dielectric layer 100) and the nanostructure 55. As shown in FIGS. 23A to 23C , after the thinning process, the back sides of the substrate 50, the first epitaxial material 91, the STI region 68, and the fin 66 may be flush with each other.

In FIGS. 24A to 24C , the remaining portions of the fin 66 and the substrate 50 are removed and replaced with the second dielectric layer 125. The fin 66 and the substrate 50 may be etched using a suitable etching process such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. The etching process may be an etching process that is selective to the materials of the fin 66 and the substrate 50 (e.g., etches the materials of the fin 66 and the substrate 50 at a faster rate than the materials of the STI regions 68, the gate dielectric layer 100, the epitaxial source/drain regions 92, and the first epitaxial material 91). After etching the fin 66 and the substrate 50, the surfaces of the STI regions 68, the gate dielectric layer 100, the epitaxial source/drain regions 92, and the first epitaxial material 91 may be exposed.

Then, a second dielectric layer 125 is deposited on the back side of the transistor structure 109 in the recess formed by removing the fin 66 and the substrate 50. The second dielectric layer 125 may be deposited over the STI region 68, the gate dielectric layer 100, and the epitaxial source/drain region 92. The second dielectric layer 125 may physically contact the surfaces of the STI region 68, the gate dielectric layer 100, the epitaxial source/drain region 92, and the first epitaxial material 91. The second dielectric layer 125 may be substantially similar to the second ILD 106 described above with respect to FIGS. 18A to 18C. For example, the second dielectric layer 125 may be formed of a material similar to the second ILD 106 and using a process similar to the second ILD 106. As shown in FIGS. 24A to 24C, a CMP process or the like may be used to remove the material of the second dielectric layer 125 so that the top surface of the second dielectric layer 125 is flush with the top surface of the STI region 68 and the first epitaxial material 91.

In FIGS. 25A to 25C , the first epitaxial material 91 is removed to form a fifth recess 128, and a second silicide region 129 is formed in the fifth recess 128. The first epitaxial material 91 may be removed by a suitable etching process, which may be an isotropic etching process, such as a wet etching process. The etching process may have a high etching selectivity to the material of the first epitaxial material 91. Thus, the first epitaxial material 91 may be removed without significantly removing the material of the second dielectric layer 125, the STI region 68, or the epitaxial source/drain region 92. The fifth recess 128 may expose the sidewalls of the STI region 68, the back side of the epitaxial source/drain region 92, and the sidewalls of the second dielectric layer 125.

Then, a second silicide region 129 may be formed in the fifth recess 128 on the back side of the epitaxial source/drain region 92. The second silicide region 129 may be similar to the first silicide region 110 described above with respect to FIGS. 19A to 19C. For example, the second silicide region 129 may be formed of a similar material and using a similar process as the first silicide region 110.

In FIGS. 26A to 26C , a backside via 130 is formed in the fifth recess 128. The backside via 130 may extend through the second dielectric layer 125 and the STI region 68 and may be electrically coupled to the epitaxial source/drain region 92 through the second silicide region 129. The backside via 130 may be similar to the source/drain contact 112 described above with respect to FIGS. 20A to 20C . For example, the backside via 130 may be formed of a similar material and using a similar process as the source/drain contact 112. The backside via 130 may include cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), copper (Cu), tantalum nitride (TaN), nickel (Ni), titanium silicon nitride (TiSiN), combinations thereof, and the like.

FIG26D shows a cross-sectional view along section C-C' of FIG1 of the device according to some embodiments. The embodiment of FIG26D may be similar to the embodiment described above with respect to FIGS. 26A to 26C, where the same reference numerals indicate the same elements formed using the same process. However, in FIG26D, the epitaxial source/drain region 92X electrically coupled to the backside via 130 has a height that is less than the height of the epitaxial source/drain region 92Y that is not electrically coupled to the backside via 130. In some embodiments, the epitaxial source/drain region 92X may be etched back during the formation of the fifth recess 128, as discussed above with respect to FIGS. 25A to 25C. Therefore, the epitaxial source/drain region 92X electrically coupled to the backside via 130 may have a height that is less than the height of the epitaxial source/drain region 92B that is not electrically coupled to the backside via 130. Then, second silicide regions 129 and backside vias 130 may be formed over the epitaxial source/drain regions 92A as described above.

27A to 27C , a third dielectric layer 132 is formed over the second dielectric layer 125, the STI regions 68, and the backside vias 130, and a photoresist 134 is formed and patterned over the third dielectric layer 132. The third dielectric layer 132 may include a dielectric material such as silicon carbide (SiC), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), silicon (Si), zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), yttrium oxide (YO), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), hafnium silicide (HfSi), lanthanum oxide (LaO), silicon oxide (SiO), combinations thereof, or multilayers thereof, and the like. The third dielectric layer 132 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc. The third dielectric layer 132 may have a thickness from about 1 nm to about 20 nm. The photoresist 134 may be patterned to form a sixth recess 136 that exposes a portion of the top surface of the third dielectric layer 132.

In FIGS. 28A to 28C , the pattern of the photoresist 134 is transferred to the third dielectric layer 132 using an acceptable etching process such as wet or dry etching, RIE, NBE, etc., or a combination thereof. The etching may be anisotropic. Thus, the sixth recess 136 is transferred to the third dielectric layer 132. Further in FIGS. 28A to 28C , the photoresist 134 may be removed by an acceptable process such as a wet etching process, a dry etching process, a planarization process, a combination thereof, etc.

In FIGS. 29A to 29C , a conductive layer 140 and a filling material 142 are deposited in the sixth groove 136 and over the third dielectric layer 132 to form a conductive line 143. The conductive layer 140 may be a seed layer, an adhesion layer, a barrier diffusion layer, a combination thereof, or a multilayer thereof, etc. The conductive layer 140 may be optional and may be omitted in some embodiments. The conductive layer 140 may include materials such as cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), copper (Cu), tantalum nitride (TaN), nickel (Ni), titanium silicon nitride (TiSiN), a combination thereof, etc. The conductive layer 140 may have a thickness from about 0.5 nm to about 10 nm. The conductive layer 140 may be formed using, for example, CVD, ALD, PVD, etc. The filling material 142 may include materials such as cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), copper (Cu), tantalum nitride (TaN), nickel (Ni), titanium silicon nitride (TiSiN), combinations thereof, and the like. The filling material 142 may have a thickness from about 0.5 nm to about 10 nm. The filling material 142 may be formed using, for example, CVD, ALD, PVD, plating, and the like. A planarization process (e.g., CMP, grinding, etch-back, and the like) may be performed to remove excess portions of the conductive layer 140 and the filling material 142, such as portions of the conductive layer 140 and the filling material 142 formed above the third dielectric layer 132. Thus, the top surfaces of the conductive layer 140 and the filling material 142 may be flush with the top surface of the third dielectric layer 132.

In some embodiments, the wire 143 is a power rail, which is a wire that electrically connects the epitaxial source/drain region 92 to a reference voltage, a power supply voltage, etc. Advantages can be achieved by placing the power rail on the back side of the resulting semiconductor die instead of the front side of the semiconductor die. For example, the gate density of the nano FET and/or the interconnection density of the front side interconnect structure 120 can be increased. In addition, the back side of the semiconductor die can accommodate a wider power rail, thereby reducing resistance and improving the power transmission efficiency to the nano FET. For example, the width of the wire 143 can be at least twice the width of the first level wire (e.g., the first conductive component 122) of the front side interconnect structure 120. In addition, as will be discussed in more detail below, air spacers can be formed between adjacent wires 143 in the same layer as the wire 143. The air spacers can isolate the wires 143 from each other, thereby reducing coupling capacitance. In addition, improved isolation allows the use of greater device speeds, which improves device performance.

In FIGS. 30A to 30C , an etch-back process is performed on the third dielectric layer 132. The etch-back process may have a high etch selectivity to the material of the third dielectric layer 132, so that the third dielectric layer 132 is etched without significantly removing the conductive line 143. The etch-back process may be an anisotropic dry etch process. In some embodiments, the etch-back process may include an etchant such as C ₄ H ₆ , which may be mixed with hydrogen (H ₂ ), oxygen (O ₂ ), combinations thereof, and the like. The etchant may be provided at a flow rate from about 5 sccm to about 200 sccm. The etch-back process may be performed in a chamber at a pressure from about 1 mTorr to about 100 mTorr, for a time from about 5 seconds to about 60 seconds, with a bias voltage from about 200 V to about 1,000 V, and with a plasma power from about 50 W to about 250 W. In some embodiments, after the etch-back process, a portion of the third dielectric layer 132 may remain. For example, after the etch-back process, the third dielectric layer 132 may have a thickness from about 0.5 nm to about 10 nm. In some embodiments, the etch-back process may completely remove the third dielectric layer 132 and may expose the STI region 68 and the surface of the second dielectric layer 125 .

In Figures 31A to 31C, a fourth dielectric layer 144 and a fifth dielectric layer 146 are formed over the structure of Figures 30A to 30C. The fourth dielectric layer 144 may be deposited over the back surface of the third dielectric layer 132, over the sidewall and back surface of the conductive layer 140, and over the back surface of the filling material 142. The fifth dielectric layer 146 may be deposited over the fourth dielectric layer 144. The fourth dielectric layer 144 and the fifth dielectric layer 146 may include dielectric materials such as silicon carbide (SiC), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), silicon (Si), zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), yttrium oxide (YO), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), hafnium silicide (HfSi), lanthanum oxide (LaO), silicon oxide (SiO), combinations thereof, or multiple layers thereof. The fourth dielectric layer 144 and the fifth dielectric layer 146 may be formed of different material compositions so that the fifth dielectric layer 146 may be selectively etched in a subsequent processing step. The fourth dielectric layer 144 and the fifth dielectric layer 146 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc. The respective thicknesses of the fourth dielectric layer 144 and the fifth dielectric layer 146 may each range from about 0.5 nm to about 6 nm.

In FIGS. 32A to 32C , the fifth dielectric layer 146 is etched to form a third spacer 147. The fifth dielectric layer 146 may be etched using a suitable etching process such as an anisotropic etching process (e.g., a dry etching process). The etching process may have a high etching selectivity to the material of the fifth dielectric layer 146, so that the fifth dielectric layer 146 is etched without significantly removing the material of the fourth dielectric layer 144. In some embodiments, the fifth dielectric layer 146 may include silicon dioxide (SiO ₂ ), and the fourth dielectric layer 144 may include silicon nitride (SiN), aluminum oxide (AlO _x ), silicon oxycarbide (SiOC), etc. In some embodiments, the fifth dielectric layer 146 may include silicon nitride (SiN), and the fourth dielectric layer 144 may include silicon dioxide (SiO ₂ ), aluminum oxide (AlO _x ), silicon oxycarbide (SiOC), etc. As shown in FIGS. 32B and 32C , the third spacer 147 is disposed on the sidewall of the fourth dielectric layer 144.

In some embodiments, the etching process may include an etchant such as C ₄ H ₆ , which may be mixed with hydrogen (H ₂ ), oxygen (O ₂ ), combinations thereof, and the like. The etchant may be provided at a flow rate of from about 5 sccm to about 200 sccm. The etch back process may be performed in the chamber at a pressure of from about 1 mTorr to about 100 mTorr, for a time of from about 5 seconds to about 60 seconds, with a bias voltage of from about 200 V to about 1,000 V, and with a plasma power of from about 50 W to about 250 W. After the etching process, the third spacer 147 may have a width W ₁ of from about 0.5 nm to about 6 nm, a height H ₁ of from about 1 nm to about 20 nm, and a ratio of the height H ₁ to the width W ₁ of from about 1 to about 3. Forming the third spacer 147 having a specified size allows sealing of a groove formed by subsequently removing the third spacer 147 to form an air spacer adjacent to the conductive line 143. Forming air spacers in the layer including the conductive lines 143 and between adjacent conductive lines 143 improves isolation of the conductive lines 143, which reduces coupling capacitance and allows for increased device speed.

In FIGS. 33A to 33C , a sixth dielectric layer 148 is formed over the fourth dielectric layer 144 and the third spacer 147. The sixth dielectric layer 148 may include a dielectric material such as silicon carbide (SiC), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), silicon (Si), zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), yttrium oxide (YO), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), hafnium silicide (HfSi), lanthanum oxide (LaO), silicon oxide (SiO), combinations thereof, or multiple layers thereof, etc. The sixth dielectric layer 148 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc. The sixth dielectric layer 148 may have a thickness from about 0.5 nm to about 10 nm.

34A to 34C , a seventh dielectric layer 150 is formed over the sixth dielectric layer 148, and a planarization process is performed on the seventh dielectric layer 150 and the sixth dielectric layer 148. The seventh dielectric layer 150 may include a dielectric material such as silicon carbide (SiC), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), silicon (Si), zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), yttrium oxide (YO), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), hafnium silicide (HfSi), lanthanum oxide (LaO), silicon oxide (SiO), a combination thereof, or a multilayer thereof. The seventh dielectric layer 150 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc. The seventh dielectric layer 150 may have a thickness from about 1 nm to about 20 nm. In some embodiments, the sixth dielectric layer 148 may be omitted, and the seventh dielectric layer 150 may be deposited directly on the fourth dielectric layer 144 and the third spacer 147.

The planarization process may be a process such as CMP, grinding, etch-back, etc., and may be performed to remove excess portions of the seventh dielectric layer 150 and the sixth dielectric layer 148. For example, portions of the seventh dielectric layer 150 and the sixth dielectric layer 148 are formed over a portion of the fourth dielectric layer 144 extending over the conductive line 143. Thus, the top surfaces of the seventh dielectric layer 150 and the sixth dielectric layer 148 may be flush with the top surface of the fourth dielectric layer 144.

In FIGS. 35A to 35C , the third spacer 147 is removed to form the seventh recess 152. The third spacer 147 may be removed by etching using a suitable etching process such as an isotropic etching process (e.g., a wet etching process). The etching process may have a high etching selectivity to the material of the third spacer 147, so that the third spacer 147 is removed without significantly removing the material of the seventh dielectric layer 150, the sixth dielectric layer 148, or the fourth dielectric layer 144. In some embodiments, the third spacer 147 may include silicon dioxide (SiO ₂ ), and the seventh dielectric layer 150, the sixth dielectric layer 148, and the fourth dielectric layer 144 may include a material selected from silicon nitride (SiN), aluminum oxide (AlO _x ), silicon oxycarbide (SiOC), and the like. In some embodiments, the third spacer 147 may include silicon nitride (SiN), and the seventh dielectric layer 150, the sixth dielectric layer 148, and the fourth dielectric layer 144 may include a material selected from silicon dioxide ( _SiO2 ), aluminum oxide ( _AlOx ), silicon oxycarbide (SiOC), etc. As shown in FIGS. 35B and 35C, the third spacer 147 is removed so that the seventh recess exposes the sidewalls of the sixth dielectric layer 148, the sidewalls of the fourth dielectric layer 144, and the backside of the fourth dielectric layer 144.

In some embodiments, the etching process may include an etchant such as nitrogen trifluoride (NF ₃ ), which may be mixed with hydrogen (H ₂ ), hydrogen bromide (HBr), combinations thereof, and the like. The etchant may be provided at a flow rate from about 5 sccm to about 200 sccm. The etching process may be performed in a chamber at a pressure from about 1 mTorr to about 100 mTorr, for a time from about 5 seconds to about 180 seconds, with a plasma power from about 50 W to about 250 W. After the etching process, the seventh groove 152 may have a width W ₁ from about 0.5 nm to about 6 nm, a height H ₁ from about 1 nm to about 20 nm, and an aspect ratio of the height H ₁ to the width W ₁ may be from about 1 to about 3. Forming the seventh groove 152 having a specified size allows the seventh groove 152 to be sealed to form an air spacer. Forming an air spacer in a layer including the wire 143 and between adjacent wires 143 improves isolation of the wire 143, which reduces coupling capacitance and allows for increased device speed.

In FIGS. 36A to 36C , an eighth dielectric layer 154 is formed over the seventh dielectric layer 150, the sixth dielectric layer 148, the fourth dielectric layer 144, and the seventh groove 152 and in the upper portion of the seventh groove 152, thereby sealing the seventh groove 152 and forming an air spacer 156 (also referred to as an air gap) therein. In some embodiments, the eighth dielectric layer 154 may be referred to as a sealing material. The eighth dielectric layer 154 may include a dielectric material such as silicon carbide (SiC), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), silicon (Si), zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), yttrium oxide (YO), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), hafnium silicide (HfSi), lanthanum oxide (LaO), silicon oxide (SiO), combinations thereof, or multilayers thereof, etc. The eighth dielectric layer 154 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc. The eighth dielectric layer 154 may have a thickness from about 5 nm to about 10 nm.

As shown in FIGS. 36A to 36C , the eighth dielectric layer 154 may partially extend into the seventh recess 152 (see FIGS. 35A to 35C ) to form the air spacer 156. Forming the eighth dielectric layer 154 partially extending into the seventh recess 152 provides material of the eighth dielectric layer 154 to seal the air spacer 156 even after the eighth dielectric layer 154 is subsequently planarized (see FIGS. 37A to 37C ). Forming the seventh recess 152 having the dimensions and aspect ratio described above allows the eighth dielectric layer 154 to partially extend into the seventh recess 152 without filling the seventh recess 152. Forming the seventh recess 152 having an aspect ratio below the specified range does not allow sufficient material of the eighth dielectric layer 154 to extend into the seventh recess 152, so that the air spacer 156 is not sealed by the eighth dielectric layer 154 after subsequent planarization. On the other hand, forming the seventh groove 152 having an aspect ratio greater than a specified range may allow the material of the eighth dielectric layer 154 to fill the seventh groove 152 without forming the air spacer 156. In some embodiments, the aspect ratio of the seventh groove 152 may be selected based on the material used for the eighth dielectric layer 154.

The air spacer 156 may include a gas, such as a gas used during the deposition of the eighth dielectric layer 154 or any other gas that may diffuse into the air spacer 156. The air spacer 156 may have a low dielectric constant (e.g., k value), such as a dielectric constant close to 1. The air spacer 156 may be disposed in the same layer as the conductive line 143, and may be disposed between adjacent conductive lines 143. As shown in FIGS. 36B and 36C, the fourth dielectric layer 144 may define the front and side boundaries of the air spacer 156, the sixth dielectric layer may define the side boundaries of the air spacer 156, and the eighth dielectric layer 154 may define the back boundary of the air spacer 156. As shown in FIG. 36B, the air spacer 156 may be formed along both side walls of the fourth dielectric layer 144 in the reference cross section BB', and as shown in FIG. 36C, the air spacer 156 may be formed along the third side wall of the fourth dielectric layer 144 in the reference cross section CC'. Thus, the air spacer 156 may extend along at least three sidewalls of the fourth dielectric layer 144. In some embodiments, the air spacer 156 may also extend along a fourth sidewall of the fourth dielectric layer 144 opposite to the third sidewall in the cross section CC'. As shown in FIGS. 36B and 36C, the air spacer 156 may be adjacent to the wire 143 in a direction parallel to the back surface of the STI region 68 and the second dielectric layer 125. The air spacer 156 may have a width _W2 from about 0.5 nm to about 6 nm, a height _H2 from about 0.5 nm to about 8 nm, and an aspect ratio of the height _H2 to the width _W2 may be from about 1 to about 2. Without filling the air spacer 156, the size of the air spacer 156 may depend on the size of the seventh groove 152, and may be selected so that the air spacer 156 is sealed by the eighth dielectric layer 154. In addition, the eighth dielectric layer 154 may extend into the seventh groove 152 a sufficient distance so that the air spacer 156 remains sealed after subsequent processing. Because air spacers 156 have a low dielectric constant, air spacers 156 improve isolation of conductive lines 153, thereby reducing coupling capacitance. In addition, improved isolation allows higher device speeds to be used, which improves device performance.

In FIGS. 37A to 38C , a planarization process is performed on the eighth dielectric layer 154. The planarization process may be a process such as CMP, grinding, etch-back, etc. In the embodiment shown in FIGS. 37A to 37C , the planarization process removes a portion of the eighth dielectric layer 154 so that the top surface of the eighth dielectric layer 154 is flush with the top surfaces of the seventh dielectric layer 150, the sixth dielectric layer 148, and the fourth dielectric layer 144. In the embodiment shown in FIGS. 38A to 38C , the planarization process also removes a portion of the seventh dielectric layer 150, the sixth dielectric layer 148, and the fourth dielectric layer 144. Thus, the top surfaces of the eighth dielectric layer 154, the seventh dielectric layer 150, the sixth dielectric layer 148, and the fourth dielectric layer 144 are flush with the top surface of the conductive line 143. After the planarization process, the eighth dielectric layer 154 may have a thickness from about 0.5 nm to about 5 nm.

39A to 39C , the remaining portion of the backside interconnect structure 164 is formed over the seventh dielectric layer 150, the sixth dielectric layer 148, the eighth dielectric layer 154, the fourth dielectric layer 144, and the conductive line 143. The backside interconnect structure 164 may be referred to as a backside interconnect structure because it is formed on the back side of the transistor structure 109 (e.g., the side of the transistor structure 109 opposite to the front side of the transistor structure 109). The backside interconnect structure 164 may include the conductive line 143, the third dielectric layer 132, the fourth dielectric layer 144, the sixth dielectric layer 148, the seventh dielectric layer 150, the eighth dielectric layer 154, and the air spacer 156.

The remainder of the backside interconnect structure 164 may include the same or similar materials as those used for the frontside interconnect structure 120 discussed above with respect to FIGS. 21A to 21C and may be formed using the same or similar processes as those used for the frontside interconnect structure 120 discussed above with respect to FIGS. 21A to 21C. In particular, the backside interconnect structure 164 may include a stacked layer of second conductive components 162 formed in the ninth dielectric layer 160. The second conductive components 162 may include wiring (e.g., for wiring to and from subsequently formed contact pads and external connectors). The second conductive components 162 may be further patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, and the like. The embedded passive devices may be integrated with the wires 143 (e.g., power rails) to provide circuits (e.g., power circuits) on the back side of the nanoFET.

In FIGS. 40A to 40C , a passivation layer 166, UBM 168, and external connector 170 are formed over backside interconnect structure 164. Passivation layer 166 may include a polymer such as PBO, polyimide, BCB, etc. Alternatively, passivation layer 166 may include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. Passivation layer 166 may be deposited by, for example, CVD, PVD, ALD, etc.

A UBM 168 is formed through the passivation layer 166 to the second conductive component 162 in the backside interconnect structure 164, and an external connector 170 is formed on the UBM 168. The UBM 168 may include one or more layers of copper, nickel, gold, etc. formed by a plating process, etc. An external connector 170 (e.g., a solder ball) is formed on the UBM 168. The formation of the external connector 170 may include placing a solder ball on an exposed portion of the UBM 168 and reflowing the solder ball. In some embodiments, the formation of the external connector 170 includes performing a plating step to form a solder area above the top second conductive component 162, and then reflowing the solder area. The UBM 168 and the external connector 170 can be used to provide input/output connections to other electrical components (such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc.). The UBM 168 and the external connector 170 can also be backside input/output pads, which can provide signals, power supply voltages, and/or ground connections to the nano FETs described above.

Embodiments can achieve advantages. For example, including air spacers 156 in backside interconnect structures 164 adjacent to conductive lines 143 and between adjacent conductive lines 143 isolates conductive lines 143, reduces coupling capacitance, and allows for greater device speeds to be used. This improves device performance.

According to an embodiment, a device includes: a first transistor structure; a front-side interconnect structure located on the front side of the first transistor structure; and a back-side interconnect structure located on the back side of the first transistor structure, the back-side interconnect structure including: a first dielectric layer located on the back side of the first transistor structure; a first through hole extending through the first dielectric layer, the first through hole electrically coupled to the source/drain region of the first transistor structure; a first conductive line electrically coupled to the first through hole; and an air spacer adjacent to the first conductive line in a direction parallel to the back side of the first dielectric layer. In an embodiment, the first conductive line is a power line or an electrical ground line. In an embodiment, the aspect ratio of the height of the air spacer to the width of the air spacer is from 1 to 2. In an embodiment, the back-side interconnect structure further includes: a second dielectric layer between the air spacer and the first conductive line, the second dielectric layer defining a first boundary of the air spacer and a second boundary of the air spacer perpendicular to the first boundary. In an embodiment, the back-side interconnect structure further includes: a third dielectric layer located above the second dielectric layer, the third dielectric layer defining a third boundary of the air spacer opposite to the first boundary. In an embodiment, the backside interconnect structure further comprises: a fourth dielectric layer extending from the second dielectric layer to the third dielectric layer, the fourth dielectric layer defining a fourth boundary of the air spacer opposite to the second boundary. In an embodiment, the backsides of the conductive line, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are flush with each other.

According to another embodiment, a device includes: a transistor structure; a front-side interconnect structure located on the front side of the transistor structure; and a back-side interconnect structure located on the back side of the transistor structure, the back-side interconnect structure including: a wire electrically coupled to a source/drain region of the transistor structure through a back-side via; a first dielectric layer contacting a side of the wire; and an air gap adjacent to the first dielectric layer, the side of the first dielectric layer defining a first boundary of the air gap. In an embodiment, the back side of the first dielectric layer defines a second boundary of the air gap perpendicular to the first boundary. In an embodiment, a second dielectric layer above the first dielectric layer defines a third boundary of the air gap opposite to the first boundary, and a third dielectric layer extending from the first dielectric layer to the second dielectric layer defines a fourth boundary of the air gap perpendicular to the first boundary. In an embodiment, the aspect ratio of the height of the first boundary and the third boundary to the width of the second boundary and the fourth boundary is from 1 to 2. In an embodiment, the wire is a power line or an electrical ground line. In an embodiment, the device further comprises: a second dielectric layer located above the back side of the transistor structure, the back side via extending through the second dielectric layer, and the conductive line, the first dielectric layer and the air gap located above the second dielectric layer. In an embodiment, in a cross-sectional view, the air gap is adjacent to three or more sides of the first dielectric layer.

According to yet another embodiment, the method includes: forming a first transistor on a first substrate; exposing a first epitaxial material, exposing the first epitaxial material includes thinning the back side of the first substrate; replacing the first epitaxial material with a backside via, the backside via being electrically coupled to the source/drain region of the first transistor; forming a conductive line above the backside via, the conductive line being electrically coupled to the backside via; forming a dummy spacer adjacent to the conductive line; etching the dummy spacer to form a first groove; and sealing the first groove to form an air spacer. In an embodiment, forming the dummy spacer includes: depositing a dummy spacer layer above the conductive line; and anisotropically etching the dummy spacer layer to form the dummy spacer. In an embodiment, after the anisotropic etching, the ratio of the height of the dummy spacer to the width of the dummy spacer is from 1 to 3. In an embodiment, the method also includes: forming a first dielectric layer above the conductive line, wherein the dummy spacer is formed along the sidewall of the first dielectric layer, and wherein etching the dummy spacer exposes a surface of the first dielectric layer, and the first dielectric layer defines the boundary of the air spacer. In an embodiment, the method further comprises: forming a second dielectric layer over the dummy spacer; and planarizing the first dielectric layer, the dummy spacer, and the second dielectric layer, the second dielectric layer defining other boundaries of the air spacer. In an embodiment, sealing the first groove comprises: depositing a sealing material over the first dielectric layer, the second dielectric layer, and the first groove; and planarizing the sealing material, the first dielectric layer, and the second dielectric layer.

The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and/or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims (20)

1. A semiconductor device comprising: a first transistor structure; a front side interconnect structure located on the front side of the first transistor structure; and a backside interconnect structure, located on the back side of the first transistor structure, the backside interconnect structure comprising: a first dielectric layer disposed on the back side of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; A first conductive line electrically coupled to the first through hole; and an air spacer adjacent to the first conductive line in a direction parallel to the back side of the first dielectric layer; and A second dielectric layer is disposed between the air spacer and the first conductive line, wherein the second dielectric layer defines a first boundary of the air spacer and a second boundary of the air spacer that is perpendicular to the first boundary, and the first boundary and the second boundary coincide with an upper surface of the second dielectric layer that is away from the back side of the first transistor structure. 2 . The semiconductor device according to claim 1 , wherein the first conductive line is a power supply line or an electrical ground line. 3 . The semiconductor device of claim 1 , wherein an aspect ratio of a height of the air spacer to a width of the air spacer is from 1 to 2. 4 . 4 . The semiconductor device according to claim 1 , wherein a top surface of the second dielectric layer is flush with a top surface of the first conductive line. 5 . The semiconductor device of claim 4 , wherein the backside interconnect structure further comprises: a third dielectric layer located above the second dielectric layer, the third dielectric layer defining a third boundary of the air spacer opposite to the first boundary. 6 . The semiconductor device of claim 5 , wherein the backside interconnect structure further comprises: a fourth dielectric layer extending from the second dielectric layer to the third dielectric layer, the fourth dielectric layer defining a fourth boundary of the air spacer opposite to the second boundary. 7 . The semiconductor device according to claim 6 , wherein back surfaces of the first conductive line, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are flush with each other. 8. A semiconductor device comprising: Transistor structure; a front side interconnect structure located on the front side of the transistor structure; and A backside interconnect structure, located on the back side of the transistor structure, the backside interconnect structure comprising: A conductive line electrically coupled to a source/drain region of the transistor structure through a backside via; a first dielectric layer contacting a side of the conductive line; and an air gap adjacent to the first dielectric layer, wherein a side of the first dielectric layer defines a first boundary of the air gap; and A second dielectric layer is located on the first dielectric layer, wherein the second dielectric layer defines a third boundary of the air gap opposite to the first boundary, and top surfaces of the first dielectric layer, the second dielectric layer, and the conductive line are flush with each other. 9 . The semiconductor device of claim 8 , wherein a backside of the first dielectric layer defines a second boundary of the air gap that is perpendicular to the first boundary. 10 . The semiconductor device of claim 9 , wherein a third dielectric layer extending from the first dielectric layer to the second dielectric layer defines a fourth boundary of the air gap that is perpendicular to the first boundary. 11 . The semiconductor device of claim 10 , wherein an aspect ratio of a height between the first boundary and the third boundary to a width between the second boundary and the fourth boundary is from 1 to 2. 12 . The semiconductor device according to claim 8 , wherein the conductive line is a power supply line or an electrical ground line. 13. The semiconductor device of claim 12 further comprising: a second dielectric layer located above the back side of the transistor structure, wherein the back side via extends through the second dielectric layer, and wherein the conductive line, the first dielectric layer and the air gap are located above the second dielectric layer. 14 . The semiconductor device of claim 8 , wherein the air gap is adjacent to three or more sides of the first dielectric layer. 15. A method of forming a semiconductor device, comprising: forming a first transistor on a first substrate; exposing a first epitaxial material, wherein exposing the first epitaxial material comprises thinning a back side of the first substrate; replacing the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of the first transistor; forming a conductive line above the backside through hole, the conductive line being electrically coupled to the backside through hole; forming a dummy spacer adjacent to the conductive line; etching the dummy spacer to form a first recess; and The first groove is sealed to form an air spacer. 16. The method according to claim 15, wherein forming the dummy spacer comprises: depositing a dummy spacer layer over the conductive line; and The dummy spacer layer is anisotropically etched to form the dummy spacers. 17 . The method of claim 16 , wherein after the anisotropic etching, a ratio of a height of the dummy spacer to a width of the dummy spacer is from 1 to 3. 18. The method of claim 15, further comprising: forming a first dielectric layer over the conductive line, wherein the dummy spacer is formed along a sidewall of the first dielectric layer, and wherein etching the dummy spacer exposes a surface of the first dielectric layer, the first dielectric layer defining a boundary of the air spacer. 19. The method according to claim 18, further comprising: forming a second dielectric layer over the dummy spacers; and The first dielectric layer, the dummy spacers, and the second dielectric layer are planarized, wherein the second dielectric layer defines other boundaries of the air spacers. 20. The method of claim 19, wherein sealing the first groove comprises: depositing a sealing material over the first dielectric layer, the second dielectric layer, and the first recess; and The sealing material, the first dielectric layer, and the second dielectric layer are planarized.