CN113675096B - Packaging method and packaging structure of power electronic device connected in series and overlapped mode - Google Patents

Abstract

The invention relates to a packaging method and a packaging structure of a series-stacked power electronic device, wherein a heterogeneous polycrystalline wafer-level packaging method is used for replacing the packaging mode of the traditional die bonding and wire bonding process, so that the inductance, the resistance and the thermal resistance of a connecting wire can be reduced, the size of a packaging body can be reduced, and the power density switching frequency can be improved. The wafer level package of the invention adopts more than one gallium nitride semiconductor crystal grain, more than one diode and more than one metal oxide semiconductor transistor; the shape of the packaging structure can be extended TO TO-220, quad flat no-lead packaging or other shape sizes; the low power application can use the sealing process of the traditional epoxy molding material; the high power application can use the sealing process of ceramic material. Therefore, the inductance, the electric resistance and the thermal resistance of the connecting wires can be reduced, the size of the package body is reduced, and the power density and the switching frequency are improved.

Description

Packaging method and packaging structure of series-connected power electronic devices

Technical Field

The present invention relates to a packaging method and a packaging structure of a series-stacked power electronic device, and in particular to a packaging method and a packaging structure of a series-stacked power electronic device using heterogeneous polycrystalline wafer-level packaging.

Background Art

ON Semiconductor is optimistic about the performance advantages of gallium nitride (GaN) for power applications and provides superior performance to silicon-based components. Therefore, it develops and promotes products and power system solutions based on gallium nitride, and launches 600V GaN cascode transistors NTP8G202N and NTP8G206N, targeting various high-voltage applications in the fields of industry, computers, communications, LED lighting and networks. The on-resistance of the two components NTP8G202N and NTP8G206N are 290Mω and 150mΩ respectively, the gate charge is 6.2nC, the output capacitance is 36pF and 56pF respectively, and the reverse recovery charge is 0.029μC and 0.054μC respectively. They use optimized TO-220 packages, which are easy to integrate according to customers' existing board manufacturing capabilities.

Based on the same on-resistance level, the first generation of 600V GaN-on-Si devices already provide more than 4 times the gate charge, better output charge, similar output capacitance and more than 20 times the reverse recovery charge than high-voltage silicon MOSFETs. There is still room for improvement, and the advantages of GaN will become more and more obvious in the future.

Summary of the invention

The object of the present invention is to provide a packaging method and packaging structure of a series-connected power electronic device, thereby reducing the inductance, resistance and thermal resistance of the connecting wire, reducing the size of the package body, and improving the power density and switching frequency.

To achieve the above object, the technical solution adopted by the present invention is: a packaging method for power electronic devices connected in series, the method comprising the following steps:

Take a substrate and set a pressure-sensitive adhesive layer on it;

Disposing one or more gallium nitride semiconductor crystal grains, one or more diodes and one or more metal oxide semiconductor transistors on the pressure-sensitive adhesive layer;

Coating a first photodevelopable layer on the pressure-sensitive adhesive layer, wherein the first photodevelopable layer covers the gallium nitride semiconductor grain, the diode and the metal oxide semiconductor transistor;

Expose and develop the first surface of the first photodevelopable layer on the gallium nitride semiconductor crystal grain, the diode and the metal oxide semiconductor transistor, and copper plate the exposed and developed area to form a copper plated layer;

A first plastic layer is disposed on the first photodevelopable layer, the first plastic layer covers the unexposed development area and the copper-plated layer on the first photodevelopable layer, and a heat sink is disposed on the first plastic layer;

Peeling off the substrate and the pressure-sensitive adhesive layer;

Coating a second photodevelopable layer on the second surface of the first photodevelopable layer, wherein the second photodevelopable layer covers the gallium nitride semiconductor grain, the diode and the metal oxide semiconductor transistor;

Expose and develop the second photodevelopable layer to reveal the gate and drain of the gallium nitride semiconductor crystal, the gate and source of the metal oxide semiconductor transistor, and the diode;

Forming a redistribution layer (RDL) with the gate and drain of the gallium nitride semiconductor crystal, the gate and source of the metal oxide semiconductor transistor and the diode;

Plating a protective layer on the redistribution layer;

The adhesive tape is adhered to the ceramic heat sink, the gallium nitride semiconductor grain, the diode, the metal oxide semiconductor transistor, the first plastic layer and the ceramic heat sink are cut to form a plurality of packaging modules, and the packaging modules are connected to each other only by the adhesive tape, the adhesive tape is stretched to increase the gap between the packaging modules, and the adhesive tape is removed to obtain a plurality of packaging modules, and the packaging modules are connected in series to form the power electronic device.

In the packaging method of the cascade-connected power electronic device of the present invention, the gallium nitride semiconductor crystal grain is a laterally conductive vertical structure or a horizontal structure, and has a front surface and a back surface opposite to the front surface, and the source of the gallium nitride semiconductor crystal grain is connected to the back surface through a conductive hole.

In the packaging method of the cascade-connected power electronic device of the present invention, the metal oxide semiconductor transistor and the diode are connected together by a metal oxide semiconductor process.

In the packaging method of the series-connected power electronic device of the present invention, after forming the copper plating layer and before peeling off the substrate and the pressure-sensitive adhesive layer, the first photodevelopable layer is separated into a plurality of spacing grooves, a second plastic layer is disposed on the spacing grooves, and a baffle is disposed on the second plastic layer.

The present invention also provides a packaging structure of a cascade-connected power electronic device obtained by the above method, including a plurality of cascade-connected packaging modules, each of which includes: a gallium nitride semiconductor crystal, a diode, a metal oxide semiconductor transistor, a first photosensitive developing substrate, a copper plating layer, a first plastic layer, a heat sink, a second photosensitive developing substrate, a redistribution layer, and a protective layer; wherein the gallium nitride semiconductor crystal is a lateral conduction vertical structure or a horizontal structure, the diode and the metal oxide semiconductor transistor are connected together, and there is a set distance between the gallium nitride semiconductor crystal and the diode and the metal oxide semiconductor transistor, the first photosensitive developing substrate covers the gallium nitride semiconductor crystal, the diode and the metal oxide semiconductor transistor, and a first opening is revealed by exposure and development, the copper plating layer is arranged at the first opening to connect the gallium nitride semiconductor crystal with the diode and the metal oxide semiconductor transistor, and the first plastic layer is arranged on the first surface of the copper plating layer and the first photosensitive developing substrate. In addition, the heat dissipation plate is arranged on the first plastic layer; the second photosensitive developing substrate covers the second surface of the first photosensitive developing substrate and reveals a second opening through exposure and development, the redistribution layer is arranged at the second opening, and the protective layer is arranged around the redistribution layer.

In the packaging structure of the cascade-connected power electronic device of the present invention, the heat sink is a ceramic heat sink or a metal plate.

In the packaging structure of the cascade-connected power electronic device of the present invention, the protective layer is a nickel metal layer, a copper metal layer or a nickel-copper alloy layer.

Secondly, the present invention also provides a packaging method for a series-connected power electronic device, the method comprising the following steps:

Take a substrate and set a pressure-sensitive adhesive layer on it;

Disposing one or more gallium nitride semiconductor crystal grains, one or more diodes, one or more metal oxide semiconductor transistors and one or more metal blocks on the pressure-sensitive adhesive layer;

Coating a first photodevelopable layer on the pressure-sensitive adhesive layer, wherein the first photodevelopable layer covers the gallium nitride semiconductor grain, the diode, the metal oxide semiconductor transistor and the metal block;

Expose and develop the first surface of the first photodevelopable layer on the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor, the diode and the metal block, and copper plate the exposed and developed area to form a copper plated layer;

A first plastic layer is arranged on the first photodevelopable layer, the first plastic layer covers the unexposed development area and the copper-plated layer on the first photodevelopable layer, and a ceramic heat sink is arranged on the first plastic layer;

Peeling off the substrate and the pressure-sensitive adhesive layer;

Coating a second photodevelopable layer on the second surface of the first photodevelopable layer, wherein the second photodevelopable layer covers the gallium nitride semiconductor grain, the diode, the metal oxide semiconductor transistor and the metal block;

Expose and develop the second photodevelopable layer to reveal the drain of the gallium nitride semiconductor crystal, the gate and source of the metal oxide semiconductor transistor, the diode and the metal block; and plate the exposed area with metal to form a metal layer;

coating the metal layer with a protective layer;

The adhesive tape is adhered to the ceramic heat sink, the gallium nitride semiconductor crystal, the diode, the metal oxide semiconductor transistor, the metal block, the first plastic layer and the ceramic heat sink are cut to form a plurality of packaging modules, and the packaging modules are connected to each other only by the adhesive tape, the adhesive tape is stretched to increase the gap between the packaging modules, and the adhesive tape is removed to obtain a plurality of packaging modules, and the packaging modules are connected in series to form the power electronic device.

In the packaging method of the cascade-connected power electronic device of the present invention, the gallium nitride semiconductor crystal grain is a laterally conductive vertical structure or a horizontal structure, and has a front surface and a back surface opposite to the front surface, and the drain of the gallium nitride semiconductor crystal grain is connected to the back surface through a conductive hole.

In the packaging method of the aforementioned power electronic device connected in series of the present invention, the metal oxide semiconductor transistor and the diode are connected together by a metal oxide semiconductor process. The present invention also provides a packaging structure of the power electronic device connected in series obtained by the aforementioned method, including a plurality of arrays of packaging modules connected in series, each packaging module including: a gallium nitride semiconductor crystal, a diode, a metal oxide semiconductor transistor, a metal block, a first photosensitive developing substrate, a copper plating layer, a first plastic layer, a heat sink, a second photosensitive developing substrate, a redistribution layer and a protective layer; wherein the gallium nitride semiconductor crystal is a laterally conductive vertical structure or a horizontal structure, and the diode is connected to the metal oxide semiconductor transistor, and there is a set distance between the gallium nitride semiconductor crystal and the diode and the metal oxide semiconductor transistor, and between the gallium nitride semiconductor crystal and the metal block, and the first photosensitive developing substrate covers The invention relates to a gallium nitride semiconductor crystal, a diode, a metal oxide semiconductor transistor and a metal block, and the first photosensitive developing substrate is exposed to a first opening through exposure and development, the copper plating layer is arranged at the first opening to connect the gallium nitride semiconductor crystal and the metal block, and the gallium nitride semiconductor crystal and the diode and the metal oxide semiconductor transistor, the first plastic layer is arranged on the copper plating layer and the first surface of the first photosensitive developing substrate, the heat sink is arranged on the first plastic layer, the second photosensitive developing substrate is covered on the second surface of the first photosensitive developing substrate, and the second photosensitive developing substrate is exposed to a second opening through exposure and development, the redistribution layer is arranged on the second openings, and the protective layer is arranged around the redistribution layers.

According to the above advantages and for a further understanding of the present invention, the preferred implementation modes are disclosed as follows. The components of the present invention and the effects achieved are described in detail with reference to the drawings and figure numbers.

BRIEF DESCRIPTION OF THE DRAWINGS

1a to 1j are structural diagrams of packaging steps of a power electronic device according to Embodiment 1 of the present invention;

FIG2a is a schematic top view of a gallium nitride semiconductor crystal grain according to Example 1 of the present invention;

FIG2 b is a side view of a gallium nitride semiconductor crystal grain according to Example 1 of the present invention;

FIG3 a is a three-dimensional schematic diagram of a metal oxide semiconductor transistor and a diode according to Embodiment 1 of the present invention;

FIG3 b is a schematic side view of a metal oxide semiconductor transistor and a diode according to Embodiment 1 of the present invention;

FIG4 is a schematic diagram of the structure of a power electronic device according to Embodiment 1 of the present invention;

FIG5 a is a three-dimensional schematic diagram of a metal oxide semiconductor transistor and a diode according to Embodiment 2 of the present invention;

FIG5 b is a schematic side view of a metal oxide semiconductor transistor and a diode according to Embodiment 2 of the present invention;

FIG6 is a schematic diagram of the structure of a power electronic device according to Embodiment 2 of the present invention;

7a to 7j are structural diagrams of packaging steps of a power electronic device according to Embodiment 3 of the present invention;

FIG8 a is a top view of a gallium nitride semiconductor grain in Example 3 of the present invention;

FIG8 b is a side view of a gallium nitride semiconductor grain in Example 3 of the present invention;

FIG9 is a schematic diagram of the structure of a power electronic device according to Embodiment 3 of the present invention;

FIG10 is a schematic diagram of the structure of a power electronic device according to Embodiment 4 of the present invention;

FIG11a is a schematic side view of a metal oxide semiconductor transistor and a diode according to Embodiment 5 of the present invention;

FIG. 11 b is a schematic top view of a metal oxide semiconductor transistor and a diode according to Embodiment 5 of the present invention;

FIG. 11 c is a schematic top view of a gallium nitride semiconductor crystal, a metal oxide semiconductor transistor and a diode according to Embodiment 5 of the present invention;

FIG12 is a schematic top view of a gallium nitride semiconductor crystal, a metal oxide semiconductor transistor and a diode according to Embodiment 6 of the present invention;

13a to 131 are structural diagrams of packaging steps of a power electronic device according to Embodiment 7 of the present invention;

FIG14 is a schematic diagram of the structure of a power electronic device according to an eighth embodiment of the present invention.

Description of labels:

1 Power Electronic Devices 1’ Package Module

10GaN semiconductor die 101Gate

102 drain 103 source

11 diode 12 metal oxide semiconductor transistor

121 Gate 122 Drain

123 source 20 substrate

21 pressure-sensitive adhesive layer 22 first photosensitive developing substrate

221 first surface 222 second surface

223 first opening 224 spacing groove

23 copper plating layer 225 second plastic layer

226 baffle 24 first plastic layer

25 heat sink 26 second photosensitive developing substrate

261 second opening 27 redistribution layer

27’ Metal layer 28 Protective layer

29 tape.

DETAILED DESCRIPTION

The following specific embodiments are used to illustrate the implementation of the present invention. A person skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. In addition, the present invention can also be implemented or applied through other different specific embodiments, and various modifications and changes can be made without departing from the spirit of the present invention.

Please refer to FIG. 1a to FIG. 1j , which are structural diagrams of packaging steps of a power electronic device according to Embodiment 1 of the present invention.

As shown in FIG. 1a to FIG. 1j, the present invention provides a packaging method for a series-connected power electronic device, the method comprising the following steps:

Take a substrate 20, and set a pressure-sensitive adhesive layer 21 thereon, and set more than one laterally conductive vertical structure gallium nitride semiconductor grain 10, more than one diode 11 and more than one metal oxide semiconductor transistor 12 on the pressure-sensitive adhesive layer 21, as shown in FIG. 1a;

A first photodevelopable layer 22 is coated on the pressure-sensitive adhesive layer 21, and the first photodevelopable layer 22 covers the laterally conductive vertically structured gallium nitride semiconductor grains 10, the diode 11 and the metal oxide semiconductor transistor 12, as shown in FIG. 1b;

A first surface 221 of the first photodevelopable layer 22 on the laterally conductive vertical structure gallium nitride semiconductor grain 10, the diode 11 and the metal oxide semiconductor transistor 12 is exposed and developed (see FIG. 1c ), and the exposed and developed area is copper plated to form a copper plated layer 23 , as shown in FIG. 1d ;

A first plastic layer 24 is disposed on the first photodevelopable layer 22, and the first plastic layer 24 covers the unexposed development area and the copper-plated layer 23 on the first photodevelopable layer 22, and a heat sink 25 is disposed on the first plastic layer 24, wherein the heat sink 25 is a ceramic heat sink or a metal plate, as shown in FIG. 1e;

The substrate 20 and the pressure-sensitive adhesive layer 21 are peeled off, as shown in FIG. 1f ;

A second photodevelopment layer 26 is coated on a second surface 222 of the first photodevelopment layer 22, and the second photodevelopment layer 26 covers the laterally conductive vertical structure gallium nitride semiconductor grain 10, the diode 11 and the metal oxide semiconductor transistor 12; the second photodevelopment layer 26 is exposed and developed to reveal the gate 101 and the drain 102 of the laterally conductive vertical structure gallium nitride semiconductor grain 10, the gate 121 and the source 123 of the metal oxide semiconductor transistor 12 and the diode 11, as shown in FIG. 1g;

The gate 101 and drain 102 of the laterally conductive vertical structured gallium nitride semiconductor grain 10, the gate 121 and source 123 of the metal oxide semiconductor transistor 12, and the diode 11 form a redistribution layer 27 (RDL, redistribution layer), as shown in FIG1h;

The redistribution layer 27 is plated with a protective layer 28, wherein the protective layer 28 is a nickel metal layer, a copper metal layer or a nickel-copper alloy layer, as shown in FIG. 1i;

The tape 29 is pasted on the ceramic heat sink 25, and the gallium nitride semiconductor grains 10 of the laterally conductive vertical structure, the metal oxide semiconductor transistor 12, the diode 11, the first plastic layer 24 and the ceramic heat sink 25 are cut to form a plurality of packaging modules 1', and the packaging modules 1' are connected to each other only by the tape 29, and the tape 29 is stretched to increase the gaps between the packaging modules 1', and the tape 29 is removed to obtain a plurality of packaging modules 1', and the packaging modules 1' are connected in series to form a power electronic device (see Figure 4 in combination), as shown in Figure 1j.

Please refer to Figures 2a to 3b, Figure 2a is a top view schematic diagram of the gallium nitride semiconductor crystal grain according to Example 1 of the present invention; Figure 2b is a side view schematic diagram of the gallium nitride semiconductor crystal grain according to Example 1 of the present invention; Figure 3a is a three-dimensional schematic diagram of the metal oxide semiconductor transistor and the diode according to Example 1 of the present invention; Figure 3b is a side view schematic diagram of the metal oxide semiconductor transistor and the diode according to Example 1 of the present invention.

As shown in Fig. 2a and Fig. 2b, the GaN semiconductor crystal grain 10 of the lateral conduction vertical structure of the first embodiment of the present invention has a gate 101, a drain 102, a source 103 and a via 104, and the GaN semiconductor crystal grain 10 of the lateral conduction vertical structure has a front surface 105 and a back surface 106 opposite to the front surface 105, and the source 103 of the GaN semiconductor crystal grain 10 of the lateral conduction vertical structure is connected to the back surface 106 through the via 104. As shown in Fig. 3a and Fig. 3b, the diode 11 is connected to the MOS transistor 12 by a MOS process to form the gate 101', the drain 102' and the source 103'.

Please refer to FIG. 4 , which is a schematic diagram of the structure of a power electronic device according to Embodiment 1 of the present invention.

As shown in FIG. 4 , the present invention provides a packaging structure of a cascade-connected power electronic device, including a plurality of cascade-connected packaging modules 1′, each of which includes: a gallium nitride semiconductor crystal grain 10 of a transversely conductive vertical structure, a diode 11, a metal oxide semiconductor transistor 12, a first photosensitive developing substrate 22, a copper plating layer 23, a first plastic layer 24, a heat sink 25, a second photosensitive developing substrate 26, a redistribution layer 27, and a protective layer 28; wherein the diode 11 and the metal oxide semiconductor transistor 12 are connected together, and a set distance is provided between the gallium nitride semiconductor crystal grain 10 of the transversely conductive vertical structure and the diode 11 and the metal oxide semiconductor transistor 12. The first photosensitive developing substrate 22 covers the gallium nitride semiconductor grain 10, the diode 11 and the metal oxide semiconductor transistor 12 of the lateral conductive vertical structure, and a first opening 223 is revealed by exposure and development (see FIG. 1c in combination). The copper plating layer 23 is arranged at the first opening 223 to connect the gallium nitride semiconductor grain 10 with the diode 11 and the metal oxide semiconductor transistor 12. The first plastic layer 24 is arranged on the copper plating layer 23 and the first surface 221 of the first photosensitive developing substrate 22. In addition, the heat sink 25 is arranged on the first plastic layer 24; the second photosensitive developing substrate 26 covers the second surface 222 of the first photosensitive developing substrate 22, and a second opening 261 is revealed by exposure and development (see FIG. 1g in combination). The redistribution layer 27 is arranged at the second opening 261, and the protective layer 28 is arranged around the redistribution layer 27.

Please refer to Figures 5a to 6, Figure 5a is a three-dimensional schematic diagram of the metal oxide semiconductor transistor and the diode of Example 2 of the present invention; Figure 5b is a side schematic diagram of the metal oxide semiconductor transistor and the diode of Example 2 of the present invention; and Figure 6 is a structural schematic diagram of the power electronic device of Example 2 of the present invention.

As shown in FIGS. 5a and 5b , in Embodiment 2, unlike Embodiment 1 in which the diode 11 and the MOS transistor 12 are connected together by a MOS process, in Embodiment 2, the diode 11 and the MOS transistor 12 are separated from each other. As shown in FIG. 6 , the diode 11 and the MOS transistor 12 are separated from each other, and the GaN semiconductor grain 10, the diode 11 and the MOS transistor 12 of the lateral conduction vertical structure are connected together by the metal layer 23 .

Please refer to FIG. 7 a to FIG. 7 j , which are structural diagrams of packaging steps of a power electronic device according to Embodiment 3 of the present invention.

As shown in FIG. 7a to FIG. 7j, the present invention further provides a packaging method for a series-connected power electronic device, the method comprising the following steps:

Take a substrate 20 and set a pressure-sensitive adhesive layer 21 thereon;

On the pressure-sensitive adhesive layer 21, one or more gallium nitride semiconductor grains 10 with a lateral conduction vertical structure, one or more diodes 11, one or more metal oxide semiconductor transistors 12 and one or more metal blocks 13 are disposed, as shown in FIG. 7a;

A first photodevelopable layer 22 is coated on the pressure-sensitive adhesive layer 21, and the first photodevelopable layer 22 covers the gallium nitride semiconductor grain 10 of the transversely conductive vertical structure, the diode 11, the metal oxide semiconductor transistor 12 and the metal block 13, as shown in FIG. 7b;

The first surface 221 of the first photodevelopable layer 22 on the laterally conductive vertical structure gallium nitride semiconductor grain 10, the diode 11, the metal oxide semiconductor transistor 12 and the metal block 13 is exposed and developed (see FIG. 7 c ), and the exposed and developed area is copper plated to form a copper plated layer 23 , as shown in FIG. 7 d ;

A first plastic layer 24 is disposed on the first photodevelopable layer 22, the first plastic layer 24 covers the unexposed developing area and the copper-plated layer 23 on the first photodevelopable layer 22, and a ceramic heat sink 25 is disposed on the first plastic layer 24, as shown in FIG. 7e;

The substrate 20 and the pressure-sensitive adhesive layer 21 are peeled off, as shown in FIG. 7 f ;

A second photodevelopment layer 26 is coated on the second surface 222 of the first photodevelopment layer 22, and the second photodevelopment layer 26 covers the gallium nitride semiconductor crystal grain 10 of the laterally conductive vertical structure, the diode 11, the metal oxide semiconductor transistor 12 and the metal block 13; the second photodevelopment layer 26 is exposed and developed for a second time to reveal the drain 102 of the gallium nitride semiconductor crystal grain 10 of the laterally conductive vertical structure, the gate 121 and the source 123 of the metal oxide semiconductor transistor 12, the diode 11 and the metal block 13, as shown in FIG. 7g;

The drain 102 of the laterally conductive vertical structured GaN semiconductor grain 10, the gate 121 and source 123 of the metal oxide semiconductor transistor 12, the diode 11 and the metal block 13 are plated with metal to form a metal layer 27', as shown in FIG7h;

The metal layer 27' is plated with a protective layer 28, as shown in FIG7i;

As shown in FIG7j, the adhesive tape 29 is pasted on the ceramic heat sink 25, and the gallium nitride semiconductor grains 10, the diode 11, the metal oxide semiconductor transistor 12, the metal block 13, the first plastic layer 24 and the ceramic heat sink 25 of the transverse conduction vertical structure are cut to form a plurality of packaging modules 1', and the packaging modules 1' are connected to each other only by the adhesive tape 29, and the adhesive tape 29 is stretched to increase the gaps between the packaging modules 1', and the adhesive tape 29 is removed to obtain a plurality of packaging modules 1', and the packaging modules 1' are connected in series to form the power electronic device (see FIG9).

Please refer to Figures 8a to 9, Figure 8a is a top view of the gallium nitride semiconductor grain in Example 3 of the present invention; Figure 8b is a side schematic view of the gallium nitride semiconductor grain in Example 3 of the present invention; Figure 9 is a structural schematic view of the power electronic device in Example 3 of the present invention.

As shown in FIG. 8 a and FIG. 8 b , in the third embodiment of the present invention, except for the structure of the laterally conductive vertically connected gallium nitride semiconductor crystal grain 10, the rest of the structures are the same as those of the first embodiment. The laterally conductive vertically connected gallium nitride semiconductor crystal grain 10 has a front surface 105 and a back surface 106 opposite to the front surface 105 , and a drain 102 of the laterally conductive vertically connected gallium nitride semiconductor crystal grain 10 is connected to the back surface 106 via a via hole 104 .

As shown in FIG9 , in the third embodiment of the present invention, the packaging structure of the power electronic device 1 connected in series comprises a plurality of arrays of packaging modules 1′ connected in series, each of which comprises: a gallium nitride semiconductor crystal grain 10 with a transverse conduction vertical structure, a diode 11, a metal oxide semiconductor transistor 12, a metal block 13, a first photosensitive developing substrate 22, a copper plating layer 23, a first plastic layer 24, a heat sink 25, a second photosensitive developing substrate 26, a redistribution layer 27 and a protective layer 28; wherein the diode 11 and the metal oxide semiconductor transistor 12 are connected together, and there is a set distance between the gallium nitride semiconductor crystal grain 10 with a transverse conduction vertical structure and the diode 11 and the metal oxide semiconductor transistor 12, and between the gallium nitride semiconductor crystal grain 10 and the metal block 13. The first photosensitive developing substrate 22 covers the gallium nitride semiconductor crystal grain 10, the diode 11, the metal oxide semiconductor transistor 12 and the metal block 13 of the laterally conductive vertical structure, and the first photosensitive developing substrate 22 is exposed to reveal a first opening 223 by exposure and development (see FIG. 7 c ). The copper plating layer 23 is arranged at the first opening 223 to connect the gallium nitride semiconductor crystal grain 10 with the metal block 13 and the gallium nitride semiconductor crystal grain 10 with the diode 11 and the metal oxide semiconductor transistor 12. The first plastic layer 24 is arranged on the copper plating layer 23 and the first surface 221 of the first photosensitive developing substrate 22. The heat sink 25 is arranged on the first plastic layer 24. The second photosensitive developing substrate 26 covers the second surface 222 of the first photosensitive developing substrate 22, and the second photosensitive developing substrate 26 is exposed to reveal a second opening 261 by exposure and development (see FIG. 7 g ). In addition, the redistribution layer 27 is disposed on the second openings 261 , and the protection layer 28 is disposed around the redistribution layer 27 .

Please refer to FIG. 10 , which is a schematic diagram of the structure of a power electronic device according to a fourth embodiment of the present invention.

As shown in FIG10 , unlike the third embodiment in which the MOS transistor 12 and the diode 11 are connected together by a MOS process, in the fourth embodiment, the diode 11 and the MOS transistor 12 are separated from each other. As shown in FIG10 , the diode 11 and the MOS transistor 12 are separated from each other, and the gallium nitride semiconductor grain 10, the diode 11, the MOS transistor 12 and the gold block 13 of the lateral conduction vertical structure are connected together by the metal layer 23 .

Please refer to Figures 11a to 11c, Figure 11a is a side schematic diagram of the metal oxide semiconductor transistor and the diode of Example 5 of the present invention; Figure 11b is a top schematic diagram of the metal oxide semiconductor transistor and the diode of Example 5 of the present invention; and Figure 11c is a top schematic diagram of the gallium nitride semiconductor grain, the metal oxide semiconductor transistor and the diode of Example 5 of the present invention.

As shown in FIG. 11a to FIG. 11c, except that the embodiment 5 includes two laterally conductive vertical gallium nitride semiconductor grains 10, two diodes 11 and two metal oxide semiconductor transistors 12, the rest is the same as the embodiment 1. In the embodiment 5, the diode 11 and the metal oxide semiconductor transistor 12 have a first gate G1 and a second gate G2, a first drain D1 and a second drain D2, and a first source S1 and a second source S2. As can be seen from FIG. 11c, the two laterally conductive vertical gallium nitride semiconductor grains 10 are arranged in parallel with the two diodes 11 and the two metal oxide semiconductor transistors 12, so the two laterally conductive vertical gallium nitride semiconductor grains 10 cannot be seen in FIG. 11a.

Please refer to FIG. 12 , which is a schematic top view of a gallium nitride semiconductor crystal, a metal oxide semiconductor transistor, and a diode according to a sixth embodiment of the present invention.

As shown in FIG. 12 , the sixth embodiment is the same as the first embodiment except that it includes four laterally conductive vertical gallium nitride semiconductor grains 10 , four diodes 11 and four metal oxide semiconductor transistors 12 .

Please refer to FIG. 13 a to FIG. 13 l , which are structural diagrams of packaging steps of a power electronic device according to Embodiment 7 of the present invention.

As shown in FIG. 13a to FIG. 13l , the present invention provides another packaging method for a series-connected power electronic device, the method comprising the following steps:

Take a substrate 20 and set a pressure-sensitive adhesive layer 21 thereon;

On the pressure-sensitive adhesive layer 21, one or more gallium nitride semiconductor grains 10 with a lateral conduction vertical structure, one or more diodes 11 and one or more metal oxide semiconductor transistors 12 are disposed, as shown in FIG. 13a ;

A first photodevelopable layer 22 is coated on the pressure-sensitive adhesive layer 21, and the first photodevelopable layer 22 covers the gallium nitride semiconductor grain 10, the diode 11 and the metal oxide semiconductor transistor 12 of the lateral conductive vertical structure, as shown in FIG13b;

The first surface 221 of the first photodevelopable layer 22 on the laterally conductive vertical structure gallium nitride semiconductor grain 10, the diode 11 and the metal oxide semiconductor transistor 12 is exposed and developed (see FIG. 13 c ), and the exposed and developed area is copper plated to form a copper plated layer 23 , as shown in FIG. 13 d ;

The first photodevelopable layer 22 is separated into a plurality of spacing grooves 224, as shown in FIG. 13e;

A second plastic layer 225 is disposed on the spacing grooves 224, and a baffle 226 is disposed on the second plastic layer 225, as shown in FIG. 13f;

The substrate 20 and the pressure-sensitive adhesive layer 21 are peeled off, as shown in FIG. 13g ;

A second photodevelopment layer 26 is coated on the second surface 222 of the first photodevelopment layer 22, and the second photodevelopment layer 26 covers the gallium nitride semiconductor grain 10, the diode 11 and the metal oxide semiconductor transistor 12 of the lateral conductive vertical structure, as shown in FIG13h;

The second photodevelopment layer 26 is exposed and developed to reveal the gate 101 and drain 102 of the laterally conductive vertical structure gallium nitride semiconductor grain 10, the gate 121 of the metal oxide semiconductor transistor 12 and the diode 11, as shown in FIG13i;

The gate 101 and drain 102 of the laterally conductive vertical structured gallium nitride semiconductor grain 10, the gate 121 of the metal oxide semiconductor transistor 12 and the diode 11 form a redistribution layer 27, as shown in FIG13j;

The redistribution layer 27 is plated with a protective layer 28, as shown in FIG13k;

The tape 29 is pasted on the baffle 226, and the gallium nitride semiconductor grain 10, the diode 11, the metal oxide semiconductor transistor 12 and the second plastic layer 225 of the laterally conductive vertical structure are cut to form a plurality of packaging modules 1', and the packaging modules 1' are connected to each other only by the tape 29, and the tape 29 is stretched to increase the gap between the packaging modules 1', and the tape 29 is removed to obtain a plurality of packaging modules 1' (see FIG. 13l), and the packaging modules 1' are connected in series to form a power electronic device 1.

Please refer to FIG. 14 , which is a schematic diagram of the structure of a power electronic device according to an eighth embodiment of the present invention.

As shown in FIG14 , the packaging structure of the power electronic device 1 of the eighth embodiment includes a plurality of packaging modules 1′ connected in series, each of which includes: a horizontally structured gallium nitride semiconductor crystal 10′, a diode 11, a metal oxide semiconductor transistor 12, a first photosensitive developing substrate 22, a copper plating layer 23, a second photosensitive developing substrate 26, a redistribution layer 27, a protective layer 28, and a separator 30; wherein the diode 11 and the metal oxide semiconductor transistor 12 are connected together, the horizontally structured gallium nitride semiconductor crystal 10′ and the metal oxide semiconductor transistor 12 are disposed on a lead frame 201 by a solder paste 105, and the separator 30 is disposed on both sides of the horizontally structured gallium nitride semiconductor crystal 10′ and the metal oxide semiconductor transistor 12. The first photosensitive developing substrate 22 covers the horizontally structured gallium nitride semiconductor crystal 10′, the diode 11, the metal oxide semiconductor transistor 12, and the separator 30, and a first opening 223 is exposed through exposure and development. The copper plating layer 23 is disposed at the first opening 223 to connect the horizontal structured gallium nitride semiconductor grain 10' with the metal oxide semiconductor transistor 12 and the separator 30. The second photosensitive developing substrate 26 covers the first photosensitive developing substrate 22 and the copper plating layer 23, and a second opening 261 is exposed through exposure and development. The redistribution layer 27 is disposed on the second opening 261, and the protection layer 28 is disposed around the redistribution layer 27.

The above embodiments are merely examples for the convenience of explanation. The scope of rights claimed by the present invention shall be based on the scope of the patent application, and shall not be limited to the above embodiments.

Claims (10)

1. A method of packaging a series-connected power electronic device, the method comprising the steps of:

taking a substrate, and arranging a pressure sensitive adhesive layer on the substrate;

more than one gallium nitride semiconductor crystal grain, more than one metal oxide semiconductor transistor and more than one diode are arranged on the pressure sensing adhesive layer;

Coating a first photo-developing layer on the pressure-sensitive adhesive layer, wherein the first photo-developing layer covers the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor and the diode;

exposing and developing the first surface of the first photo-developing layer on the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor and the diode, and plating copper on the exposed and developed area to form a copper plating layer;

arranging a first plastic layer on the first photo-development layer, wherein the first plastic layer covers the unexposed development area and the copper plating layer on the first photo-development layer, and arranging a heat dissipation plate on the first plastic layer;

Peeling the substrate and the pressure sensitive adhesive layer;

coating a second photo-developing layer on the second surface of the first photo-developing layer, wherein the second photo-developing layer covers the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor and the diode;

performing a second exposure and development on the second photo-development layer to expose the gate and drain of the GaN semiconductor die, the gate and source of the MOS transistor, and the diode;

Forming a redistribution layer on the gate and drain of the GaN semiconductor die, the gate and source of the MOS transistor, and the diode;

plating the redistribution layer with a protective layer;

And sticking an adhesive tape on the ceramic heat dissipation plate, cutting the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor, the diode, the first plastic layer and the ceramic heat dissipation plate to form a plurality of packaging modules, connecting the packaging modules with each other only through the adhesive tape, stretching the adhesive tape to increase gaps among the packaging modules, removing the adhesive tape to obtain a plurality of packaging modules, and connecting the packaging modules in a serial manner to form the power electronic device.

2. The method of claim 1, wherein the gan semiconductor die has a lateral through vertical structure or a horizontal structure, and has a front surface and a back surface opposite to the front surface, and the source of the gan semiconductor die is connected to the back surface by a via.

3. A method of packaging a series-connected power electronic device as recited in claim 1, the MOS transistor is connected with the diode by a MOS process.

4. The method of claim 1, wherein after the copper plating is formed and before the substrate and the pressure sensitive adhesive layer are peeled off, the first photo-developing layer is separated by a plurality of spacer grooves, a second plastic layer is disposed on the spacer grooves, and a barrier is disposed on the second plastic layer.

5. The utility model provides a package structure of power electronic device of tandem connection, includes the encapsulation module of plural array tandem connection, its characterized in that: each package module includes: gallium nitride semiconductor crystal grains, a diode, a metal oxide semiconductor transistor, a first photosensitive development substrate, a copper plating layer, a first plastic layer, a heat dissipation plate, a second photosensitive development substrate, a redistribution layer and a protection layer;

The semiconductor crystal grain of the gallium nitride is of a transverse conduction vertical structure or a horizontal structure, the diode and the metal oxide semiconductor transistor are connected together, a set distance is reserved between the semiconductor crystal grain of the gallium nitride and the diode and between the semiconductor crystal grain of the gallium nitride and the metal oxide semiconductor transistor, the first photosensitive developing substrate covers the semiconductor crystal grain of the gallium nitride, the diode and the metal oxide semiconductor transistor, a first opening is exposed through exposure and development, the copper plating layer is arranged at the first opening, the semiconductor crystal grain of the gallium nitride is connected with the diode and the metal oxide semiconductor transistor, and the first plastic layer is arranged on the copper plating layer and the first surface of the first photosensitive developing substrate; the heat dissipation plate is arranged on the first plastic layer; the second photosensitive development substrate is covered on the second surface of the first photosensitive development substrate, a second opening is exposed through exposure and development, the redistribution layer is arranged at the second opening, and the protection layer is arranged around the redistribution layer.

6. The package structure of power electronic device according to claim 5, wherein the heat dissipation plate is a ceramic heat dissipation plate or a metal plate, and the protection layer is a nickel metal layer, a copper metal layer, or a nickel-copper alloy layer.

7. A method of packaging a series-connected power electronic device, the method comprising the steps of:

taking a substrate, and arranging a pressure sensitive adhesive layer on the substrate;

more than one gallium nitride semiconductor crystal grain, more than one metal oxide semiconductor transistor, more than one diode and more than one metal block are arranged on the pressure sensing adhesive layer;

coating a first photo-developing layer on the pressure-sensitive adhesive layer, wherein the first photo-developing layer covers the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor, the diode and the metal block;

exposing and developing the first surface of the first photo-developing layer on the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor, the diode and the metal block, and plating copper on the exposed and developed area to form a copper plating layer;

arranging a first plastic layer on the first photo-development layer, wherein the first plastic layer covers an unexposed development area and a copper plating layer on the first photo-development layer, and arranging a ceramic heat dissipation plate on the first plastic layer;

Peeling the substrate and the pressure sensitive adhesive layer;

Coating a second photo-developing layer on the second surface of the first photo-developing layer, wherein the second photo-developing layer covers the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor, the diode and the metal block;

Exposing and developing the second photo-developing layer to expose the drain of the GaN semiconductor die, the gate and source of the MOS transistor, the diode and the metal block; plating metal on the exposed area after exposure and development to form a metal layer;

Plating a protective layer on the metal layer;

And sticking an adhesive tape on the ceramic heat dissipation plate, cutting the gallium nitride semiconductor crystal grain, the metal oxide semiconductor transistor, the diode, the metal block, the first plastic layer and the ceramic heat dissipation plate to form a plurality of packaging modules, connecting the packaging modules with each other only through the adhesive tape, stretching the adhesive tape to increase gaps among the packaging modules, removing the adhesive tape to obtain a plurality of packaging modules, and connecting the packaging modules in a serial manner to form the power electronic device.

8. The method of claim 7, wherein the gan semiconductor die has a lateral through vertical structure or a horizontal structure, and has a front surface and a back surface opposite to the front surface, and the drain of the gan semiconductor die is connected to the back surface through a via hole.

9. A method of packaging a series-connected power electronic device as recited in claim 7, the MOS transistor is connected with the diode through a MOS process.

10. The utility model provides a package structure of power electronic device of tandem connection, includes the encapsulation module of plural array tandem connection, its characterized in that: each package module includes: gallium nitride semiconductor crystal grains, a diode, a metal oxide semiconductor transistor, a metal block, a first photosensitive development substrate, a copper plating layer, a first plastic layer, a heat radiation plate, a second photosensitive development substrate, a redistribution layer and a protective layer;

The semiconductor crystal grain is of a transverse conduction vertical structure or a horizontal structure, the diode is connected with the metal oxide semiconductor transistor, a set distance is reserved between the semiconductor crystal grain and the diode as well as between the semiconductor crystal grain and the metal block, the first photosensitive developing substrate covers the semiconductor crystal grain, the diode, the metal oxide semiconductor transistor and the metal block, a first opening is exposed on the first photosensitive developing substrate through exposure and development, the copper plating layer is arranged at the first opening to connect the semiconductor crystal grain and the metal block as well as the semiconductor crystal grain and the diode as well as the metal oxide semiconductor transistor, the first plastic layer is arranged on the copper plating layer and the first surface of the first photosensitive developing substrate, the second photosensitive developing substrate covers the second surface of the first photosensitive developing substrate, the second photosensitive developing substrate is exposed with a second opening through exposure and development, the copper plating layer is arranged at the first opening to connect the semiconductor crystal grain and the metal block, and the semiconductor crystal grain and the metal oxide semiconductor transistor are arranged on the first plastic layer, the second photosensitive developing substrate covers the second surface of the first photosensitive developing substrate, and the second photosensitive developing substrate is arranged on the second opening to surround the redistribution layer.