CN113672026B - MIPI's biasing circuit, MIPI module and display device - Google Patents
MIPI's biasing circuit, MIPI module and display device Download PDFInfo
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- CN113672026B CN113672026B CN202110944667.7A CN202110944667A CN113672026B CN 113672026 B CN113672026 B CN 113672026B CN 202110944667 A CN202110944667 A CN 202110944667A CN 113672026 B CN113672026 B CN 113672026B
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The application discloses MIPI's biasing circuit is connected with the signal amplification module of MIPI module, and the circuit includes: the circuit comprises a reference current output unit, a current mirror unit, a fine adjustment unit and a bias current output unit; the reference current output unit is respectively connected with the current mirror unit and the fine tuning unit, the current mirror unit is connected with the fine tuning unit, the bias current output unit is connected with the current mirror unit, and the fine tuning unit is also connected with an external control source; the reference current output unit is used for outputting reference current according to input low-voltage current, the fine adjustment unit is used for controlling a mirror scale factor of the current mirror unit according to the control source, the current mirror unit is used for outputting bias current according to the mirror scale factor, and the bias current output unit is used for outputting the bias current to the signal amplification module. The method and the device can adjust the bias current of the MIPI module.
Description
Technical Field
The application relates to the field of electronic circuits, in particular to a biasing circuit of MIPI, a MIPI module and a display device.
Background
In a physical layer of an MIPI (Mobile Industry Processor Interface) module, a bias amplifier 2 for amplifying a signal is generally provided, and a constant DC current of a certain value is generally generated in the bias amplifier 2 by a bias circuit and supplied to the amplifier. As shown in fig. 1, the bias circuit is generally composed of a trimming circuit 1 composed of a variable resistor, a bias amplifier 2 and a current mirror, and generates a bias current through the current mirror, however, the bias circuit cannot adjust the proportion of the current mirror factor, thereby adjusting the bias current.
Disclosure of Invention
The embodiment of the application provides a biasing circuit of a MIPI and a MIPI module so as to adjust the biasing current of the MIPI module.
The embodiment of the application provides a MIPI's biasing circuit, is connected with the signal amplification module of MIPI module, the circuit includes: the circuit comprises a reference current output unit, a current mirror unit, a fine adjustment unit and a bias current output unit; the reference current output unit is respectively connected with the current mirror unit and the fine tuning unit, the current mirror unit is connected with the fine tuning unit, the bias current output unit is connected with the current mirror unit, and the fine tuning unit is also connected with an external control source;
the reference current output unit is used for outputting reference current according to the input low-voltage current;
the fine adjustment unit is used for controlling a mirror image scale factor of the current mirror unit according to the control source;
the current mirror unit is used for outputting a bias current according to the mirror scale factor;
the bias current output unit is used for outputting bias current to the signal amplification module.
Optionally, the reference current output unit includes: the PMOS transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS (N-channel metal oxide semiconductor) transistor, a second NMOS transistor, a first resistor and a second resistor;
the source electrode of the first PMOS tube is an input end of the reference current output unit, the grid electrode of the first PMOS tube is an enabling control end, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the other end of the first resistor is connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is further connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube is grounded, the grid electrode of the third PMOS tube is further connected with the grid electrode of the fourth PMOS tube, the source electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube is connected with one end of the resistor of the second PMOS tube, the grid electrode of the fifth PMOS tube is connected with the source electrode of the fifth PMOS tube, and the grid electrode of the second PMOS tube is further connected with the source electrode of the second PMOS tube.
Optionally, the trimming unit includes a plurality of trimming sub-units, each of the trimming sub-units is cascaded, and a first end of each of the trimming sub-units is grounded, wherein one of the trimming sub-units is connected to the reference current output unit.
Optionally, the fine tuning subunit comprises: a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor;
the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is grounded, the source electrode of the fourth NMOS tube is also connected with the drain electrode of the fifth NMOS tube, and the source electrode of the fifth NMOS tube is grounded; each fine tuning subunit is connected with the other through a drain electrode of a fourth NMOS tube, wherein the drain electrode of the fourth NMOS tube of one fine tuning subunit is connected with the current mirror unit; and the grids of the fourth NMOS tube and the fifth NMOS tube are connected with the control source.
Optionally, the current mirror unit includes: a sixth PMOS tube, a sixth NMOS tube and a seventh NMOS tube;
the source electrode of the sixth PMOS tube is connected with the input end of the reference current output unit, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the sixth PMOS tube is connected with the fine tuning unit;
the drain electrode of the sixth NMOS tube is respectively connected with the drain electrode of the fourth NMOS tube and the drain electrode of the sixth PMOS tube, the grid electrode of the sixth NMOS tube is respectively connected with the drain electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube, and the source electrode of the sixth NMOS tube is grounded; the drain electrode of the seventh NMOS tube is connected with the bias current output unit, and the source electrode of the seventh NMOS tube is grounded.
Optionally, the bias current output unit includes a seventh PMOS transistor and a plurality of eighth PMOS transistors;
the source electrode of the seventh PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the seventh PMOS tube is connected with the grid electrode of one eighth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube; and the source electrode of each eighth PMOS tube is connected with the source electrode of the seventh PMOS tube, and the drain electrode of each eighth PMOS tube is connected with the signal amplification module of the MIPI module.
Optionally, each PMOS transistor is a low-voltage PMOS transistor, and each NMOS transistor is a low-voltage NMOS transistor.
An embodiment of the present application further provides a MIPI module, where the MIPI module includes the above-mentioned bias circuit of the MIPI.
An embodiment of the present application further provides a display device, where the display device includes the MIPI module.
In the above embodiment, the reference current is output by the reference current output unit, and the mirror scale factor of the current mirror unit is controlled by the fine tuning unit, so that the current mirror unit can output the bias current according to the mirror scale factor, and the bias current output unit outputs the bias current to the signal amplification module, thereby achieving the effect of adjustable bias current.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a biasing circuit of a MIPI module in the prior art;
fig. 2 is a functional block diagram of a biasing circuit of the MIPI module in an embodiment of the present application;
fig. 3 is a circuit diagram of a biasing circuit of a MIPI module in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
In the description of the present application, it is noted that the terms "first", "second", "third", and the like are used merely for distinguishing between descriptions and are not intended to indicate or imply relative importance.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as meaning either a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
An embodiment of the present application provides a bias circuit 100 of a MIPI, as shown in fig. 2, the bias circuit 100 is connected to a signal amplification module 200 of a MIPI module, and the bias circuit includes: a reference current output unit 10, a trimming unit 20, a current mirror unit 30, and a bias current output unit; the reference current output unit 10 is respectively connected with the current mirror unit 30 and the fine tuning unit 20, the current mirror unit 30 is connected with the fine tuning unit 20, the bias current output unit is connected with the current mirror unit 30, and the fine tuning unit 20 is also connected with an external control source;
the reference current output unit 10 is used for outputting a reference current according to the input low-voltage current VLP;
the fine tuning unit 20 is used for controlling the mirror scale factor of the current mirror unit 30 according to the control source;
the current mirror unit 30 is used for outputting a bias current according to a mirror scale factor;
the bias current output unit is used to output a bias current to the signal amplification module 200.
In the above embodiment, the reference current output unit 10 outputs the reference current, and the fine tuning unit 20 controls the mirror scale factor of the current mirror unit 30 according to the control source, so that the current mirror unit 30 can output the bias current according to the mirror scale factor, and the bias current output unit outputs the bias current to the signal amplification module 200, thereby achieving the effect of adjusting the bias current.
In one embodiment, as shown in fig. 3, the reference current output unit 10 includes: the PMOS transistor comprises a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a first resistor R1 and a second resistor R2;
the source electrode of the first PMOS transistor P1 is an input end of the reference current output unit 10, the gate electrode of the first PMOS transistor P1 is an enable control end, the drain electrode of the first PMOS transistor P1 is connected with one end of the first resistor R1, the other end of the first resistor R1 is connected with the drain electrode of the first NMOS transistor N1, the gate electrode of the first NMOS transistor N1 is connected with the drain electrode of the first NMOS transistor N1, the source electrode of the first NMOS transistor N1 is grounded, the gate electrode of the first NMOS transistor N1 is also connected with the gate electrode of the second NMOS transistor N2, the source electrode of the second NMOS transistor N2 is grounded, the drain electrode of the second PMOS transistor P2 is connected with the gate electrode of the second PMOS transistor P2, the source electrode of the second PMOS transistor P2 is connected with the source electrode of the first PMOS transistor P1, the drain electrode of the second PMOS transistor P2 is connected with the source electrode of the third PMOS transistor P3, the drain electrode of the third PMOS transistor P3 is also connected with the gate electrode of the fourth PMOS transistor P4, the drain electrode of the fifth PMOS transistor P5 is connected with the drain electrode of the fourth PMOS transistor P2, the drain electrode of the fifth PMOS transistor P5, the fourth PMOS transistor P2 is connected with the drain electrode of the fourth PMOS transistor P5, and the drain electrode of the fourth PMOS transistor P5, the fourth PMOS transistor P2 is connected with the drain electrode of the fourth PMOS transistor P5, the drain electrode of the fifth PMOS transistor P2, the fifth PMOS transistor P5, the fourth PMOS transistor P5 is connected with the drain electrode of the fourth PMOS transistor P2, and the drain electrode of the fourth PMOS transistor P5, the fourth PMOS transistor P5 is connected with the drain electrode of the fourth PMOS transistor P2.
In an embodiment, the trimming unit 20 includes a plurality of trimming sub-units 21, each trimming sub-unit 21 is cascaded, and a first end of each trimming sub-unit 21 is grounded, wherein a trimming sub-unit 21 is connected to the reference current output unit 10. The mirror scale factor of the current mirror unit 30 can be adjusted by controlling the operation of each fine tuning sub-unit 21 by the control source.
Specifically, the fine adjustment subunit 21 includes: a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth NMOS transistor N5; the drain electrode of the third NMOS tube N3 is connected with the drain electrode of the fourth NMOS tube N4, the grid electrode of the third NMOS tube N3 is connected with the source electrode of the fourth NMOS tube N4, the source electrode of the third NMOS tube N3 is grounded, the source electrode of the fourth NMOS tube N4 is also connected with the drain electrode of the fifth NMOS tube N5, and the source electrode of the fifth NMOS tube N5 is grounded; each fine tuning subunit 21 is connected with the drain electrode of the fourth NMOS transistor N4, wherein the drain electrode of the fourth NMOS transistor N4 of one fine tuning subunit 21 is connected with the drain electrode of the sixth PMOS transistor P6; and the gates of the fourth NMOS tube and the fifth NMOS tube are connected with the control source, so that a control signal Trim _ RN sent by the control source is received.
In the above embodiment, the control source outputs the control signal to the fourth NMOS transistor N4 and the fifth NMOS transistor N5 to control the fourth NMOS transistor N4 and the fifth NMOS transistor N5, so as to control each fine tuning sub-unit to work, and further control the mirror scale factor of the current mirror unit 30.
In one embodiment, the current mirror unit 30 includes: a sixth PMOS tube P6, a sixth NMOS tube N6 and a seventh NMOS tube N7; a source electrode of a sixth PMOS transistor P6 is connected with the input end of the reference current output unit 10, a gate electrode of the sixth PMOS transistor P6 is connected with a drain electrode of the second NMOS transistor N2, and a drain electrode of the sixth PMOS transistor P6 is connected with the fine tuning unit 20; the drain electrode of the sixth NMOS tube N6 is respectively connected with the drain electrode of the fourth NMOS tube N4 and the drain electrode of the sixth PMOS tube P6, the grid electrode of the sixth NMOS tube N6 is respectively connected with the drain electrode of the sixth NMOS tube N6 and the grid electrode of the seventh NMOS tube N7, and the source electrode of the sixth NMOS tube N6 is grounded; the drain electrode of the seventh NMOS tube N7 is connected with the bias current output unit, and the source electrode of the seventh NMOS tube N7 is grounded.
In one embodiment, the bias current output unit 40 includes a seventh PMOS transistor P7 and a plurality of eighth PMOS transistors P8; the source electrode of the seventh PMOS tube P7 is connected with the source electrode of the sixth PMOS tube P6, the grid electrode of the seventh PMOS tube P7 is connected with the grid electrode of one eighth PMOS tube P8, and the drain electrode of the seventh PMOS tube P7 is connected with the drain electrode of the seventh NMOS tube N7; the source electrode of each eighth PMOS transistor P8 is connected to the source electrode of the seventh PMOS transistor P7, and the drain electrode of each eighth PMOS transistor P8 is connected to the signal amplification module 200 of the MIPI module.
In one embodiment, each PMOS transistor is a low voltage PMOS transistor, and each NMOS transistor is a low voltage NMOS transistor. The low voltage refers to a low-voltage component, the voltage range of the low voltage is 1.0V-1.3V, and by using the low-voltage component, a higher-precision manufacturing process such as TSMC40n and PSMC80n can be used for manufacturing the MIPI module, so that the circuit wiring area of the MIPI module is reduced.
In one embodiment, a MIPI module is provided, which includes the bias circuit proposed in the above embodiment. The descriptions of the MIPI module refer to the corresponding descriptions of the bias circuit, and are not described herein again.
In one embodiment, a display device is provided, which includes the MIPI module described above. The descriptions of the MIPI module refer to the corresponding descriptions of the bias circuit, and are not described herein again.
It should be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional units and modules is only used for illustration, and in practical applications, the above function distribution may be performed by different functional units and modules as needed, that is, the internal structure of the apparatus may be divided into different functional units or modules to perform all or part of the above described functions.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present application, and they should be construed as being included in the present application.
Claims (7)
1. A biasing circuit of MIPI, which is connected with a signal amplification module of the MIPI module, characterized in that the circuit comprises: the circuit comprises a reference current output unit, a current mirror unit, a fine adjustment unit and a bias current output unit; the reference current output unit is respectively connected with the current mirror unit and the fine tuning unit, the current mirror unit is connected with the fine tuning unit, the bias current output unit is connected with the current mirror unit, and the fine tuning unit is also connected with an external control source;
the reference current output unit is used for outputting reference current according to the input low-voltage current;
the fine adjustment unit is used for controlling a mirror image scale factor of the current mirror unit according to the control source;
the current mirror unit is used for outputting a bias current according to the mirror scale factor;
the bias current output unit is used for outputting bias current to the signal amplification module;
the fine tuning unit comprises a plurality of fine tuning sub-units, the fine tuning sub-units are cascaded, the first end of each fine tuning sub-unit is grounded, and one fine tuning sub-unit is connected with the reference current output unit;
the fine tuner unit includes: a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor;
the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is grounded, the source electrode of the fourth NMOS tube is also connected with the drain electrode of the fifth NMOS tube, and the source electrode of the fifth NMOS tube is grounded; each fine tuning subunit is connected with each other through a drain electrode of a fourth NMOS (N-channel metal oxide semiconductor) tube, and the drain electrode of the fourth NMOS tube of one fine tuning subunit is connected with the current mirror unit; and the grids of the fourth NMOS tube and the fifth NMOS tube are connected with the control source.
2. The biasing circuit of the MIPI of claim 1, wherein the reference current output unit includes: the PMOS transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS (N-channel metal oxide semiconductor) transistor, a second NMOS transistor, a first resistor and a second resistor;
the source electrode of the first PMOS tube is an input end of the reference current output unit, the grid electrode of the first PMOS tube is an enabling control end, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the other end of the first resistor is connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is further connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube is grounded, the grid electrode of the third PMOS tube is further connected with the grid electrode of the fourth PMOS tube, the source electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube is connected with one end of the resistor of the second PMOS tube, the grid electrode of the fifth PMOS tube is connected with the source electrode of the fifth PMOS tube, and the grid electrode of the second PMOS tube is further connected with the source electrode of the second PMOS tube.
3. The MIPI biasing circuit of claim 2, wherein the current mirror cell
The method comprises the following steps: a sixth PMOS tube, a sixth NMOS tube and a seventh NMOS tube;
the source electrode of the sixth PMOS tube is connected with the input end of the reference current output unit, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the sixth PMOS tube is connected with the fine tuning unit;
the drain electrode of the sixth NMOS tube is respectively connected with the drain electrode of the fourth NMOS tube and the drain electrode of the sixth PMOS tube, the grid electrode of the sixth NMOS tube is respectively connected with the drain electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube, and the source electrode of the sixth NMOS tube is grounded; the drain electrode of the seventh NMOS tube is connected with the bias current output unit, and the source electrode of the seventh NMOS tube is grounded.
4. The biasing circuit of the MIPI of claim 3, wherein the bias current output unit includes a seventh PMOS transistor and a plurality of eighth PMOS transistors;
the source electrode of the seventh PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the seventh PMOS tube is connected with the grid electrode of one eighth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube; and the source electrode of each eighth PMOS tube is connected with the source electrode of the seventh PMOS tube, and the drain electrode of each eighth PMOS tube is connected with the signal amplification module of the MIPI module.
5. The MIPI bias circuit of claim 4, wherein each PMOS transistor is a low voltage PMOS transistor and each NMOS transistor is a low voltage NMOS transistor.
6. A MIPI module characterized in that the MIPI module comprises the biasing circuit of the MIPI of any one of the claims 1-5.
7. A display device characterized in that it comprises a biasing circuit of the MIPI according to any one of claims 1-5.
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| CN112423436A (en) * | 2020-12-17 | 2021-02-26 | 北京集创北方科技股份有限公司 | Power supply circuit and display device |
| CN113114142A (en) * | 2021-04-25 | 2021-07-13 | 联芸科技（杭州）有限公司 | Rail-to-rail operational amplifier and interface circuit |
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| CN113672026A (en) | 2021-11-19 |
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