CN113671351A - Chip test substrate and chip test system - Google Patents
Chip test substrate and chip test system Download PDFInfo
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- CN113671351A CN113671351A CN202110977207.4A CN202110977207A CN113671351A CN 113671351 A CN113671351 A CN 113671351A CN 202110977207 A CN202110977207 A CN 202110977207A CN 113671351 A CN113671351 A CN 113671351A
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- 238000012360 testing method Methods 0.000 title claims abstract description 137
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 8
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 6
- 238000007654 immersion Methods 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000000523 sample Substances 0.000 abstract description 14
- 230000017525 heat dissipation Effects 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The application relates to the technical field of chips, and particularly discloses a chip testing substrate and a chip testing system. The substrate comprises a circuit board, a wiring terminal and a decoupling capacitor, wherein the circuit board comprises a plurality of bonding pads, and the bonding pads are used for connecting a plurality of pins of a chip; the wiring terminal is connected with the circuit board and comprises a first end and a second end, the first end is connected with the plurality of bonding pads, and the second end is used for connecting a chip testing device; a decoupling capacitor is connected between the second terminal and ground. Therefore, the probe is not needed to be used for leading out the chip pin, the chip pin is only needed to be connected to a preset bonding pad on the circuit board, and the bonding pad is connected with the wiring terminal, so that the chip testing device is connected with the chip testing device through the wiring terminal to realize the electric connection between the chip testing device and the chip pin during actual testing, the difficulty of connecting the chip before testing is effectively reduced, the testing efficiency is improved, the loss of the probe is avoided, and the chip testing cost is reduced.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a chip test substrate and a chip test system.
Background
Before a chip is put into use, a series of tests are often required, and a common method is to lead out chip pins through a probe station, connect test equipment to the outside, and test the chip through the test equipment. However, because the pins on the chip are distributed densely, the difficulty of pricking the pins is high for ordinary testers, the probes are easy to prick askew and inaccurate, even bad contact accidents are caused, the testing efficiency is influenced, the loss of the probes is high, and the testing cost of the chip is increased.
Disclosure of Invention
In view of the above, it is desirable to provide a chip test substrate and a chip test system.
A chip test substrate, comprising:
the circuit board comprises a plurality of bonding pads, and the bonding pads are used for connecting a plurality of pins of the chip;
the wiring terminal is connected with the circuit board and comprises a first end and a second end, the first end is connected with the plurality of bonding pads, and the second end is used for connecting a chip testing device;
and the decoupling capacitor is connected between the second end and the ground end.
In one embodiment, a side of the circuit board adjacent to the chip has a heat sink.
In one embodiment, the area of the circuit board is greater than or equal to the area of the chip.
In one embodiment, the pads are distributed on an edge area of the circuit board.
In one embodiment, the bonding pad comprises a rectangular shape, and the length of the rectangular bonding pad is between 55mil and 65mil, and the width of the rectangular bonding pad is between 5mil and 15 mil.
In one embodiment, the bonding pad is connected to the lead of the chip by wire bonding.
In one embodiment, the bonding pad is formed by a plating process, and the plating process comprises a nickel-gold immersion process or a nickel-palladium-gold process.
In one embodiment, the wiring terminal is disposed on the circuit board, and the first end is connected to the bonding pad through an embedded copper wire inside the circuit board.
In one embodiment, the connection terminal includes a plurality of sub-terminals, the sub-terminals respectively correspond to the pads, and each sub-terminal is grounded through the decoupling capacitor.
A chip testing system comprises a chip testing device and the chip testing substrate, wherein the chip testing device is connected with the second end of a wiring terminal in a pluggable mode.
The chip testing substrate comprises a circuit board, wherein a plurality of bonding pads are arranged on the circuit board, the bonding pads are used for being connected with pins of a chip, the circuit board is connected with a wiring terminal, a first end of the wiring terminal is connected with the bonding pads, a second end of the wiring terminal is used for being externally connected with a chip testing device, and the second end of the wiring terminal is grounded through a decoupling capacitor. Therefore, the probe is not needed to be used for leading out the chip pin, the chip pin is only needed to be connected to a preset bonding pad on the circuit board, and the bonding pad is connected with the wiring terminal, so that the chip testing device is connected with the chip testing device through the wiring terminal to realize the electric connection between the chip testing device and the chip pin during actual testing, the difficulty of connecting the chip before testing is effectively reduced, the testing efficiency is improved, the loss of the probe is avoided, and the chip testing cost is reduced. In addition, the second end of the wiring terminal is grounded through the decoupling capacitor, so that interference signals of chip radio-frequency signals in the testing process can be effectively removed, high-frequency switch noise generated by the chip is guided to the ground end, the propagation of the high-frequency switch noise on a circuit board is reduced, and the testing precision of the chip is improved.
Drawings
Fig. 1 is a schematic structural diagram of a chip test substrate according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a circuit board according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a chip connection according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a sub-terminal grounded through a decoupling capacitor according to an embodiment of the present disclosure.
Description of reference numerals:
100. a chip; 110. a pin; 200. a chip test substrate; 210. a circuit board; 211. a pad; 220. a wiring terminal; 221. a sub-terminal; 230. a decoupling capacitor; 300. a chip testing device.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As described in the background art, before a chip is put into use, a series of tests are often required, and a common method is to lead out pins of the chip through a probe station, connect test equipment to the outside, and test the chip through the test equipment. However, because the pins on the chip are distributed densely, the difficulty of pricking the pins is high for ordinary testers, the probes are easy to prick askew and inaccurate, even bad contact accidents are caused, the testing efficiency is influenced, the loss of the probes is high, and the testing cost of the chip is increased.
In order to solve the above problems, the present application provides a chip test substrate and a chip test system.
In one embodiment, a chip test substrate 200 is provided. The chip testing substrate 200 provided in this embodiment mainly plays a role in connecting the chip 100 and the chip testing device 300, thereby reducing the difficulty in connecting the chip and the chip testing device 300 and improving the testing efficiency.
Referring to fig. 1 and 2, the chip test substrate 200 provided in the present embodiment includes a circuit board 210, a connection terminal 220, and a decoupling capacitor 230.
The circuit board 210 includes a plurality of pads 211, and the pads 211 are used for connecting the pins 110 of the chip 100; the connection terminal 220 is connected to the circuit board 210 and includes a first end and a second end, the first end is connected to the pads 211, and the second end is used for connecting the chip testing device 300; the decoupling capacitor 230 is connected between the second terminal and ground.
Specifically, the Circuit Board 210 may be a Printed Circuit Board 210 (PCB), which may be a rigid PCB or a flexible PCB. The circuit board 210 has a plurality of pads 211 formed thereon, and the number of the pads 211 may be the same as the number of the pins 110 of the chip 100, i.e., each pad 211 may be connected to each pin 110 of the chip 100 in a one-to-one correspondence. The number of the pads 211 may also be greater than the number of the pins 110 of the chip 100, that is, the spare pads 211 are disposed on the circuit board 210, and when the pads 211 in use are damaged, the spare pads 211 may be used to connect the chip pins 110, so as to avoid a situation that the corresponding pins 110 of the chip cannot be connected to the circuit board 210 due to a failure of a specific pad 211, and improve reliability of chip connection.
The connection terminal 220 is connected to the circuit board 210, a first end of the connection terminal 220 is connected to the pads 211, and a second end of the connection terminal 220 is used for externally connecting the chip testing device 300. Before testing the chip, the pin 110 of the chip is first connected to the pad 211 correspondingly, and then the chip testing device 300 is connected to the second end of the connection terminal 220, because the pad 211 on the circuit board 210 is connected to the first end of the connection terminal 220, the pin 110 of the chip is connected to the chip testing device 300 through the pad 211 and the connection terminal 220.
The connection terminal 220 may be disposed on the circuit board 210, or may extend out of the circuit board 210 through a signal line. When the connection terminal 220 is disposed on the circuit board 210, the chip testing device 300 is directly connected to the circuit board 210, so that a signal transmission path between the chip pin 110 and the chip testing device 300 is shortened, and the integrity of signals is improved. When the connection terminal 220 extends out of the circuit board 210 through a signal line, the chip testing device 300 can be connected with the connection terminal 220 at the end of the signal line, and when the chip testing device 300 is inconvenient to be directly connected with the circuit board 210, the connection convenience is improved in this way.
The second terminal of the connection terminal 220 is further connected to a ground terminal through a decoupling capacitor 230, and the decoupling capacitor 230 is used for removing an interference signal generated in a chip testing process, so that the testing precision is improved.
The chip testing substrate 200 comprises a circuit board 210, wherein the circuit board 210 is provided with a plurality of bonding pads 211, the bonding pads 211 are used for being connected with pins 110 of a chip, the circuit board 210 is connected with a wiring terminal 220, a first end of the wiring terminal 220 is connected with the bonding pads 211, a second end of the wiring terminal 220 is used for being externally connected with a chip testing device 300, and the second end of the wiring terminal is grounded through a decoupling capacitor 230. Therefore, the probe is not required to be used for leading out the chip pins 110, the chip pins 110 are only required to be connected to the preset bonding pads 211 on the circuit board 210, and the bonding pads 211 are connected with the wiring terminals 220, so that during actual testing, the chip testing device 300 is connected with the chip testing device 300 through the wiring terminals 220, and the electric connection between the chip testing device 300 and the chip pins 110 can be realized. In addition, the second end of the connection terminal 220 is grounded through the decoupling capacitor 230, so that interference signals of noise waves inside a power supply or a circuit to the radio frequency signals of the chip can be effectively removed in the test process, bad common mode radio frequency energy is transferred out from the circuit board 210, meanwhile, high-frequency switching noise generated by the chip is guided to the ground end, the propagation of the high-frequency switching noise on the circuit board 210 is reduced, and the test precision of the chip is improved.
In one embodiment, the side of the circuit board 210 adjacent to the chip has a heat spreader.
Because the chip can produce heat in the testing process, because the circuit board 210 has the heat dissipation piece near one side of the chip, consequently, can dispel the heat to the chip through the heat dissipation piece, improve chip test substrate 200 to the heat-sinking capability of the heat that produces in the chip work, guarantee that the chip works under relatively stable operating temperature. The heat dissipation piece can comprise a copper sheet formed on the surface of the chip, the chip is dissipated through the copper sheet, the cost is low, and the process is simple.
In one embodiment, the area of the circuit board 210 is greater than or equal to the area of the chip.
Because the area of the circuit board 210 is greater than or equal to the area of the chip, in the process of connecting the pins 110 of the chip and the bonding pads 211 on the circuit board 210, a tester can clearly observe the positions of the bonding pads 211 and the chip pins 110 on the circuit board 210, and the connection difficulty between the chip pins 110 and the bonding pads 211 is reduced. Meanwhile, the larger the area of the circuit board 210 is, the larger the area of the heat dissipation piece on the surface of the circuit board can be, so that the heat generated after the chip is electrified is effectively diffused to the external environment through the heat dissipation piece, the possibility of efficiency reduction and power consumption improvement of the chip due to heating is reduced, and effective guarantee is provided for accurate testing of the chip. For example, the circuit board 210 may be provided in a rectangular shape of 4mm × 4mm in size.
In one embodiment, referring to fig. 2, the pads 211 are distributed at an edge region of the circuit board 210. In this embodiment, the bonding pads 211 are disposed on the edge region of the circuit board 210, so that the bonding pads 211 are connected to the chip pins 110. For example, the circuit board 210 is a rectangle, the pads 211 are respectively disposed at the edges of four sides of the rectangular circuit board 210, the pads 211 may be equally distributed to the edges of the four sides according to the number of the pads 211, or may be disposed according to actual requirements. For example, referring to fig. 2, the circuit board 210 has a total of 40 pads 211, 10 pads 211 may be disposed on four side edges of the rectangular circuit board 210, or 15 pads 211 may be disposed on two opposite sides of the rectangular circuit board, and 5 pads 211 may be disposed on the other two opposite sides of the rectangular circuit board.
In this embodiment, a certain preset interval is reserved between the pads 211, which avoids a connection error between the pads 211 and the chip pins 110 due to a too close distance between the pads 211, provides operability for connection between the chip pins 110 and the pads 211, and reduces connection difficulty.
In one embodiment, the bonding pad 211 comprises a rectangular shape, and the length of the rectangular bonding pad 211 is between 55mil and 65mil and the width is between 5mil and 15 mil. For example, the length may be 55 mils, 60 mils, 65 mils, etc., and the width may be 5 mils, 10 mils, or 15 mils. In this embodiment, the length of the rectangular pad 211 is preferably set to 60 mils, and the width is preferably set to 10 mils.
In one embodiment, the bonding pads 211 are connected to the leads 110 of the chip by wire bonding. The wire bonding is a method using a thin metal wire, the metal wire and the bonding pad 211 are tightly welded by heat, pressure and ultrasonic energy, and the bonding pad 211 and the chip pin 110 are connected in a wire bonding mode, so that on one hand, the connection reliability is high, the tight connection between the chip pin 110 and the bonding pad 211 is facilitated, on the other hand, the process is simple, the connection difficulty is reduced, and the overall efficiency of the test is improved.
In one embodiment, the bonding pads 211 are formed using a plating process including a nickel-gold immersion process or a nickel-palladium-gold process. The nickel-gold immersion process is low in cost, and the overall cost of the chip test substrate 200 can be reduced; the bonding pad 211 is formed by ni-pd-au process, so that the bonding pad 211 and the chip lead 110 can be connected more easily by wire bonding. In practical application, the plating process can be selected according to actual requirements.
In one embodiment, the connection terminal 220 is disposed on the circuit board 210, and the first end of the connection terminal passes through the pre-buried copper wire connection pad 211 inside the circuit board 210. That is, the copper wire is embedded in the circuit board 210 for the connection of the internal components of the circuit board 210, the bonding pad 211 is directly printed out to the first end of the connection terminal 220 through the embedded copper wire, and the external chip testing device 300 is directly connected with the connection terminal 220, so that the connection with the chip pin 110 can be realized.
In one embodiment, referring to fig. 3, the connection terminal 220 includes a plurality of sub-terminals 221, the plurality of sub-terminals 221 respectively correspond to the plurality of pads 211, and each sub-terminal 221 is grounded through a decoupling capacitor 230 (refer to fig. 4). The connection terminal 220 may be in the form of a strip socket or a strip pin, and has a plurality of sub-terminals 221, each sub-terminal 221 has a first end and a second end, the first end of the connection terminal 220 refers to the first ends of all the sub-terminals 221, and the second end of the connection terminal 220 refers to the second ends of all the sub-terminals 221. The first end of each sub-terminal 221 is connected to each pad 211, and the second end of each sub-terminal 221 is grounded through a decoupling capacitor 230, and only one sub-terminal 221 is illustrated in fig. 4 as an example.
Wherein, binding post 220 can select for use the row that the interval is 2.54mm to insert or arrange the needle, and it is general size, can compatible dupont line etc. wire's size, greatly compatible chip testing arrangement 300's connecting piece adapts to various operating mode environment in a flexible way.
In one embodiment, a chip test system is provided.
The chip testing system provided by the embodiment includes the chip testing device 300 and the chip testing substrate 200 provided by the above embodiment, and the chip testing device 300 is connected to the second end of the connection terminal 220 in a pluggable manner.
The chip test substrate 200 includes a circuit board 210, a connection terminal 220, and a decoupling capacitor 230. The circuit board 210 includes a plurality of pads 211, the plurality of pads 211 are used for connecting a plurality of pins 110 of the chip; the connection terminal 220 is connected to the circuit board 210 and includes a first end and a second end, the first end is connected to the pads 211, and the second end is used for connecting the chip testing device 300; the decoupling capacitor 230 is connected between the second terminal and ground.
When a chip needs to be tested, the chip pin 110 is correspondingly connected with the pad 211 on the chip test substrate 200, and then the chip test device 300 is connected with the second end of the connection terminal 220, because the pad 211 is connected with the first end of the connection terminal 220, the chip test device 300 is connected with the chip pin 110, and then the chip pin 110 can be tested through the test chip device. After the test is completed, the test chip device is removed from the second end of the connection terminal 220.
Specifically, the Circuit Board 210 may be a Printed Circuit Board 210 (PCB), which may be a rigid PCB or a flexible PCB. The circuit board 210 has a plurality of pads 211 formed thereon, and the number of the pads 211 may be the same as the number of the pins 110 of the chip, i.e., each pad 211 may be connected to each pin 110 of the chip in a one-to-one correspondence. The number of the pads 211 may also be greater than the number of the pins 110 of the chip, that is, the spare pads 211 are disposed on the circuit board 210, and when the pads 211 in use are damaged, the spare pads 211 may be used to connect the pins 110 of the chip, thereby avoiding a situation that the corresponding pins 110 of the chip cannot be connected to the circuit board 210 due to a failure of a specific pad 211, and improving reliability of chip connection.
The connection terminal 220 is connected to the circuit board 210, a first end of the connection terminal 220 is connected to the pads 211, and a second end of the connection terminal 220 is used for externally connecting the chip testing device 300. Before testing the chip, the pin 110 of the chip is first connected to the pad 211 correspondingly, and then the chip testing device 300 is connected to the second end of the connection terminal 220, because the pad 211 on the circuit board 210 is connected to the first end of the connection terminal 220, the pin 110 of the chip is connected to the chip testing device 300 through the pad 211 and the connection terminal 220.
The connection terminal 220 may be disposed on the circuit board 210, or may extend out of the circuit board 210 through a signal line. When the connection terminal 220 is disposed on the circuit board 210, the chip testing device 300 is directly connected to the circuit board 210, so that a signal transmission path between the chip pin 110 and the chip testing device 300 is shortened, and the integrity of signals is improved. When the connection terminal 220 extends out of the circuit board 210 through a signal line, the chip testing device 300 can be connected with the connection terminal 220 at the end of the signal line, and when the chip testing device 300 is inconvenient to be directly connected with the circuit board 210, the connection convenience is improved in this way.
The second terminal of the connection terminal 220 is further connected to a ground terminal through a decoupling capacitor 230, and the decoupling capacitor 230 is used for removing an interference signal generated in a chip testing process, so that the testing precision is improved.
The chip testing system provided by the embodiment does not need to use a probe to lead out the chip pin 110, the chip pin 110 is only required to be connected to the preset bonding pad 211 on the circuit board 210, and the bonding pad 211 is connected with the wiring terminal 220, so that during actual testing, the chip testing device 300 is connected with the chip testing device 300 through the wiring terminal 220 to realize the electric connection between the chip testing device 300 and the chip pin 110, and compared with a mode of leading out the chip pin 110 through a probe station, the above connection mode provided by the embodiment of the application effectively reduces the difficulty of connecting a chip before testing, improves the testing efficiency, avoids the loss of the probe, and reduces the chip testing cost. In addition, the second end of the connection terminal 220 is grounded through the decoupling capacitor 230, so that interference signals of chip radio frequency signals in the test process can be effectively removed, bad common mode radio frequency energy is transferred out from the circuit board 210, high frequency switching noise generated by the chip is guided to the ground end, the propagation of the high frequency switching noise on the circuit board 210 is reduced, and the chip test precision is improved.
In one embodiment, the side of the circuit board 210 adjacent to the chip has a heat spreader. Because the chip can produce heat in the testing process, because the circuit board 210 has the heat dissipation piece near one side of the chip, consequently, can dispel the heat to the chip through the heat dissipation piece, improve chip test substrate 200 to the heat-sinking capability of the heat that produces in the chip work, guarantee that the chip works under relatively stable operating temperature. The heat dissipation piece can comprise a copper sheet formed on the surface of the chip, the chip is dissipated through the copper sheet, the cost is low, and the process is simple.
In one embodiment, the area of the circuit board 210 is greater than or equal to the area of the chip. Because the area of the circuit board 210 is greater than or equal to the area of the chip, in the process of connecting the pins 110 of the chip and the bonding pads 211 on the circuit board 210, a tester can clearly observe the positions of the bonding pads 211 and the chip pins 110 on the circuit board 210, and the connection difficulty between the chip pins 110 and the bonding pads 211 is reduced. Meanwhile, the larger the area of the circuit board 210 is, the larger the area of the heat dissipation piece on the surface of the circuit board can be, so that the heat generated after the chip is electrified is effectively diffused to the external environment through the heat dissipation piece, the possibility of efficiency reduction and power consumption improvement of the chip due to heating is reduced, and effective guarantee is provided for accurate testing of the chip. For example, the circuit board 210 may be provided in a rectangular shape of 4mm × 4mm in size.
In one embodiment, the pads 211 are distributed on an edge area of the circuit board 210. In this embodiment, the bonding pads 211 are disposed on the edge region of the circuit board 210, so that the bonding pads 211 are connected to the chip pins 110. For example, the circuit board 210 is a rectangle, the pads 211 are respectively disposed at the edges of four sides of the rectangular circuit board 210, the pads 211 may be equally distributed to the edges of the four sides according to the number of the pads 211, or may be disposed according to actual requirements. For example, referring to fig. 2, the circuit board 210 has a total of 40 pads 211, 10 pads 211 may be disposed on four side edges of the rectangular circuit board 210, or 15 pads 211 may be disposed on two opposite sides of the rectangular circuit board, and 5 pads 211 may be disposed on the other two opposite sides of the rectangular circuit board.
In this embodiment, a certain preset interval is reserved between the pads 211, which avoids a connection error between the pads 211 and the chip pins 110 due to a too close distance between the pads 211, provides operability for connection between the chip pins 110 and the pads 211, and reduces connection difficulty.
In one embodiment, the bonding pad 211 comprises a rectangular shape, and the length of the rectangular bonding pad 211 is between 55mil and 65mil and the width is between 5mil and 15 mil. For example, the length may be 55 mils, 60 mils, 65 mils, etc., and the width may be 5 mils, 10 mils, or 15 mils. In this embodiment, the length of the rectangular pad 211 is preferably set to 60 mils, and the width is preferably set to 10 mils.
In one embodiment, the bonding pads 211 are connected to the leads 110 of the chip by wire bonding. The wire bonding is a method using a thin metal wire, the metal wire and the bonding pad 211 are tightly welded by heat, pressure and ultrasonic energy, and the bonding pad 211 and the chip pin 110 are connected in a wire bonding mode, so that on one hand, the connection reliability is high, the tight connection between the chip pin 110 and the bonding pad 211 is facilitated, on the other hand, the process is simple, the connection difficulty is reduced, and the overall efficiency of the test is improved.
In one embodiment, the bonding pads 211 are formed using a plating process including a nickel-gold immersion process or a nickel-palladium-gold process. The nickel-gold immersion process is low in cost, and the overall cost of the chip test substrate 200 can be reduced; the bonding pad 211 is formed by ni-pd-au process, so that the bonding pad 211 and the chip lead 110 can be connected more easily by wire bonding. In practical application, the plating process can be selected according to actual requirements.
In one embodiment, the connection terminal 220 is disposed on the circuit board 210, and the first end of the connection terminal passes through the pre-buried copper wire connection pad 211 inside the circuit board 210. That is, the copper wire is embedded in the circuit board 210 for the connection of the internal components of the circuit board 210, the bonding pad 211 is directly printed out to the first end of the connection terminal 220 through the embedded copper wire, and the external chip testing device 300 is directly connected with the connection terminal 220, so that the connection with the chip pin 110 can be realized.
In one embodiment, the connection terminal 220 includes a plurality of sub-terminals 221, the plurality of sub-terminals 221 respectively correspond to the plurality of pads 211, and each sub-terminal 221 is grounded through the decoupling capacitor 230. The connection terminal 220 may be in the form of a strip socket or a strip pin, and has a plurality of sub-terminals 221, each sub-terminal 221 has a first end and a second end, the first end of the connection terminal 220 refers to the first ends of all the sub-terminals 221, and the second end of the connection terminal 220 refers to the second ends of all the sub-terminals 221. A first end of each sub-terminal 221 is connected to each pad 211, and a second end of each sub-terminal 221 is grounded through a decoupling capacitor 230.
Wherein, binding post 220 can select for use the row that the interval is 2.54mm to insert or arrange the needle, and it is general size, can compatible dupont line etc. wire's size, greatly compatible chip testing arrangement 300's connecting piece adapts to various operating mode environment in a flexible way.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A chip test substrate, comprising:
the circuit board comprises a plurality of bonding pads, and the bonding pads are used for connecting a plurality of pins of the chip;
the wiring terminal is connected with the circuit board and comprises a first end and a second end, the first end is connected with the plurality of bonding pads, and the second end is used for connecting a chip testing device;
and the decoupling capacitor is connected between the second end and the ground end.
2. The chip test substrate according to claim 1, wherein a side of the circuit board adjacent to the chip has a heat sink.
3. The chip test substrate according to claim 2, wherein the area of the circuit board is greater than or equal to the area of the chip.
4. The chip test substrate according to claim 1, wherein the pads are distributed at an edge region of the circuit board.
5. The chip test substrate according to claim 1, wherein the bonding pad comprises a rectangular shape, and the length of the rectangular bonding pad is between 55mil and 65mil, and the width of the rectangular bonding pad is between 5mil and 15 mil.
6. The chip test substrate according to claim 1, wherein the pads are connected to the leads of the chip by wire bonding.
7. The chip test substrate according to claim 1, wherein the pads are formed using a plating process, the plating process comprising a nickel-gold immersion process or a nickel-palladium-gold process.
8. The substrate of claim 1, wherein the connecting terminal is disposed on the circuit board, and the first end is connected to the bonding pad through a pre-buried copper wire inside the circuit board.
9. The substrate for testing chips of claim 1, wherein said connecting terminal comprises a plurality of sub-terminals, each of said plurality of sub-terminals corresponds to a respective one of said plurality of bonding pads, and each of said sub-terminals is grounded via said decoupling capacitor.
10. A chip testing system comprising a chip testing device and the chip testing substrate according to any one of claims 1 to 9, wherein the chip testing device is connected to the second end of the connection terminal in a pluggable manner.
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| CN115267496A (en) * | 2022-07-26 | 2022-11-01 | 南京芯驰半导体科技有限公司 | A chip testing device and testing method |
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