CN113659982A

CN113659982A - Signal processing circuit and signal processing method thereof

Info

Publication number: CN113659982A
Application number: CN202010398848.XA
Authority: CN
Inventors: 陈昀泽; 黄亮维; 苏季希; 林铂涵
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-05-12
Filing date: 2020-05-12
Publication date: 2021-11-16
Anticipated expiration: 2040-05-12
Also published as: CN113659982B

Abstract

Embodiments of the present disclosure relate to a signal processing circuit and a signal processing method thereof. A signal processing circuit, comprising: a first clock source for generating a first clock signal; a phase adjustment circuit for receiving the first clock signal to generate a second clock signal and a third clock signal with different phases a clock signal; a transmission circuit for generating an output signal according to the first clock signal; an error compensation circuit for compensating an input signal according to an error signal to generate a compensated input signal; an error calculation circuit, for generating the error signal according to the first clock signal, the third clock signal and the compensated input signal; and a receiver analog-to-digital converter for generating the compensated input signal according to the second clock signal The input signal is sampled.

Description

Signal processing circuit and signal processing method thereof

Technical Field

The present invention relates to a signal processing circuit, and more particularly, to a signal processing circuit capable of sampling a compensated input signal with a simple circuit structure and selecting an appropriate sampling phase.

Background

In a conventional transceiver circuit, since signals are transmitted and received by using the same set of circuits, the received signals and the transmitted signals may interfere with each other, which is called echo (echo). In order to improve the problem of echo, error detection is performed on the signal to compensate the input signal. However, the error calculation circuit in the prior art often requires a circuit with a larger area or a more complicated calculation manner. Furthermore, there may be multiple elements in the transceiver circuit to sample the same signal, but the value of the sampled signal may be affected by the sampling operation, so that if the sampling phases of the multiple elements are too close, an incorrect sampling value may be obtained.

Disclosure of Invention

Therefore, an object of the present invention is to provide a signal processing circuit or a signal processing method that can improve the problem of the error calculation circuit in the prior art that requires a circuit with a larger area or a more complicated calculation method.

An object of the present invention is to provide a signal processing circuit or a signal processing method capable of selecting an appropriate sampling phase.

An embodiment of the present invention discloses a signal processing circuit, including: a first clock source for generating a first clock signal; a phase adjustment circuit for receiving the first clock signal and generating a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases; an error compensation circuit for compensating an input signal according to an error signal to generate a compensated input signal; an error calculation circuit for generating the error signal according to the first clock signal, the third clock signal and the compensated input signal; and a receiving end analog-to-digital converter for sampling the compensated input signal according to the second clock signal.

Another embodiment of the present invention discloses a signal processing method, including: (a) generating a first clock signal, a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases; (b) generating a compensated input signal by an error compensation circuit according to an error signal to compensate an input signal; (c) generating the error signal by an error calculation circuit according to the first clock signal, the third clock signal and the compensated input signal; and (d) sampling the compensated input signal by a receiving-end analog-to-digital converter according to the second clock signal.

In summary, the signal processing circuit and the signal processing method provided by the present disclosure can perform error compensation (echo suppression) with a simpler circuit and a smaller amount of data, and can solve the problem that the error calculation circuit in the prior art often needs a circuit with a larger area or a more complicated calculation method. Moreover, the sampling phases of different elements can have larger phase difference, so as to improve the inaccuracy of sampling values caused by too close sampling phases.

Drawings

FIG. 1 is a block diagram of a signal processing circuit according to an embodiment of the invention.

FIG. 2 is a more detailed block diagram of the signal processing circuit shown in FIG. 1 according to one embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating the operation of the signal processing circuit shown in FIG. 2 to select a sampling phase.

FIG. 4 is a block diagram of the signal processing circuit shown in FIG. 2 used in a network device.

Fig. 5 is a flow chart of a signal processing method according to an embodiment of the invention.

Detailed Description

The present invention will be described in terms of various embodiments, and it is also noted that the components of each embodiment can be implemented by hardware (e.g., a device or circuit) or firmware (e.g., at least one program written in a microprocessor). Furthermore, the terms "first," "second," and the like in the following description are used only to define different components, parameters, data, signals, or steps. And are not intended to be limiting. In addition, the components in the embodiments may be integrated into fewer components or divided into more components without changing the overall functions.

The signal processing circuit provided by the invention will be described in a plurality of embodiments. It should be noted that the signal processing circuit in the following embodiments is used as a signal transceiver circuit (signal transceiver), but the signal processing circuit provided in the present invention is not limited to being used as a signal transceiver circuit.

Fig. 1 is a block diagram of a signal processing circuit 100 according to an embodiment of the invention. As shown in fig. 1, the signal processing circuit 100 includes a first clock source CLKS _1, a transmitting circuit 101, a phase adjusting circuit 102, an error compensating circuit 103, an error calculating circuit 105, and a receiving ADC 107(Analog to Digital Converter). The first clock source CLKS _1 generates a first clock signal CLK _ 1. The phase adjustment circuit 102 is configured to receive a first clock signal CLK _1, generate a second clock signal CLK _2 and a third clock signal CLK _3, wherein the second clock signal CLK _2 and the third clock signal CLK _3 have different phases. The transmission circuit 101 is used for generating an output signal OS according to the first clock signal CLK _ 1. The error compensation circuit 103 IS used for compensating an input signal IS according to an error signal ES to generate a compensated input signal CIS. The error calculating circuit 103 is used for generating an error signal ES according to the first clock signal CLK _1, the third clock signal CLK _3 and the compensated input signal CIS. The receiving-end ADC is configured to sample the compensated input signal CIS according to the second clock signal CLK _ 2. In one embodiment, the output signal OS generated by the transmitting circuit 101 passes through a hybrid circuit (hybrid circuit) in the error compensation circuit 103 and then is output, but not limited thereto.

Compared with the conventional signal transceiver circuit, the error calculation circuit 103 in the signal processing circuit 100 performs error calculation according to a part of the compensated input signal CIS received by the receiving-end ADC 107, rather than according to a large amount of data at the output end of the receiving-end ADC 107. Thus requiring only simpler circuitry and computational steps.

FIG. 2 is a more detailed block diagram of the signal processing circuit shown in FIG. 1 according to one embodiment of the present invention. It should be noted that the circuit shown in fig. 2 is only an example, and all circuit architectures that achieve the same functions should be covered by the scope of the present invention. As shown in fig. 2, the signal processing circuit 200 includes a first clock source CLKS _1, an output DAC (Digital to Analog Converter) 201, a hybrid circuit (e.g., hybrid circuit)203, an echo DAC 205, an Analog echo canceller (Analog echo canceller)207, an n-bit ADC209, a receiving ADC211, and the aforementioned phase adjusting circuit 102. The output DAC 201 functions as the transmission circuit 101 in fig. 1, and the hybrid circuit 203 functions as the error compensation circuit 103 in fig. 1. An echo DAC 205, an analog echo interference canceller 207, and an n-bit ADC209 serve as the error calculation circuit 105 in fig. 1.

Therefore, in the embodiment of fig. 2, the output signal OS is an analog signal, and the output DAC 201 converts a digital output signal DOS according to the first clock signal CLK _1 to generate the output signal OS. The hybrid circuit 203 IS used to output the output signal OS and subtract the error signal ES from the input signal IS to generate a compensated input signal CIS. The n-bit ADC209 samples the compensated input signal CIS for a predetermined period according to the third clock signal CLK _3 and outputs an n-bit error reference value EV, where n is a positive integer. In one embodiment, n is equal to 1. The n-bit ADC209 has an advantage of simpler structure and can reduce the data amount of the error reference value. For example, if the n-bit ADC209 is a 1-bit analog-to-digital converter (1-bit ADC), the n-bit ADC209 samples the compensated input signal CIS for a predetermined period to generate a plurality of sample values (e.g., 10), and then outputs a 1-bit error reference value according to the 10 sample values. In one example, the 10 samples may be averaged to output a 1-bit error reference. In one embodiment, the n-bit ADC209 outputs the minimum root Mean Square error (LMS error) of the compensated input signal CIS.

In an embodiment, the signal processing circuit 200 further has a high-pass filter and an amplifier between the mixing circuit 203 and the receiving-side ADC 211. Therefore, what the n-bit ADC209 samples and what the receiving ADC211 receives is the compensated input signal CIS after being processed by the high pass filter and the amplifier.

As previously described, in the embodiment of fig. 2, the echo DAC 205, the analog echo interference canceller 207, and the n-bit ADC209 function as the error calculation circuit 105 in fig. 1. As shown in fig. 2, the analog echo interference canceller 207 generates a digital error signal DES according to the output of the n-bit ADC209, and then the echo DAC 205 converts the digital error signal DES into an analog error signal ES. Various circuits may be used to implement the echo DAC 205 and the analog echo interference canceller 207, and thus are not described herein. The phase adjustment circuit 102 is used for receiving the first clock signal CLK _1 and adjusting the phase of the first clock signal CLK _1 to generate a second clock signal CLK _2 and a third clock signal CLK _3, respectively. In one embodiment, the phase adjusting circuit 102 is a phase interpolator (phase interpolator).

In one embodiment, the receiving ADC211 samples a first phase of the compensated input signal CIS, and the n-bit ADC209 samples a second phase of the compensated input signal CIS, where a phase difference between the first phase and the second phase is greater than a predetermined phase difference. Since the signal values of the signals may be disturbed when they are sampled, if the sampling points of different elements are too close to each other when they sample the same signal, they may interfere with each other and result in incorrect sampled values. Therefore, by making the phase difference between the first phase and the second phase larger, different elements will not interfere with each other when sampling the same signal.

FIG. 3 is a schematic diagram illustrating the operation of the signal processing circuit shown in FIG. 2 to select a sampling phase. Ph _0, Ph _1, Ph _2 … Ph _7 respectively represent the phase adjustment circuit 102 adjusting different phases of the first clock signal CLK _ 1. In this embodiment, the phase adjustment circuit 102 adjusts the first clock signal CLK _1 into 8 clock signals with different phases. As shown in fig. 3, the first phases P _11 and P _12 are interpolated to obtain the sampling phase of the receiving-end ADC211 to the compensated input signal CIS, and the second phases P _21 and P _22 are interpolated to obtain the sampling phase of the n-bit ADC209 to the compensated input signal CIS. As can be seen from fig. 3, the first phases P _11 and P _12 and the second phases P _21 and P _22 have a phase difference of at least two phases (Ph _4 and Ph _5), i.e., the first phases P _11 and P _12 and the second phases P _21 and P _22 are phases having a larger phase difference (or, a phase difference at a greater distance). In one embodiment, the receiving ADC211 samples the compensated input signal CIS by interpolating a clock signal having a third phase from a plurality of first phases (e.g., P _11 and P _ 12). The n-bit ADC209 samples the compensated input signal CIS by interpolating a clock signal having at least one phase in a plurality of second phases (e.g., P _21 and P _ 22). However, if the n-bit ADC209 samples only once and then outputs one error reference value within a predetermined period, the n-bit ADC209 may sample using only one second phase. In another embodiment, after determining that the clock signal used by the receiving ADC211 has the third phase, the phase farther away from the third phase in the remaining phases can be dynamically selected as the sampling phase (e.g., one of P _21 and P _22) of the clock signal used by the n-bit ADC209 to avoid that the sampling time points of the two ADCs are too close to each other and affect each other.

Fig. 4 is a block diagram of the signal processing circuit shown in fig. 2 used in a network device 400, which in one embodiment is an Ethernet (Ethernet) device. In the embodiment of fig. 4, in addition to the components of the embodiment shown in fig. 2, the network device 400 further includes a transceiving interface 401 and a DSP (Digital Signal processing) circuit 403. The transceiving interface 401 IS configured to receive an input signal IS and an output signal OS, and may be a single transmission line, a pair of transmission lines (pair), a single endpoint, a single pin, or a single port. The DSP circuit 403 is used to process the output of the receiving ADC211 for providing to the subsequent circuits. In addition, in an embodiment, the DSP circuit 403 further controls the phase adjustment circuit 102 to control the sampling phases of the receiving-end ADC211 and the n-bit ADC209 according to the condition of the output of the receiving-end ADC 211. For example, the sampling phases of the receiving-side ADC211 and the n-bit ADC209 may be controlled according to a Signal-to-Noise Ratio (SNR) of the output Signal of the receiving-side ADC, or whether the output Signal is easy to converge, but is not limited thereto.

FIG. 5 is a flow chart of a signal processing method according to an embodiment of the invention, which includes the following steps:

step 501

A first clock signal CLK _1, a second clock signal CLK _2 and a third clock signal CLK _3 are generated. The second clock signal CLK _2 and the third clock signal CLK _3 have different phases.

Step 503

An output signal OS is generated by a transmitting circuit according to the first clock signal CLKS _ 1.

Step 505

An error compensation circuit compensates an input signal IS according to an error signal ES to generate a compensated input signal CIS.

Step 507

An error signal ES is generated by an error calculation circuit according to the first clock signal CLK _1, the third clock signal CLK _3 and the compensated input signal CIS.

Step 509

The compensated input signal CIS is sampled by a receiving ADC according to the second clock signal CLK _ 2.

Other detailed steps are disclosed in the foregoing embodiments and are not described herein again. It should be understood that, in the embodiment, the steps mentioned in the sequence may be adjusted according to the actual requirement, and may even be executed at the same time or partially at the same time, except for the sequence specifically mentioned.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.

[ notation ] to show

100. 200, 400 signal processing circuit

101 transmission circuit

102 phase adjusting circuit

103 error compensation circuit

105 error calculation circuit

107 receiving end ADC

200 signal processing circuit

201 output DAC

203 hybrid circuit

205 echo DAC

207 analog echo interference canceller

209n bit ADC

211 receiving end ADC

401 transceiver interface

403DSP circuit

CLKS _1 first clock Source

Claims

1. A signal processing circuit, comprising:

a first clock source for generating a first clock signal;

a phase adjustment circuit for receiving the first clock signal and generating a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases;

an error compensation circuit for compensating the input signal according to the error signal to generate a compensated input signal;

an error calculation circuit to generate the error signal from the first clock signal, the third clock signal, and the compensated input signal; and

A receiver analog-to-digital converter for sampling the compensated input signal according to the second clock signal.

2. The signal processing circuit according to claim 1, further comprising:

a transmission circuit for generating an output signal according to the first clock signal;

The transmission circuit is an output-end digital-to-analog converter, and the output signal is an analog signal, and the transmission circuit converts a digital output signal according to the first clock signal to generate the output signal.

3. The signal processing circuit of claim 1, wherein the error calculation circuit comprises:

an n-bit analog-to-digital converter for sampling the compensated input signal within a predetermined period according to the third clock signal and outputting an n-bit error reference value, where n is a positive integer;

The error calculation circuit generates the error signal according to the error reference value.

4. The signal processing circuit of claim 3, wherein the n-bit analog-to-digital converter is a 1-bit analog-to-digital converter.

5. The signal processing circuit of claim 3, wherein the second clock signal has a first phase, the third clock signal has a second phase, and the first phase and the second phase The phase difference is greater than a predetermined phase difference.

6 . The signal processing circuit according to claim 5 , further comprising a digital signal processing circuit for controlling the phase adjustment circuit to control the analog-to-digital converter at the receiving end according to the output state of the analog-to-digital converter at the receiving end. 7 . The sampling phase of the digitizer and the n-bit analog-to-digital converter.

7. The signal processing circuit of claim 5, wherein the phase adjustment circuit is a phase interpolation circuit.

8. The signal processing circuit of claim 3, wherein the second clock signal has a plurality of first phases.

9 . The signal processing circuit of claim 8 , wherein the analog-to-digital converter at the receiving end samples the compensated input signal by interpolating a third phase from a plurality of the first phases. 10 .

10. A signal processing method, comprising:

(a) generating a first clock signal, a second clock signal, and a third clock signal, wherein the second clock signal and the third clock signal have different phases;

(b) generating a compensated input signal by compensating the input signal according to the error signal by the error compensation circuit;

(c) generating the error signal from the first clock signal, the third clock signal, and the compensated input signal by an error calculation circuit; and

(d) The compensated input signal is sampled by a receiver analog-to-digital converter according to the second clock signal.