CN113659980B - Lock detection circuit and phase-locked loop circuit system - Google Patents
Lock detection circuit and phase-locked loop circuit system Download PDFInfo
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- CN113659980B CN113659980B CN202110970784.0A CN202110970784A CN113659980B CN 113659980 B CN113659980 B CN 113659980B CN 202110970784 A CN202110970784 A CN 202110970784A CN 113659980 B CN113659980 B CN 113659980B
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- 238000005070 sampling Methods 0.000 claims abstract description 103
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- 238000000034 method Methods 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
本发明提供了一种锁定检测电路，用于锁相环电路的锁定检测，包括第一采样单元、第二采样单元、与门和计数单元，所述与门与所述第一采样单元和所述第二采样单元以及计数单元连接，第一采样单元用于接收前置分频信号和反馈分频信号，并通过所述反馈分频信号对所述前置分频信号采样，以输出第一采样信号，第二采样单元用于接收所述前置分频信号的反向信号和所述反馈分频信号，并通过所述前置分频信号的反向信号对所述反馈分频信号采样，以输出第二采样信号的反向信号，采用双沿环路锁定检测，降低锁相环电路的误锁几率。本发明提供了一种锁相环电路系统。
The present invention provides a locking detection circuit for locking detection of a phase-locked loop circuit, comprising a first sampling unit, a second sampling unit, an AND gate and a counting unit, wherein the AND gate is connected to the first sampling unit, the second sampling unit and the counting unit, the first sampling unit is used to receive a pre-frequency division signal and a feedback frequency division signal, and to sample the pre-frequency division signal through the feedback frequency division signal to output a first sampling signal, the second sampling unit is used to receive an inverse signal of the pre-frequency division signal and the feedback frequency division signal, and to sample the feedback frequency division signal through the inverse signal of the pre-frequency division signal to output an inverse signal of the second sampling signal, and a dual-edge loop locking detection is adopted to reduce the false locking probability of the phase-locked loop circuit. The present invention provides a phase-locked loop circuit system.
Description
Technical Field
The present invention relates to the field of phase-locked loop technologies, and in particular, to a lock detection circuit and a phase-locked loop circuit system.
Background
Phase locked loop circuits are widely used in integrated circuits, wireless communications, wired transmission, sample and hold circuits, and the like.
At present, the Lock of the dual-loop phase-locked loop circuit is detected by a loop Lock detection circuit (Lock detector), as shown in fig. 1, the loop Lock detection circuit comprises a D flip-flop (DFF) and a Counter (Counter), a D input end of the D flip-flop is used for receiving a pre-divided signal ref, a clock end CK of the D flip-flop is used for receiving a feedback divided signal fbk, a Q output end of the D flip-flop is connected with an enable signal receiving end of the Counter, a D input end of the Counter is connected with a high level signal, a clock end CK of the Counter is used for receiving the feedback divided signal fbk, the loop Lock detection circuit samples the pre-divided signal through the feedback divided signal, and if the pre-divided signal is sampled to the high level for 2 N times continuously, the loop Lock detection circuit judges that the dual-loop phase-locked loop circuit is locked.
However, the time span of the detection signal of the existing dual-loop lock detection circuit is seriously dependent on the number of bits of the counter, the longer the duration of the signal to be detected is, the larger the number of bits of the counter is, after the dual-loop lock is locked, the waiting time required for detecting the dual-loop lock is correspondingly increased, if the duration of the detection signal is shorter, the situation as shown in fig. 2 may occur, the correct locking time of the dual-loop lock circuit is 32 μs, but the integral path voltage and the proportional path voltage in the dual-loop lock circuit are not established stably, i.e. the dual-loop lock circuit is not locked yet, and the dual-loop lock detection circuit already outputs a high level representing the locking of the dual-loop lock circuit.
Therefore, there is a need for a new lock detection circuit and a pll circuit system that solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a lock detection circuit and a phase-locked loop circuit system, which can reduce the false lock probability of the phase-locked loop circuit.
In order to achieve the above object, the lock detection circuit of the present invention is used for lock detection of a phase-locked loop circuit, and includes:
The first sampling unit is used for receiving the pre-frequency-division signal and the feedback frequency-division signal, and sampling the pre-frequency-division signal through the feedback frequency-division signal so as to output a first sampling signal;
The second sampling unit is used for receiving the reverse signal of the pre-frequency-division signal and the feedback frequency-division signal, and sampling the feedback frequency-division signal through the reverse signal of the pre-frequency-division signal so as to output the reverse signal of a second sampling signal;
and an AND gate connected with the first sampling unit and the second sampling unit to receive the inverse signals of the first sampling signal and the second sampling signal and output a control signal;
The counting unit is connected with the AND gate, and is used for receiving the feedback frequency division signal and the preset sampling signal simultaneously by taking the received control signal as an enabling signal, sampling the preset sampling signal through the feedback frequency division signal, and outputting a locking signal when the sampled number of the preset sampling signal reaches a preset value.
The lock detection circuit has the beneficial effects that the first sampling unit is used for receiving the pre-frequency dividing signal and the feedback frequency dividing signal, sampling the pre-frequency dividing signal through the feedback frequency dividing signal to output a first sampling signal, the second sampling unit is used for receiving the reverse signal of the pre-frequency dividing signal and the feedback frequency dividing signal, sampling the feedback frequency dividing signal through the reverse signal of the pre-frequency dividing signal to output the reverse signal of the second sampling signal, and double-edge loop lock detection is adopted to reduce the false lock probability of the phase-locked loop circuit.
Preferably, the first sampling unit is a D flip-flop, the D input end of the first sampling unit is configured to receive the pre-divided signal, and the clock end of the first sampling unit is configured to receive the feedback divided signal. The method has the advantage of facilitating sampling of the pre-divided signal by the rising edge of the feedback divided signal.
Further preferably, the second sampling unit is a D flip-flop, a D input end of the second sampling unit is configured to receive the feedback divided signal, and a clock end of the second sampling unit is configured to receive an inverse signal of the pre-divided signal. The feedback frequency division signal sampling method has the advantage that the feedback frequency division signal is conveniently sampled through the falling edge of the front frequency division signal.
Further preferably, the lock detection circuit further includes an inverter unit, an output terminal of the inverter unit is connected to the second sampling unit, and an input terminal of the inverter unit is used for receiving the prescaled signal. The method has the advantage that the reverse signal of the pre-frequency division signal is conveniently obtained.
Further preferably, a first input terminal of the and gate is connected to the Q output terminal of the first sampling unit, and a second input terminal of the and gate is connected to the QN output terminal of the second sampling unit.
The invention also provides a phase-locked loop circuit system, comprising:
a phase-locked loop circuit;
and the lock detection circuit is connected with the phase-locked loop circuit and used for detecting the lock of the phase-locked loop circuit.
The phase-locked loop circuit system has the beneficial effects that the lock detection circuit is connected with the phase-locked loop circuit to detect whether the phase-locked loop circuit is locked or not, and the false lock probability of the phase-locked loop circuit is reduced by adopting double-edge loop lock detection.
Preferably, the phase-locked loop circuit comprises an oscillator unit, a prescaler unit, a phase frequency detector unit, a charge pump unit, a voltage-controlled oscillator unit and a feedback frequency divider unit, wherein the oscillator unit is connected with the prescaler unit, the prescaler unit is connected with the phase frequency detector unit and the lock detection circuit and is used for outputting a prescaler signal, the phase frequency detector unit is connected with the charge pump unit, the charge pump unit is connected with the voltage-controlled oscillator unit, the voltage-controlled oscillator unit is connected with the feedback frequency divider unit, and the feedback frequency divider unit is connected with the phase frequency detector unit and the lock detection circuit and is used for outputting a feedback frequency division signal.
Further preferably, the prescaler unit and the feedback divider unit are both falling edge count dividers or rising edge count dividers.
Further preferably, the duty cycle of the feedback frequency division signal output by the feedback frequency divider unit is less than 50%.
Drawings
FIG. 1 is a schematic diagram of a prior art loop lock detection circuit;
FIG. 2 is a graph of the integrated path voltage, the proportional path voltage and the counter output signal in the prior art;
FIG. 3 is a schematic diagram of the phase locked loop circuitry of the present invention;
FIG. 4 is a schematic diagram of a PLL circuit of the present invention;
FIG. 5 is a schematic diagram of waveforms of an input signal and a feedback divided signal of the feedback divider unit according to the present invention;
FIG. 6 is a schematic diagram of waveforms of a pre-divide signal and a feedback divide signal according to the present invention;
FIG. 7 is a schematic diagram of a lock detection circuit of the present invention;
FIG. 8 is a graph showing the integrated path voltage, the proportional path voltage and the output signal of the counting unit according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
In view of the problems existing in the prior art, an embodiment of the present invention provides a phase-locked loop circuit system, referring to fig. 3, the phase-locked loop circuit system 100 includes a phase-locked loop circuit 101 and a lock detection circuit 102, where the lock detection circuit 102 is connected to the phase-locked loop circuit 101, and is used for lock detection of the phase-locked loop circuit 101.
Fig. 4 is a schematic diagram of a pll circuit according to the present invention. Referring to fig. 4, the phase-locked loop circuit 101 includes an oscillator unit 1011, a prescaler unit 1012, a phase-frequency detector unit 1013, a charge pump unit 1014, a voltage-controlled oscillator unit 1015, and a feedback divider unit 1016, wherein the oscillator unit 1011 is connected to the prescaler unit 1012, the prescaler unit 1012 is connected to the phase-frequency detector unit 1013 and the lock detection circuit (not shown) for outputting a prescaler signal ref, the phase-frequency detector unit 1013 is connected to the charge pump unit 1014, the charge pump unit 1014 is connected to the voltage-controlled oscillator unit 1015, the voltage-controlled oscillator unit 1015 is connected to the feedback divider unit 1016, and the feedback divider unit 1016 is connected to the phase-frequency detector unit 1013 and the lock detection circuit for outputting a feedback divider signal fbk.
Referring to fig. 4, the charge pump unit 1014 includes an integrating circuit 10141 and a proportional circuit 10142, and the integrating circuit 10141 and the proportional circuit 10142 are well known in the art and will not be described in detail herein.
In some embodiments, when the phase-locked loop circuit is applied to a port of the MIPI D-PHY protocol, the reference frequency input by the phase-locked loop circuit is 266MHz, and the output frequency of the phase-locked loop circuit is 600MHz to 1.5ghz, which can be seen that the output frequency of the phase-locked loop circuit is higher than the reference frequency input by the phase-locked loop circuit.
In some embodiments, the output frequencies of the prescaler unit and the feedback divider unit are equal, for example, the reference frequency input by the phase-locked loop circuit is 266MHz, the output frequency is 1.07GHz, the output frequency after being divided by the prescaler unit is 133MHz, and the output frequency after being divided by the feedback divider unit is 133MHz.
In some embodiments, the prescaler unit and the feedback divider unit are both a falling edge count divider or a rising edge count divider, and the duty cycle of the feedback divided signal output by the feedback divider unit is less than 50%
In some embodiments, taking the falling edge count frequency divider as an example, the working principle of the falling edge count frequency divider can be known, where the width of a high level of the output signal of the falling edge count frequency divider is related to the frequency of the input signal, and the higher the frequency of the input signal, the narrower the width of a high level of the output signal.
Fig. 5 is a schematic waveform diagram of an input signal and a feedback divided signal of the feedback divider unit according to the present invention. Referring to fig. 5, the feedback frequency-divided signal is formed by dividing the input signal by 10, wherein the width of one high level signal of the feedback frequency-divided signal is equal to the width of one period of the input signal, and the width of one low level signal of the feedback frequency-divided signal is equal to the width of 9 periods of the input signal.
In some embodiments, the output frequency of the pll circuit is higher than the reference frequency of the pll circuit input, and therefore, a high level of the prescaled signal has a width greater than a high level of the feedback signal.
Fig. 6 is a schematic waveform diagram of a pre-divided signal and a feedback divided signal according to the present invention. Referring to fig. 6, the diagram includes a pre-divided signal and a feedback divided signal, the pre-divided signal and the feedback divided signal have the same frequency, and the feedback divided signal has a high level width smaller than that of the pre-divided signal. If the phase-locked loop circuit is locked, a rising edge of the feedback frequency-dividing signal corresponds to a high level of the pre-frequency-dividing signal, and a falling edge of the pre-frequency-dividing signal corresponds to a low level of the feedback frequency-dividing signal.
In some embodiments, the lock detection circuit includes a first sampling unit, a second sampling unit, an AND gate, and a counting unit. The first sampling unit is used for receiving a pre-frequency dividing signal and a feedback frequency dividing signal, sampling the pre-frequency dividing signal through the feedback frequency dividing signal to output a first sampling signal, the second sampling unit is used for receiving an inverse signal of the pre-frequency dividing signal and the feedback frequency dividing signal, sampling the feedback frequency dividing signal through the inverse signal of the pre-frequency dividing signal to output an inverse signal of a second sampling signal, the AND gate is connected with the first sampling unit and the second sampling unit to receive the inverse signal of the first sampling signal and the second sampling signal and output a control signal, the counting unit is connected with the AND gate and is used for taking the received control signal as an enabling signal, receiving the feedback frequency dividing signal and a preset sampling signal at the same time, sampling the preset sampling signal through the feedback frequency dividing signal and outputting a locking signal when the sampled number of the preset sampling signal reaches a preset value.
In some embodiments, the predetermined sampling signal is a high level signal or a low level signal, and the counting unit is well known in the art, and is not described in detail herein, for example, a counter in the loop lock detection circuit.
In some embodiments, the lock detection circuit further includes an inverter unit, an output terminal of the inverter unit is connected to the second sampling unit, and an input terminal of the inverter unit is configured to receive the prescaled signal.
FIG. 7 is a schematic diagram of a lock detection circuit according to the present invention. In fig. 7, the lock detection circuit 102 includes a first sampling unit 1021, an inverter unit 1022, a second sampling unit 1023, an and gate 1024, and a counting unit 1025, where the first sampling unit 1021 and the second sampling unit 1023 are both D flip-flops, a D input terminal of the first sampling unit 1021 is configured to receive the pre-divided signal ref, a clock terminal ck of the first sampling unit 1021 is configured to receive the feedback divided signal fbk, an input terminal of the inverter unit 1022 is configured to receive the pre-divided signal ref, an output terminal of the inverter unit 1022 is connected to a clock terminal ck of the second sampling unit 1023, so as to send a signal inverse to the clock terminal ck of the second sampling unit 1023, a D input terminal of the second sampling unit 1023 is configured to receive the feedback divided signal fbk, a first input terminal of the and gate 1024 is connected to a Q output terminal of the first sampling unit 1021, a second input terminal of the and the second input terminal 1024 is connected to the Q output terminal of the second sampling unit 1023, and the output terminal of the and the gate 1025 is configured to output a signal with a high-level signal, and the counter signal is configured to be a signal with a high value when the signal is sampled by the pre-divided by the and the gate 1023.
Referring to fig. 4 and 7, the D input terminal of the first sampling unit 1021 is connected to the output terminal of the prescaler unit 1012 to receive the prescaler signal ref output from the prescaler unit 1012, the clock terminal ck of the second sampling unit 1023 is connected to the output terminal of the feedback divider unit 1016 to receive the feedback divided signal fbk output from the feedback divider unit 1016, the D input terminal of the second sampling unit 1023 is connected to the output terminal of the feedback divider unit 1016 to receive the feedback divided signal fbk output from the feedback divider unit 1016, and the input terminal of the inverter unit 1022 is connected to the output terminal of the prescaler unit ref to receive the prescaler signal ref output from the prescaler unit 1012.
Referring to fig. 7, the first sampling unit 1021 samples the pre-divided signal ref through a rising edge of the feedback divided signal fbk, outputs a high level if sampled to a high level, and outputs a low level if sampled to a low level.
Referring to fig. 7, the second sampling unit 1023 samples the feedback divided signal fbk through a rising edge of a reverse signal of the pre-divided signal ref, that is, the second sampling unit 1023 samples the feedback divided signal fbk through a falling edge of the pre-divided signal ref, if sampled to a high level, the QN output terminal of the second sampling unit 1023 outputs a low level, and if sampled to a low level, the QN output terminal of the second sampling unit 1023 outputs a high level.
Referring to fig. 7, if the Q output terminal of the first sampling unit 1021 outputs a high level and the QN terminal of the second sampling unit 1023 outputs a high level, the control signal output from the and gate 1024 is a high level, the high level is used as the enable signal of the counting unit 1025, the counting unit 1025 operates to sample the high level by the rising edge of the feedback frequency division signal fbk, and the sampled number of the high level signal is increased by 1 every time the high level is sampled.
Referring to fig. 7, if the Q output terminal of the first sampling unit 1021 outputs a low level, which represents a low level sampled to the pre-divided signal ref through the rising edge of the feedback divided signal fbk, and thus represents that the phase-locked loop circuit 101 is not locked, the control signal output from the and gate 1024 must be a low level, the low level serves as the enable signal of the counting unit 1025, the counting unit 1025 is reset, and the counting unit 1025 re-counts.
Referring to fig. 7, if the QN output terminal of the second sampling unit 1023 outputs a low level, which represents that the rising edge of the inverted signal of the pre-divided signal ref is sampled to the high level of the feedback divided signal fbk, which is also equivalent to the falling edge of the pre-divided signal ref is sampled to the high level of the feedback divided signal fbk, and thus represents that the phase-locked loop circuit 101 is not locked, the control signal output from the and gate 1024 must be a low level, which is used as the enable signal of the counting unit 1025, the counting unit 1025 is reset, and the counting unit 1025 re-counts.
FIG. 8 is a graph showing the integrated path voltage, the proportional path voltage and the output signal of the counting unit according to the present invention. Referring to fig. 8, it can be seen that after the integrated and proportional path voltages are established stable, i.e., at 32 μs, the counting unit issues a high-level lock signal, which represents that the phase-locked loop circuit is locked, and does not issue a false-lock high-level lock signal before the integrated and proportional path voltages are established stable.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (7)
1. A lock detection circuit for lock detection of a phase locked loop circuit, comprising:
The sampling device comprises a first sampling unit, a second sampling unit and a first sampling unit, wherein the first sampling unit is a D trigger, the D input end of the first sampling unit is used for receiving a pre-frequency-division signal, the clock end of the first sampling unit is used for receiving a feedback frequency-division signal, and the pre-frequency-division signal is sampled through the rising edge of the feedback frequency-division signal so as to output a first sampling signal;
The second sampling unit is a D trigger, the D input end of the second sampling unit is used for receiving the feedback frequency division signal, the clock end of the second sampling unit is used for receiving the reverse signal of the pre-frequency division signal, and the feedback frequency division signal is sampled through the reverse signal of the pre-frequency division signal so as to output the reverse signal of the second sampling signal;
and an AND gate connected with the first sampling unit and the second sampling unit to receive the inverse signals of the first sampling signal and the second sampling signal and output a control signal;
The counting unit is connected with the AND gate, and is used for receiving the feedback frequency division signal and the preset sampling signal simultaneously by taking the received control signal as an enabling signal, sampling the preset sampling signal through the feedback frequency division signal, and outputting a locking signal when the sampled number of the preset sampling signal reaches a preset value.
2. The lock detection circuit of claim 1, further comprising an inverter unit, an output of the inverter unit being coupled to the second sampling unit, an input of the inverter unit being configured to receive the prescaled signal.
3. The lock detection circuit of claim 1, wherein a first input of the and gate is connected to the Q output of the first sampling unit and a second input of the and gate is connected to the QN output of the second sampling unit.
4. A phase locked loop circuitry comprising:
a phase-locked loop circuit;
The lock detection circuit according to any one of claims 1 to 3, connected to the phase-locked loop circuit, for lock detection of the phase-locked loop circuit.
5. The phase-locked loop circuitry of claim 4, wherein the phase-locked loop circuitry comprises an oscillator unit, a prescaler unit, a phase frequency detector unit, a charge pump unit, a voltage controlled oscillator unit, and a feedback divider unit, the oscillator unit being coupled to the prescaler unit, the prescaler unit being coupled to the phase frequency detector unit and the lock detection circuit for outputting a prescaled signal, the phase frequency detector unit being coupled to the charge pump unit, the charge pump unit being coupled to the voltage controlled oscillator unit, the voltage controlled oscillator unit being coupled to the feedback divider unit, the feedback divider unit being coupled to the phase frequency detector unit and the lock detection circuit for outputting a feedback divided signal.
6. The phase locked loop circuitry of claim 5, wherein the prescaler unit and the feedback divider unit are each a falling edge count divider or a rising edge count divider.
7. The phase-locked loop circuitry of claim 6 wherein the duty cycle of the feedback divided signal output by the feedback divider unit is less than 50%.
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| KR101960184B1 (en) * | 2017-09-11 | 2019-03-19 | 한양대학교 산학협력단 | Phase locked loop with high bandwidth using dual edge of signal |
| CN110224697A (en) * | 2019-06-18 | 2019-09-10 | 苏州兆凯电子有限公司 | A kind of phase lock loop locks method, circuit and transceiver communication system |
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| KR20020042161A (en) * | 2000-11-30 | 2002-06-05 | 박종섭 | Lock detection circuit for pll circuit |
| KR20080077515A (en) * | 2007-02-20 | 2008-08-25 | 엠텍비젼 주식회사 | Phase locking detection method and phase locked loop circuit for performing the same |
| KR101701641B1 (en) * | 2015-10-15 | 2017-02-02 | 한양대학교 산학협력단 | Phase locked loop with high bandwidth using rising edge and falling edge of signal |
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| KR101960184B1 (en) * | 2017-09-11 | 2019-03-19 | 한양대학교 산학협력단 | Phase locked loop with high bandwidth using dual edge of signal |
| CN110224697A (en) * | 2019-06-18 | 2019-09-10 | 苏州兆凯电子有限公司 | A kind of phase lock loop locks method, circuit and transceiver communication system |
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