CN113659434B - Manufacturing method of VCSEL chip without Mesa - Google Patents
Manufacturing method of VCSEL chip without Mesa Download PDFInfo
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- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000001259 photo etching Methods 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 238000004544 sputter deposition Methods 0.000 claims description 12
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 238000009616 inductively coupled plasma Methods 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
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- 239000007789 gas Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims 1
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- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
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- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18344—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] characterized by the mesa, e.g. dimensions or shape of the mesa
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
- H01S5/18322—Position of the structure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention discloses a manufacturing method of a VCSEL chip without a Mesa, and relates to the technical field of vertical cavity surface emitting lasers. The invention discloses a manufacturing method of a VCSEL chip without a Mesa, which is characterized in that a photoelectric limiting layer is deposited on the surface of a quantum well after the growth of the quantum well is finished, then the photoelectric limiting layer is subjected to photoetching and etching to define a light emitting region, and the photoelectric limiting layer is made of aluminum oxide. According to the manufacturing method of the VCSEL chip without the Mesa, the traditional oxidation or ion implantation process is omitted in the whole production process, the equipment investment in the VCSEL chip preparation process can be reduced, the whole process flow is shortened, the production time can be effectively shortened, the production efficiency is improved, and the production cost is reduced.
Description
Technical Field
The invention relates to the technical field of vertical cavity surface emitting lasers, in particular to a manufacturing method of a VCSEL chip without a Mesa.
Background
A vertical cavity surface emitting laser chip (VCSEL for short) is a semiconductor laser chip whose laser light is emitted perpendicularly to the top surface. The existing VCSEL chip is mainly prepared by sequentially growing an N-DBR layer, a quantum well, an oxidation layer and a P-DBR layer on a substrate by MOCVD (metal organic chemical vapor deposition), making P-metal ohmic contact through photoetching coating of the chip, making a chip mesa structure through photoetching etching for protecting the coating, feeding the chip into an oxidation furnace to oxidize the oxidation layer to form photoelectric limitation, then coating an insulation film for protecting the chip, opening an electrode channel through photoetching etching, thickening the P-metal through photoetching electroplating after making a seed layer, finally opening a light outlet of the chip through wet etching, making photoetching etching of a cutting channel, and finally grinding and shearing a thin wafer to make a back metal N-metal to finish the whole processing process. The VCSEL chip manufacturing process by the method is complicated in flow, 5-6 steps are needed for photoetching, the overall process is small, the process steps are about 70 steps in a large summary, a large amount of time is needed in the overall process, and more devices need to be purchased, so that the production cost is high.
Disclosure of Invention
In view of the above problems, the present invention is directed to a method for manufacturing a VCSEL chip without Mesa, which omits a conventional oxidation or ion implantation process in the whole production process, reduces the equipment investment in the VCSEL chip preparation process, shortens the whole process flow, effectively shortens the production time, improves the production efficiency, and reduces the production cost.
Specifically, according to the manufacturing method of the VCSEL chip without the Mesa, a photoelectric limiting layer is deposited on the surface of the quantum well after the quantum well grows, and then photoetching and etching are carried out on the photoelectric limiting layer to define a light emitting region.
Further, the photoelectric limiting layer is made of aluminum oxide.
Further, the photoelectric limiting layer is obtained by deposition through a magnetron sputtering or atomic layer deposition method.
Furthermore, the thickness of the photoelectric limiting layer is 20-40nm. Preferably 30nm.
Further, the manufacturing method specifically comprises the following steps:
providing a GaAs substrate;
sequentially growing an N-DBR structure and a quantum well on the GaAs substrate;
depositing a photoelectric limiting layer on the surface of the quantum well to obtain a pattern, etching the photoelectric limiting layer to form a through hole by etching, and defining a light emitting area;
growing a P-DBR structure on the surface of the photoelectric limiting layer by using MOCVD;
depositing and covering a silicon nitride layer on the surface of the P-DBR structure to be used as a protective film;
etching an electrode position on the SiNx layer;
evaporating P-contact on the P surface;
bonding and binding the P surface of the wafer and the sapphire, and grinding and thinning the N surface;
and evaporating and plating an N-metal electrode on the N surface of the wafer, annealing and unbinding, and scribing to obtain the VCSEL chip.
Further, the step S3 is specifically operative to: and (2) feeding the wafer with the quantum well grown in the step (S2) into an RF magnetron sputtering machine, vacuumizing the RF magnetron sputtering machine, introducing argon and oxygen into the machine, controlling the sputtering pressure and sputtering power of the machine to deposit on the surface of the quantum well to obtain a photoelectric limiting layer, coating photoresist on the surface of the photoelectric limiting layer in a spinning mode, baking, exposing and developing to obtain a luminous zone pattern, etching the photoelectric limiting layer according to the luminous zone pattern by utilizing ICP (inductively coupled plasma) etching, etching a plurality of through holes on the photoelectric limiting layer, and cleaning and removing redundant photoresist after etching is finished.
Further, the flow rate of the argon is 40-60ml/min, the flow rate of the oxygen is 1-10ml/min, the sputtering pressure during sputtering is 0.5-5pa, and the sputtering power is 70W.
Further, when light emitting area patterns are formed on the photoelectric limiting layer, positive photoresist is spin-coated, glue is evenly coated at the rotating speed of 800-1200r/min during glue coating, the time is 20-60s, the baking temperature is 80-120 ℃, the time is 60-120s, the exposure energy is 80mj/c square meter, and the exposure time is 15-45s.
Further, the diameter of the through hole is 8-12 μm.
Further, the N-DBR structure comprises 30 pairs of Ga materials 0.1 Al 0.9 As/Ga 0.9 Al 0.1 A DBR layer of As, the P-DBR structure comprises 22 pairs of Ga 0.1 Al 0.9 As/Ga 0.9 Al 0.1 DBR layer of As.
The invention has the beneficial effects that:
1. the invention discloses a method for manufacturing a VCSEL chip without a Mesa, wherein aluminum oxide is directly deposited to form a photoelectric limiting layer in the process of substrate growth.
2. The method for manufacturing the VCSEL chip does not need to be oxidized, so that the core particles do not need to be manufactured into a mesa structure, and the surface of the whole wafer is flat because the mesa structure is not arranged, so that the whole wafer is relatively easy to process, and the requirements on a machine table are lower than those of the traditional process.
3. The VCSEL chip prepared by the preparation method of the invention has no mesa structure, so that the electrical parasitic parameters of the whole core particles can be reduced, and the electrical parasitic parameters are also the main limiting factors of VCSEL high-speed modulation, so that the VCSEL chip processed by the process has higher modulation frequency, and the high-speed VCSEL chip can be manufactured.
Drawings
Fig. 1 to fig. 6 are schematic structural diagrams corresponding to steps in a method for manufacturing a VCSEL chip without Mesa according to the present invention;
FIG. 7 is an SEM image of a VCSEL chip prepared according to an embodiment of the invention;
FIG. 8 is an SEM image of a VCSEL chip prepared by a conventional method in a comparative example;
the semiconductor structure comprises a GaAs substrate 1, an N-DBR structure 2, a quantum well 3, a photoelectric limiting layer 4, a through hole 5, a P-DBR structure 6, a silicon nitride layer 7, a groove 8, a P-contact 9 and an N-metal electrode 10.
Detailed Description
The present invention will be described in detail with reference to specific examples below:
examples
S1: providing a GaAs substrate 1;
s2: 30 pairs of Ga materials are grown on the GaAs substrate 1 by overlapping by a conventional method by using MOCVD 0.1 Al 0.9 As/Ga 0.9 Al 0.1 Obtaining N-DBR structures 2 by using the DBR layers of As, wherein the thickness of each DBR layer is 1/4 of the lasing wavelength, and growing quantum wells 3 made of InGaAs/AlGaAs on the surfaces of the N-DBR structures 2;
s3: directly feeding the wafer with the quantum well grown in the step S2 into an RF (radio frequency) magnetron sputtering machine, taking alpha-Al 2O3 as a target material, and pumping the vacuum degree in the machine to 10 × E -3 pa, introducing argon gas at the flow rate of 40-60ml/min into an RF magnetron sputtering machine, introducing oxygen at the flow rate of 1-10ml/min, controlling the sputtering pressure of the machine to be 0.5-5pa, and obtaining a photoelectric limiting layer 4 which is 30nm thick and is made of aluminum oxide on the surface of the quantum well 3 by magnetron sputtering with the sputtering power of 70W, wherein the material is shown in figure 1;
spin-coating positive photoresist on the surface of the photoelectric limiting layer 4 obtained by sputtering, spin-coating at the rotating speed of 800-1200r/min for 20-60s, baking at the temperature of 80-120 ℃ for 60-120s, exposing at the exposure energy of 80mj/c for 15-45s, spin-coating developing solution at the rotating speed of 800-1000r/min for developing to obtain luminous zone patterns, wherein the diameter of each small luminous zone is 8-12 μm, each 100 luminous zones are formed into an array, ICP etching is adopted, and BCl is selected as process gas 3 The gas flow is 50-100sccm, the process pressure is 0.5pa,etching under the conditions that ICP power is 800-1200W and bias power is 200-400W, etching a plurality of through holes 5 with the diameter of 8-12 mu m on the photoelectric limiting layer 4, immediately etching a light emitting area, realizing P-surface and N-surface circuit intercommunication, defining a light emitting area, timely finding an etching end point by monitoring the variation of Ai element closing lines during etching, preventing over-etching, and cleaning by using an organic solvent to remove redundant photoresist after etching is finished to obtain the photoresist shown in figure 2.
S4: using MOCVD, 22 pairs of Ga are grown on the surface of the photoelectric confinement layer 4 in an overlapping manner by the conventional method 0.1 Al 0.9 As/Ga 0.9 Al 0.1 The DBR layer of As to obtain a P-DBR structure 6, each DBR layer has a thickness of 1/4 of the lasing wavelength, and a highly carbon-doped GaAs layer is grown on the uppermost layer, with a doping concentration of 1 × 10 20 /㎝ 3 So as to facilitate the subsequent ohmic contact of the electrode, as shown in FIG. 3;
s5: depositing and covering a silicon nitride layer 7 on the surface of the P-DBR structure 6 by using a PECVD (plasma enhanced chemical vapor deposition) method by adopting a conventional method to serve as a protective film so as to protect the whole wafer;
s6: patterning the silicon nitride layer 7 by photolithography, etching an annular groove 8 in the silicon nitride layer by etching, and removing photoresist after etching is completed, as shown in fig. 4;
s7: and photoetching again, performing photoresist shielding on a light-emitting area, then evaporating and plating P-metal on a P surface through electron beam evaporation, and stripping the redundant photoresist and metal by using Lift-off to form P-contact 9 as shown in figure 5.
S8: bonding and binding a P surface of the wafer and the sapphire, grinding and thinning an N surface, wherein the specific thickness can be selected according to actual needs;
s9: and (3) evaporating and plating an N-metal electrode 10 on the N surface of the wafer, annealing and unbinding, and scribing to obtain the VCSEL chip.
Comparative example
The comparative example adopts the existing preparation method of the Vcsel chip, and specifically comprises the following steps:
s1: providing a GaAs substrate;
s2: sequentially growing an N-DBR structure, a quantum well, an oxide layer and a P-DBR structure in an overlapping manner on the GaAs substrate;
s3: p-metal photoetching is carried out on the wafer, then metal is deposited through electron beam evaporation to form P-contact, and the wafer is sent to a metal stripping cleaning machine to strip redundant metal.
S4: the wafer is sent to a PECVD machine to deposit a silicon nitride protection layer.
S5: and continuing to send the wafer to yellow light for mesa photoetching.
S6: etching the P-DBR structure to expose the oxide layer, oxidizing the oxide layer by wet oxidation process to reach photoelectric limit effect and define light emitting region,
s7: the wafer is again sent to PECVD for silicon nitride deposition.
S8: and (3) sending the wafer to yellow light again, finishing the planarization of the wafer in the yellow light, spin-coating BCB on the wafer, exposing and developing the BCB to enable the surface of the wafer to be relatively flat, and finally baking and hardening the film to finish the planarization of the BCB.
S9: and after the VIA photoetching of the channel above the electrode ring is completed by photoetching again, conveying the wafer to an etching room, and etching silicon nitride above the P-contact metal.
S10: and magnetron sputtering to form a seed layer of Au metal on the whole wafer.
S11: and (4) carrying out photoetching on the wafer, continuing to carry out metal thickening photoetching, keeping the photoresist in the light-emitting area, and exposing the rest parts.
S12: plating Au thickened wafer connecting metal on the wafer, then adopting organic photoresist removal, and then etching the seed layer metal in the light emitting region by a wet method.
S13: the wafer is again photo-etched and then etched, and each core grain on the surface of the wafer is etched and separated.
S14: bonding and binding the P surface of the wafer and the sapphire, grinding and thinning the N surface, wherein the specific thickness can be selected according to actual needs;
s15: and (4) evaporating and plating an N-metal electrode on the N surface of the wafer, annealing and unbinding, and scribing to obtain the VCSEL chip.
Through comparison between a comparative example and an embodiment, it is obvious that the preparation method provided by the invention is greatly reduced in operation steps, oxidation or ion implantation technology is not used in the whole process, the whole process of the preparation method provided by the invention only needs 3 times of photoetching, 2 times of etching, 1 time of PECVD coating, 2 times of metal coating, 1 time of magnetron sputtering or atomic deposition coating to complete the whole process, and the preparation of the VCSEL chip with the traditional Mesa structure in the comparative example usually needs 5-6 times of photoetching, 4-5 times of etching, 2-4 times of PECVD coating and 3 times of metal coating.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present invention, which is defined by the claims appended hereto. The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.
Claims (8)
1. A manufacturing method of a VCSEL chip without a Mesa is characterized in that a photoelectric limiting layer is deposited on the surface of a quantum well after the growth of the quantum well is completed, and then the photoelectric limiting layer is subjected to photoetching and etching to define a light emitting region; the manufacturing method specifically comprises the following steps: s1: providing a GaAs substrate;
s2: sequentially growing an N-DBR structure and a quantum well on the GaAs substrate;
s3: depositing a photoelectric limiting layer on the surface of the quantum well to obtain a pattern, etching the photoelectric limiting layer to form a through hole by etching, and defining a light emitting area; s3, the specific operation of the step is as follows: feeding the wafer with the quantum well grown in the step S2 into an RF magnetron sputtering machine, vacuumizing the RF magnetron sputtering machine, introducing argon and oxygen into the machine, controlling the sputtering pressure and sputtering power of the machine to deposit on the surface of the quantum well to obtain a photoelectric limiting layer, coating photoresist on the surface of the photoelectric limiting layer in a spinning mode, baking, exposing and developing to obtain a luminous zone pattern, etching the photoelectric limiting layer by utilizing ICP (inductively coupled plasma) according to the luminous zone pattern, etching a plurality of through holes on the photoelectric limiting layer, and cleaning and removing redundant photoresist after etching is finished;
s4: growing a P-DBR structure on the surface of the photoelectric limiting layer by using MOCVD;
s5: depositing and covering a silicon nitride layer on the surface of the P-DBR structure to be used as a protective film;
s6: etching an electrode position on the silicon nitride layer;
s7: evaporating P-contact on the P surface;
s8: bonding and binding the P surface of the wafer and the sapphire, and grinding and thinning the N surface;
s9: and evaporating and plating an N-metal electrode on the N surface of the wafer, annealing and unbinding, and scribing to obtain the VCSEL chip.
2. The method of claim 1, wherein the material of the optical confinement layer is alumina.
3. The method of claim 2, wherein the optical confinement layer is deposited by magnetron sputtering or atomic layer deposition.
4. The method of claim 3, wherein the thickness of the optical confinement layer is 20-40nm.
5. The method as claimed in claim 1, wherein the flow rate of argon is 40-60ml/min, the flow rate of oxygen is 1-10ml/min, the sputtering pressure is 0.5-5pa, and the sputtering power is 70W.
6. The method for manufacturing a VCSEL chip without a Mesa Mesa according to claim 1, wherein when light emitting region patterns are formed on the photoelectric limiting layer, positive photoresist is spin-coated, the photoresist is uniformly coated at the rotating speed of 800-1200r/min during coating, the coating time is 20-60s, the baking temperature is 80-120 ℃, the coating time is 60-120s, the exposure energy is 80mj/c square meter, and the exposure time is 15-45s.
7. The method of claim 1, wherein the ICP etching is BCl 3 The flow rate of the process gas is 50-100sccm, the process pressure is 0.5pa, the ICP power is 800-1200W, and the bias power is 200-400W.
8. A method of fabricating a VCSEL chip without a Mesa according to any of claims 1 to 7, wherein the via hole has a diameter of 8 to 12 μm.
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| CN108233176A (en) * | 2018-01-28 | 2018-06-29 | 海南师范大学 | A kind of electrical pumping GaN vertical-cavity surface emitting laser structures and preparation method thereof |
| CN112993750A (en) * | 2021-01-28 | 2021-06-18 | 华芯半导体科技有限公司 | VCSEL chip, preparation method thereof and laser scanning radar |
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