CN113644158B - Upper incident light type infrared sensor element and its manufacturing method - Google Patents

Abstract

Embodiments of the present invention disclose an upper incident light type infrared sensor element including at least one compound semiconductor stack capable of detecting infrared rays having a wavelength of 1 μm or more and outputting an electrical signal representing the detection, and a method of manufacturing the same; a substrate including an IC circuit that processes and computes an electric signal output from the at least one compound semiconductor stack to obtain a detection result; and an adhesive layer bonding the at least one compound semiconductor stack to a substrate containing an IC circuit. The electrode of the at least one compound semiconductor stack is electrically connected to a lead terminal of the IC circuit. The invention belongs to the technical field of semiconductors. The upper incident light type infrared sensor element can work at room temperature, is not easily influenced by dark current, electromagnetic noise and thermal fluctuation, and has a compact structure.

Description

Top-incident infrared sensor element and manufacturing method thereof

Technical Field

The disclosure of the present application relates to the field of semiconductor technology, and in particular to a top-incident infrared sensor element and a corresponding manufacturing method.

Background technique

Infrared sensors have been widely used in various fields, such as human sensors that automatically turn on and off household appliances such as lighting, air conditioning, and televisions by detecting people, as well as surveillance sensors for prevention, etc. In addition, infrared sensors can also be used to detect the leakage of flammable and explosive gases such as methane.

One type of existing infrared sensor is a pyroelectric infrared sensor that uses the pyroelectric effect. Since the pyroelectric element has a very high impedance, it is easily affected by electromagnetic noise and thermal fluctuations. Therefore, it needs to be shielded by a metal shell package. In addition, the I-V conversion circuit must have large resistance and capacitance, so it is difficult to miniaturize.

Another type of infrared sensor is the quantum type, and HgCdTe (MCT) and InSb series are commonly used materials. The sensor must be cooled using liquid nitrogen, liquid helium, or electronic cooling using the Peltier effect. Generally, quantum infrared sensors can achieve a sensitivity 100 times or more of that of thermoelectric sensors. In addition, the element resistance can be as small as tens to hundreds of ohms, and is rarely affected by electronic noise and thermal fluctuations. However, for packaging, since it must be cooled to a low temperature, a strong metal package must be used.

For the InSb series, mixed crystal layers of InAs _x Sb _1-x are studied according to the wavelength to be detected. For example, an epitaxial growth method is attempted using an InSb substrate and replacing a portion of InSb with As.

In addition, a monolithic structure using an infrared sensor part grown on a substrate integrated with a readout and signal processing circuit is proposed. However, the technology of growing a compound semiconductor thin film as the core of the infrared sensor on a signal processing circuit is extremely difficult, and it is not easy to obtain a film that can be used as a practical device. The heat generated when the signal processing circuit is running becomes noise to the thermal fluctuation of the infrared sensor part formed thereon in a monolithic manner, and the problem of generating an erroneous signal occurs. Therefore, in order to suppress the influence of this thermal fluctuation, the entire sensor must be cooled using liquid nitrogen or the like. Such cooling limits the use of infrared sensors.

Summary of the invention

In view of the above, an object of the present invention is to provide a compact top-illuminated infrared sensor element that can operate at room temperature and is not easily affected by dark current, electromagnetic noise, and thermal fluctuations, and a method for manufacturing the same.

The inventors of the present invention have found that by reducing the resistance of the compound semiconductor stack, reducing the surface defect density of the infrared photon absorption stack to less than 100/ ^cm2 , and integrating the compound semiconductor stack and the integrated circuit that processes the electrical signal output from the compound semiconductor stack on the same substrate and encapsulating them in the same package, detection can be performed at room temperature. In addition, in this way, the infrared sensor of the present invention can be made less susceptible to dark current, electromagnetic noise and thermal fluctuations. In the present invention, the resistance of the compound semiconductor stack in the infrared sensor circuit can be made small, and the resistance and capacitance in the signal output circuit can be very small, thereby allowing the miniaturization of the top-input infrared sensor element.

According to one aspect of the present invention, there is provided a top-light type infrared sensor element, the top-light type infrared sensor element comprising:

at least one compound semiconductor stack capable of detecting infrared light having a wavelength of 1 micrometer or more and outputting an electrical signal indicative of the detection;

A substrate containing an IC circuit, wherein the IC circuit processes an electrical signal output from the at least one compound semiconductor stack and performs calculations to obtain a detection result;

an adhesive layer that bonds at least one compound semiconductor stack to a substrate containing an IC circuit;

Wherein, the electrode of the at least one compound semiconductor stack is electrically connected to the lead terminal of the IC circuit.

In one example, one of the at least one compound semiconductor stack includes, from top to bottom, an N-type electrode, an N-type electrode ohmic contact and current conduction layer, a P-N or P-i-N type photon absorption layer, a carrier blocking layer, a P-type electrode ohmic contact and current conduction layer, and a P-type electrode located on a portion of the P-type electrode ohmic contact and current conduction layer.

In one example, the P-type electrode ohmic contact and current conducting layer includes a first P-type electrode ohmic contact and current conducting layer and a second P-type electrode ohmic contact and current conducting layer, the first P-type electrode ohmic contact and current conducting layer is located on the second P-type electrode ohmic contact and current conducting layer, the size of the second P-type electrode ohmic contact and current conducting layer is larger than the first P-type electrode ohmic contact and current conducting layer, and a P-type electrode is disposed on a portion of the second P-type electrode ohmic contact and current conducting layer not covered by the first P-type electrode ohmic contact and current conducting layer;

The electrical connection between the N-type electrode and the negative lead terminal of the IC circuit and the electrical connection between the P-type electrode and the positive lead terminal of the IC circuit are connected by metal wire bonding or multi-layer metal interconnection lines formed by photolithography.

In one example, the P-type electrode includes a metal electrode formed of Au, Ge, Ni, Ti, Cr, Cu or an alloy thereof;

The first P-type electrode ohmic contact and current conducting layer and the second P-type electrode ohmic contact and current conducting layer are p-type heavily doped compound semiconductor films;

The carrier blocking layer includes a p-type doped compound semiconductor film containing Ga, Al, In, Sb or As or a compound semiconductor film including Sb;

The P-N or P-i-N photon absorption layer comprises a P-N or P-i-N type lightly doped InSb, GaAs, InAs, InGaAs, GaAsSb or InGaP compound semiconductor film;

The N-type electrode ohmic contact and current conducting layer include an n-type heavily doped InSb, GaAs, InAs, InGaAs, GaAsSb or InGaP compound semiconductor film;

The N-type electrode includes a metal electrode formed of Au, Ge, Ni, Ti, Cr, Cu or an alloy thereof.

In one example, the compound semiconductor stack is manufactured by the following steps:

Hetero-epitaxially growing a plurality of compound semiconductor films on a semiconductor single crystal substrate in sequence, respectively forming an N-type electrode ohmic contact and current conducting layer containing a lattice buffer sacrificial layer, a P-N or P-i-N type photon absorption layer, a carrier blocking layer, a first P-type electrode ohmic contact and current conducting layer, and a second P-type electrode ohmic contact and current conducting layer;

Coating an adhesive layer on at least one of the second P-type electrode ohmic contact and the current conducting layer and the substrate, and bonding them face to face through the adhesive layer;

Selectively remove the lattice buffer sacrificial layer in the semiconductor single crystal substrate, N-type electrode ohmic contact and current conduction layer,

Among them, the semiconductor single crystal substrate adopts GaAs, InP, GaN or Si single crystal substrate, the compound semiconductor film includes InSb, GaAs, InAs, InGaAs, InAlSb, GaAsSb or InGaP, the bonding layer includes any one of silicon nitride film, silicon oxide film, aluminum oxide film, silicon oxynitride film, epoxy resin, silica gel, silicon dioxide and polyimide film, and the substrate includes any one of Si-based wafer containing IC circuit, quartz substrate, aluminum oxide substrate, aluminum nitride substrate, polyimide flexible substrate.

In one example, the mobility of the N-type electrode ohmic contact and the current conducting layer removed from the semiconductor single crystal substrate is greater than 40000 cm ² /Vs, and the thickness of the N-type electrode ohmic contact and the current conducting layer is 500 nm-10 μm;

At the same time, a lattice buffer sacrificial layer with poor lattice quality in the semiconductor single crystal substrate and the N-type electrode ohmic contact and the current conducting layer is removed, the mobility of the N-type electrode ohmic contact and the current conducting layer is greater than 50000 ^cm2 /Vs and less than 78000 ^cm2 /Vs, and the thickness of the N-type electrode ohmic contact and the current conducting layer is 100nm-9μm;

The surface defect density of the PN or PiN type photon absorption layer is less than or equal to 10-100/cm ² .

In one example, the top-incident infrared sensor element further includes a protection layer for covering the compound semiconductor stack, but at least a portion of the N-type electrode and the P-type electrode is exposed;

The protective layer includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silica gel, silicon dioxide, and a polyimide film.

In one example, the substrate containing the IC circuit is rigid or flexible;

A reflective film is also arranged between the substrate and the bonding layer.

In one example, the at least one compound semiconductor stack is arranged on the substrate in the form of a planar array, a linear array, or four quadrants.

According to another aspect of the present invention, there is provided a method for manufacturing a top-incident infrared sensor element, the method comprising:

manufacturing at least one compound semiconductor stack capable of detecting infrared light having a wavelength of 1 micrometer or more and outputting an electrical signal indicative of the detection;

Providing a substrate containing an IC circuit, wherein the IC circuit processes the electrical signal output from the at least one compound semiconductor stack and performs calculations to obtain a detection result;

Providing an adhesive layer to bond at least one compound semiconductor stack to a substrate containing an IC circuit;

Wherein, the electrode of the at least one compound semiconductor stack is electrically connected to the lead terminal of the IC circuit.

Other objects and advantages of the present disclosure will be apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments in conjunction with the accompanying drawings, in which:

FIG1 is a schematic diagram of a cross-sectional structure of a top-light-incident infrared sensor element according to an embodiment of the present invention;

FIG2A is a schematic diagram showing a cross-sectional structure of a compound semiconductor material stack having an infrared sensing function grown heteroepitaxially on a semiconductor single crystal substrate;

FIG2B shows a schematic cross-sectional structure diagram of manufacturing a reflective film on a substrate having an IC circuit;

FIG2C is a schematic diagram showing a cross-sectional structure after a bonding layer is applied to the structure of FIG2B ;

FIG2D is a schematic cross-sectional view showing the structure shown in FIG2A and the structure shown in FIG2C bonded together;

FIG2E is a schematic cross-sectional view of the structure of FIG2D after selectively removing the semiconductor single crystal substrate originally used for heteroepitaxial growth of the compound semiconductor stack and etching away a portion of the semiconductor stack;

FIG2F is a schematic diagram showing a cross-sectional structure of an electrode manufactured based on the structure of FIG2E ;

FIG. 2G is a schematic cross-sectional view showing a structure after manufacturing a protection layer based on the structure of FIG. 2F and electrically connecting the electrode of the compound semiconductor bottom layer to the lead terminal of the IC circuit.

Detailed ways

The technical solution of the present invention is further specifically described below by examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation of the present invention.

FIG1 shows a schematic cross-sectional structure diagram of a top-light-incident infrared sensor element according to an embodiment of the present invention. The top-light-incident infrared sensor element 100 includes a substrate 10 containing an IC circuit. For the sake of simplicity, the IC circuit on the substrate 10 is not shown, but the positive lead terminal 11 and the negative lead terminal 12 of the IC circuit are shown. A compound semiconductor stack is provided on the substrate 10 through an adhesive layer 30. The compound semiconductor stack can detect infrared rays with a wavelength greater than or equal to 1 micron and output an electrical signal representing the detection. The IC circuit processes the electrical signal output from the compound semiconductor stack and performs calculations to obtain a detection result.

In the example, the compound semiconductor stack is bonded to the substrate 10 containing the IC circuit through the bonding layer 30. The bonding layer 30 is "transparent" to infrared photons exceeding a specific wavelength according to the specific application, and includes any one of silicon nitride film, silicon oxide film, aluminum oxide film, silicon oxynitride film, epoxy resin, silica gel, silicon dioxide and polyimide film. The electrodes 13 and 14 of the compound semiconductor stack are electrically connected to the lead terminals 12 and 11 of the IC circuit respectively.

Optionally, a protective layer 80 may be provided, which covers the compound semiconductor stack but exposes at least a portion of the N-type electrode 13 and the P-type electrode 14. The protective layer 80 includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silica gel, silicon dioxide, and a polyimide film.

It should be noted that the compound semiconductor stack is a unit that detects incident infrared rays and outputs the detection result as an electrical signal, i.e., an infrared sensor. Since it is integrated with a substrate with an IC circuit in the present invention, an infrared sensor element is formed. The IC circuit is a circuit with multiple circuit elements formed on or inside the substrate 10, and is a unit that processes the detection signal (electrical signal) of infrared rays output from the compound semiconductor stack and performs a predetermined operation. In the embodiment, the present invention connects the IC circuit and the compound semiconductor stack to each other and integrates them on the same substrate by providing an adhesive layer 30.

In one example, the substrate 10 may include any one of a Si-based wafer of an IC circuit, other semiconductor substrates, a metal substrate, a quartz substrate, an aluminum oxide substrate, an aluminum nitride substrate, and a polyimide flexible substrate, and may be "transparent" to infrared light exceeding a specific wavelength depending on the specific application.

As shown in FIG1 , the compound semiconductor stack includes, from top to bottom, an N-type electrode 13, an N-type electrode ohmic contact and current conducting layer 70, a photon absorption layer 60, a carrier blocking layer (for suppressing dark current) 50, a P-type electrode ohmic contact and current conducting layer (in this example, the P-type electrode ohmic contact and current conducting layer include a first P-type electrode ohmic contact and current conducting layer 41 and a second P-type electrode ohmic contact and current conducting layer 42). The photon absorption layer 60 is, for example, a P-N type or P-i-N type photon absorption layer.

Considering that the subsequent compound semiconductor stack is reversed from the originally grown substrate and attached to the substrate 10, the size of the second P-type electrode ohmic contact and current conduction layer 42 is set to be larger than the first P-type electrode ohmic contact and current conduction layer 41, and a P-type electrode 14 is provided on the portion of the second P-type electrode ohmic contact and current conduction layer 42 not covered by the first P-type electrode ohmic contact and current conduction layer 41.

Combined with the subsequent description, it can be seen that through such a setting, a compound semiconductor stack can be formed by photolithography and etching after the substrate on which the compound semiconductor stack was originally grown is selectively removed. At the same time, the size of the second P-type electrode ohmic contact and the current conduction layer 42 can be set to be larger, thereby facilitating the setting of the P-type electrode 14.

It is understandable that only one integrated P-type electrode ohmic contact and current conduction layer may be provided, and in the subsequent etching process, a step portion is formed on which the P-type electrode 14 can be placed, and its shape is the same as or similar to the shape formed by stacking the first P-type electrode ohmic contact and current conduction layer 41 and the second P-type electrode ohmic contact and current conduction layer 42 together.

The N-type electrode 13 is electrically connected to the negative lead terminal 12 of the IC circuit through a metal wire, and similarly, the P-type electrode 14 is electrically connected to the positive lead terminal 11 of the IC circuit through a metal wire. Alternatively, the aforementioned electrical connection can also be achieved by a multi-layer metal interconnection formed by photolithography, thereby improving the reliability of the connection and simplifying the process.

In one example, the P-type electrode 14 includes a metal electrode formed of Au, Ge, Ni, Ti, Cr, Cu or an alloy thereof, preferably a Ti/Au metal electrode; the first P-type electrode ohmic contact and current conducting layer 41 and the second P-type electrode ohmic contact and current conducting layer 42 are p-type heavily doped compound semiconductor films, for example, p+InSb with a thickness of 0.5 μm; the carrier blocking layer 50 includes a p-type doped compound semiconductor film containing Ga, Al, In, Sb or As, preferably InAlSb, for example, p+Al _0.17 In _0.83 with a thickness of 50 nm. Sb or p+GaAsSb; the photon absorption layer 60 comprises a PN or PiN type lightly doped InSb, GaAs, InAs, InGaAs, GaAsSb or InGaP compound semiconductor film, for example, a p-InSb with a thickness of 1 μm or a p-InSb with a thickness of 1 μm plus an n-InSb with a thickness of 1 μm; the N-electrode ohmic contact and current conduction layer 70 comprises an N-type heavily doped InSb, GaAs, InAs, InGaAs, GaAsSb or InGaP compound semiconductor film, for example, a n+InSb with a thickness of 0.5 μm; the N-type electrode 13 comprises a metal electrode formed of Au, Ge, Ni, Ti, Cr, Cu or an alloy thereof, preferably a Ti/Au metal electrode. In this example, the protective layer 80 may be a Si ₃ N ₄ passivation layer, SiO ₂ , epoxy resin, silica gel or polyimide.

It should be understood that the materials and thicknesses of the various compound semiconductor films, protective layers, etc. in the aforementioned compound semiconductor stack are merely examples, and those skilled in the art may select any feasible material or suitable thickness as needed, without being limited to the examples shown here.

The compound semiconductor stack is manufactured by the following steps:

A plurality of compound semiconductor films are heteroepitaxially grown in sequence on a semiconductor single crystal substrate to form an N-type electrode ohmic contact and current conducting layer 70 (including a lattice buffer sacrificial layer 71 with poor crystal quality for heteroepitaxial growth, and a P-type electrode ohmic contact and current conducting layer 72 with excellent crystal quality on the lattice buffer sacrificial layer 71), a photon absorption layer 60, a carrier blocking layer 50, a first P-type electrode ohmic contact and current conducting layer 41 and a second P-type electrode ohmic contact and current conducting layer 42; the surface defect density of the PN or PiN type (InSb infrared) photon absorption layer 60 is less than or equal to 10-100/ ^cm2 .

Coating an adhesive layer 30 on at least one of the second P-type electrode ohmic contact and current conducting layer 42 and the substrate 10, and bonding them face to face through the adhesive layer 30;

Selectively remove the semiconductor single crystal substrate, the N-type electrode ohmic contact and a portion of the current conducting layer 70, that is, selectively remove the lattice buffer sacrificial layer 71 with poor crystal quality by etching;

The semiconductor single crystal substrate may be any suitable single crystal substrate such as GaAs, InP, GaN, Si, etc., and the compound semiconductor film includes InSb, GaAs, InAs, InGaAs, InAlSb, GaAsSb or InGaP. The bonding layer 30 includes any one of silicon nitride film, silicon oxide film, aluminum oxide film, silicon oxynitride film, epoxy resin, silica gel, silicon dioxide and polyimide film. In this embodiment, the mobility of the N-type electrode ohmic contact and current conducting layer 72 removed from the semiconductor single crystal substrate is greater than 40000 ^cm2 /Vs, and the thickness of the N-type electrode ohmic contact and current conducting layer 72 is 500nm-10μm, preferably 1μm-3μm. After the semiconductor single crystal substrate and the lattice buffer sacrificial layer 71 of the N-type electrode ohmic contact and current conducting layer are removed at the same time, the mobility of the N-type electrode ohmic contact and current conducting layer 72 is greatly improved, which is greater than 50000 ^cm2 /Vs and less than 78000 ^cm2 /Vs. The thickness of the N-type electrode ohmic contact and current conducting layer 72 is 100nm-9μm, preferably 300nm-2μm.

The substrate 10 containing the IC circuit is rigid or flexible. The rigid substrate 10 can be a silicon-based substrate, a quartz substrate, an aluminum oxide substrate, or an aluminum nitride substrate; the flexible substrate is made of polyimide or polyester film as a base material.

A reflective film 20 may also be provided between the substrate 10 and the bonding layer 30, and the reflective film 20 may reflect at least a portion of the incident light that passes through the compound semiconductor stack from above and enter the compound semiconductor stack again in the form of reflected light, thereby improving the detection efficiency of the infrared sensor. In one example, the reflective film 20 may include a metal reflective film or a multilayer dielectric reflective film. The metal reflective film 20 is located directly below the incident light and may be manufactured separately from the metal electrode by photolithography and coating, and there is no electrical connection between the two. It is understood that if the substrate 10 itself is made of metal and has a better reflective function, it is no longer necessary to provide a reflective film.

Materials that can be used to manufacture compound semiconductor stacks, such as GaAs, InSb and InAs, have different infrared wavelength absorption rates at room temperature. Among them, InSb material can absorb infrared photons with a wavelength greater than or equal to 1 micron at room temperature, and has the highest electron mobility, which can reach 78,000 cm ² /Vs. Therefore, it is one of the most suitable embodiment materials of the present invention.

In one embodiment of the present invention, there are two methods for manufacturing compound semiconductor films such as InSb. One is to obtain a polycrystalline InSb film by evaporating the InSb material onto a mica sheet or a silicon oxide substrate. Although the InSb film manufactured by this method has a relatively low manufacturing cost, the quality is relatively poor. The mobility is generally only 15,000 cm ² /Vs to 30,000 cm ² /Vs, and the photoelectric performance is very poor, which does not meet the expected requirements for infrared photon absorption and detection. Another manufacturing method is to use homoepitaxial growth on a semi-insulating InSb single crystal substrate to obtain a high-quality InSb single crystal film. The InSb single crystal film manufactured in this way has high quality and basically meets the detection requirements of infrared photons. However, since the production process of semi-insulating InSb single crystal substrates is very immature, there is currently no way to use it for large-scale production.

Therefore, in the manufacture of compound semiconductor stacks, other semiconductor single crystal substrates are usually selected, such as GaAs substrates or Si substrates. Although these alternative semiconductor single crystal substrates are relatively cheap, due to the large lattice mismatch with InSb, the quality of the InSb single crystal film grown on such alternative semiconductor single crystal substrates will be reduced, and the mobility will be much lower than that of the InSb single crystal film obtained on the InSb single crystal substrate, generally between ^30000cm2 /Vs and ^50000cm2 /Vs. More fatally, the defect surface density of such InSb single crystal film is very large, generally above 10000/ ^cm2 , resulting in extremely large dark current of infrared photon PN or PiN junction, and it is impossible to achieve the signal-to-noise ratio required for infrared photon detection.

Because there is a large lattice mismatch between the InSb film and the semiconductor single crystal substrate, the quality of the InSb film grown at the beginning is very poor, with a large defect density and very low mobility. As the thickness of the InSb film material increases, the lattice quality will continue to improve, the defect density will gradually decrease, and the mobility will increase.

In order to achieve an electron mobility of less than or equal to 10-100/ ^cm2 and higher than ^50000cm2 /Vs, the InSb film is generally required to be grown with a thickness of more than 1-2μm. However, since the InSb film is very thick, part of the infrared photons will be absorbed by the InSb film with poor crystal quality, significantly reducing the quantum efficiency of the infrared photon detection device finally manufactured.

Usually, the crystal defects of the film caused by the mismatch with the substrate are obvious near the interface of the substrate. Although the density of crystal defects gradually decreases with the growth of the film, the concentration of crystal defects is high and the electron mobility is reduced. If a film of several microns is formed, the impact of defects near the interface becomes very small, but when manufacturing devices, due to the thick InSb film thickness, some infrared photons will be absorbed by the InSb film with poor crystal quality, significantly reducing the quantum efficiency of the infrared photon detection device finally manufactured.

The following embodiments of the present invention provide a top-incident infrared sensor element and a manufacturing method, in which a compound semiconductor stack is integrated with a signal processing circuit board. Compared with the prior art, the compound semiconductor stack has a low crystal defect density, high mobility and simultaneously has a high photon absorption efficiency, and the thickness of the formed device is relatively small.

In FIG1 , only one compound semiconductor stack is shown, and at least one compound semiconductor stack may be arranged in a planar array, a linear array, or a four-quadrant array on the substrate 10, so that the position or two-dimensional image of the object to be detected can be detected. When at least one compound semiconductor stack is arranged, they can be integrated with an IC circuit, so that a single circuit chip controls multiple compound semiconductor stacks.

2A-2G , which show a manufacturing flow chart of a top-incident infrared sensor element according to an embodiment of the present invention.

Specifically, as shown in FIG2A , a compound semiconductor film is grown on a semiconductor single crystal substrate 90 by epitaxy (e.g., metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE)), and the compound semiconductor film 70 includes a first portion (lattice buffer sacrificial layer 71) of poor quality and a second portion (N-type electrode ohmic contact and current conduction layer 72, the boundary line is schematically shown by a dotted line in the figure). In one example, the semiconductor single crystal substrate can be any suitable single crystal substrate such as GaAs, InP, GaN, Si, etc. The compound semiconductor film can include binary, ternary, and quaternary materials composed of In, Sb, As, Ga, and P, such as GaAs, InAs, InSb, InGaAs, InGaP, InGaAsP, etc., preferably InSb film.

InSb is used as an example for illustration. In one example, multiple compound semiconductor films are formed by epitaxial growth to form an N-type electrode ohmic contact and current conducting layer 72, a photon absorption layer 60, a carrier blocking layer 50, a first P-type electrode ohmic contact and current conducting layer 41, and a second P-type electrode ohmic contact and current conducting layer 42.

As shown in FIG. 2B , a reflective film 20 is formed on a substrate 10 including an IC circuit by coating, sputtering or the like.

2C, a layer of adhesive is coated on the second P-type electrode ohmic contact and current conducting layer 42 and/or the reflective film 20 to form an adhesive layer 30. In one example, the adhesive such as polyimide or epoxy resin is coated by coating or scraping.

As shown in FIG2D , the second P-type electrode ohmic contact and current conducting layer 42 are then bonded face-to-face with the reflective film 20 on the substrate 10 through the adhesive layer 30. The substrate 10 includes any integrated circuit suitable for the specific application of the Hall element, for example, a silicon-based wafer including a suitable integrated circuit. Of course, the adhesive may also be applied to the reflective film 20 of the substrate 10 or the adhesive may be applied to both the second P-type electrode ohmic contact and current conducting layer 42 and the reflective film 20. Those skilled in the art may select the material of the substrate 10 as needed, without being limited to the examples described herein.

As shown in FIG2E , the semiconductor single crystal substrate 90 is selectively removed to expose the back side of the N-type electrode ohmic contact and the current conducting layer 70. In one example, mechanical grinding or chemical etching can be used. The mechanical grinding described here can be a conventional semiconductor grinding device, and the chemical etching solution can be a mixed solution of phosphoric acid and hydrogen peroxide, or a hydrochloric acid solution. Those skilled in the art will appreciate that the mechanical grinding or chemical etching here can be performed by other alternative methods known in the art.

The first part of the exposed N-type electrode ohmic contact and current conducting layer 70 that has just grown and has poor quality (i.e., the lattice buffer sacrificial layer 71) is removed to leave the second part (N-type electrode ohmic contact and current conducting layer 72) with high quality. In one example, the first part of the exposed N-type electrode ohmic contact and current conducting layer 70 can be removed by dry or wet etching, that is, the first part previously grown on the semiconductor single crystal substrate 60 is removed. The first part has poor quality due to lattice mismatch, so the second part with high quality (e.g., high mobility) can be retained. The dry etching described here can be ion beam etching, etc., and the wet etching can be etching using any suitable solution.

Those skilled in the art should understand that the method described in the present invention can be used to select the mobility and thickness of the compound semiconductor film according to the design requirements of the device, thereby providing great flexibility in selection of the mobility and thickness of the compound semiconductor film, so that a compound semiconductor film with higher mobility and thinner thickness (higher square resistance) can be obtained at the same time.

The N-type electrode ohmic contact and current conduction layer 72, the photon absorption layer 60, the carrier blocking layer 50, and the right end portion of the first P-type electrode ohmic contact and current conduction layer 41 in the compound semiconductor stack are etched away by graphical etching (for example, etching away by a semiconductor mesa etching process), thereby obtaining a mesa structure as shown in the figure, wherein the size of the second P-type electrode ohmic contact and current conduction layer 42 is larger than that of the first P-type electrode ohmic contact and current conduction layer 41.

As shown in FIG. 2F , an N-type electrode 13 and a P-type electrode 14 are manufactured on the N-type electrode ohmic contact and current conducting layer 70 and the second P-type electrode ohmic contact and current conducting layer 42 respectively or simultaneously by photolithography and metal lift-off processes.

In one example, a metal electrode layer is first formed by a deposition method such as electron beam evaporation or magnetron sputtering, and the material of the metal electrode layer may include Au, Ge, Ni, Ti, Cr, Cu or their alloys; then, electrodes 13 and 14 are formed from the metal electrode layer by stripping or etching; the electrodes 13 and 14 are optionally annealed to form a better ohmic contact between the electrode and the compound semiconductor stack. Of course, those skilled in the art can form electrodes 13 and 14 by any method known in the art, and the present invention will not be repeated here.

As shown in FIG. 2G , the N-type electrode 13 and the negative lead terminal 12 , and the P-type electrode 14 and the positive lead terminal 11 are electrically connected through metal bonding wires 15 and 16 , respectively.

Furthermore, a protective layer 80 is formed on at least a portion of the surface (eg, the entire surface) of the compound semiconductor stack and the electrodes 13 , 14 .

The protective layer 80 can prevent the compound semiconductor stack from being damaged in the subsequent process and prevent water vapor, foreign particles, etc. from entering. The protective layer 80 includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silica gel, a silicon dioxide, and a polyimide film. It can be formed by plasma enhanced chemical vapor deposition (PECVD), sputtering, or other conventional film forming methods, using a photoresist pattern as a mask.

The compound semiconductor stack manufactured by the embodiment of Figures 2A-2G of the present invention, if the compound semiconductor film is made of InSb material, the mobility of the compound semiconductor film can exceed 60,000 ^cm2 /Vs. At the same time, the square resistance of the compound semiconductor film can be designed to a desired value, thereby ultimately obtaining a high-sensitivity, low-power consumption InSb compound semiconductor stack.

Alternatively, after growing a compound semiconductor film on another semiconductor single crystal substrate, the subsequent compound semiconductor film may not be epitaxially grown, but may be bonded to the substrate 10 via a bonding layer (e.g., the bonding layer 30 described below), and the other semiconductor single crystal substrate and the poor quality compound semiconductor film that has just grown may be selectively removed, thereby leaving only a good quality portion on the substrate 10 as a second P-type electrode ohmic contact and current conduction layer 42, the mobility of which is greater than 50,000 ^cm2 /Vs and less than 78,000 ^cm2 /Vs, and the thickness of the P-type electrode ohmic contact and current conduction layer is 100nm-9μm. It can be understood that by continuing to epitaxially grow subsequent multiple layers (such as the second P-type electrode ohmic contact and current conducting layer 41, the carrier blocking layer 50, the photon absorption layer 60, the N-type electrode ohmic contact and current conducting layer 72) on the good quality P-type electrode ohmic contact and current conducting layer, a compound semiconductor film of similar quality to homoepitaxial growth can be obtained, thereby further improving the quality of the obtained compound semiconductor stack. At this time, in order to meet the requirements of the subsequent epitaxial growth of the compound semiconductor film, the bonding layer used needs to be a high temperature resistant material such as silicon dioxide or silicon nitride.

In summary, the inventors of the present invention have found that by reducing the resistance of the compound semiconductor stack, and integrating the compound semiconductor stack and the integrated circuit that processes the electrical signal output from the compound semiconductor stack on the same substrate, and encapsulating them in the same package, detection can be performed at room temperature. In addition, in this way, the infrared sensor element of the present invention can be made less susceptible to dark current, electromagnetic noise and thermal fluctuations. In the present invention, the resistance of the compound semiconductor stack in the infrared sensor circuit can be made small, so that the resistance and capacitance in the signal output circuit can be very small, thereby allowing the infrared sensor element to be miniaturized.

The present invention also provides a plurality of embodiments according to the following aspects, which are specifically as follows:

Aspect 1: A method for manufacturing a top-incident infrared sensor element, the method comprising:

manufacturing at least one compound semiconductor stack capable of detecting infrared light having a wavelength of 1 micrometer or more and outputting an electrical signal indicative of the detection;

Providing a substrate containing an IC circuit, wherein the IC circuit processes the electrical signal output from the at least one compound semiconductor stack and performs calculations to obtain a detection result;

Providing an adhesive layer to bond at least one compound semiconductor stack to a substrate containing an IC circuit;

Wherein, the electrode of the at least one compound semiconductor stack is electrically connected to the lead terminal of the IC circuit.

Aspect 2: The method according to aspect 1, wherein:

One of the at least one compound semiconductor stack comprises, from top to bottom, an N-type electrode, an N-type electrode ohmic contact and current conduction layer, a P-N or P-i-N type photon absorption layer, a carrier blocking layer, a P-type electrode ohmic contact and current conduction layer, and a P-type electrode located on a portion of the P-type electrode ohmic contact and current conduction layer.

Aspect 3: The method according to aspect 2, wherein:

The P-type electrode ohmic contact and current conducting layer comprises a first P-type electrode ohmic contact and current conducting layer and a second P-type electrode ohmic contact and current conducting layer, the first P-type electrode ohmic contact and current conducting layer is located on the second P-type electrode ohmic contact and current conducting layer, the size of the second P-type electrode ohmic contact and current conducting layer is larger than the first P-type electrode ohmic contact and current conducting layer, and a P-type electrode is disposed on a portion of the second P-type electrode ohmic contact and current conducting layer not covered by the first P-type electrode ohmic contact and current conducting layer;

The electrical connection between the N-type electrode and the negative lead terminal of the IC circuit and the electrical connection between the P-type electrode and the positive lead terminal of the IC circuit are connected by metal wire bonding or multi-layer metal interconnection lines formed by photolithography.

Aspect 4: The method according to aspect 2, wherein:

The P-type electrode comprises a metal electrode formed of Au, Ge, Ni, Ti, Cr, Cu or an alloy thereof, preferably a Ti/Au metal electrode;

The first P-type electrode ohmic contact and current conducting layer and the second P-type electrode ohmic contact and current conducting layer are p-type heavily doped compound semiconductor films;

The carrier blocking layer comprises a p-type heavily doped compound semiconductor film containing Ga, Al, In, Sb, and As, preferably an InAlSb compound semiconductor film;

The photon absorption layer comprises a P-N or P-i-N lightly doped InSb, GaAs, InAs, InGaAs, GaAsSb or InGaP compound semiconductor film, preferably an InSb compound semiconductor film;

The N-type electrode ohmic contact and current conducting layer include an n-type heavily doped InSb, GaAs, InAs, InGaAs, GaAsSb or InGaP compound semiconductor film, preferably an InSb compound semiconductor film;

The N-type electrode includes a metal electrode formed of Au, Ge, Ni, Ti, Cr, Cu or an alloy thereof, preferably a Ti/Au metal electrode.

Aspect 5: The method according to aspect 4, wherein:

The compound semiconductor stack is manufactured by the following steps:

Hetero-epitaxially growing a plurality of compound semiconductor films on a semiconductor single crystal substrate in sequence, respectively forming an N-type electrode ohmic contact and current conducting layer containing a lattice buffer sacrificial layer, a P-i-N type photon absorption layer, a carrier blocking layer, a first P-type electrode ohmic contact and current conducting layer, and a second P-type electrode ohmic contact and current conducting layer;

Coating an adhesive layer on at least one of the second P-type electrode ohmic contact, the current conducting layer and the substrate, and bonding them face to face through the adhesive layer;

Selectively remove the lattice buffer sacrificial layer in the semiconductor single crystal substrate, N-type electrode ohmic contact and current conduction layer,

in,

The semiconductor single crystal substrate adopts any suitable single crystal substrate such as GaAs, InP, GaN, Si, etc., the compound semiconductor film includes InSb, GaAs, InAs, InGaAs or InGaP, InAlSb, GaAsSb or InGaP, the bonding layer includes any one of silicon nitride film, silicon oxide film, aluminum oxide film, silicon oxynitride film, epoxy resin, silica gel, silicon dioxide and polyimide film, and the substrate includes any one of Si-based wafer containing IC circuit, quartz substrate, aluminum oxide substrate, aluminum nitride substrate, polyimide flexible substrate.

Aspect 6: The method according to aspect 5, wherein:

After only the semiconductor single crystal substrate is removed, the mobility of the N-type electrode ohmic contact and the current conducting layer is greater than 40000 cm ² /Vs, and the thickness of the N-type electrode ohmic contact and the current conducting layer is 500nm-10μm, preferably 1μm-3μm;

At the same time, the lattice buffer sacrificial layer with poor crystal quality in the semiconductor single crystal substrate, the N-type electrode ohmic contact and the current conducting layer is removed, and the mobility of the N-type electrode ohmic contact and the current conducting layer is greatly improved, the mobility is greater than ^50000cm2 /Vs and less than ^78000cm2 /Vs, the thickness of the N-type electrode ohmic contact and the current conducting layer is 100nm-9μm, preferably 300nm-2μm; the surface defect density of the PN or PiN type (InSb infrared) photon absorption layer is less than or equal to 10-100/ ^cm2 .

Aspect 7: The method according to any one of aspects 1-6, wherein:

The top-incident infrared sensor element further includes a protective layer for covering the compound semiconductor stack, but at least a portion of the N-type electrode and the P-type electrode is exposed;

The protective layer includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silica gel, silicon dioxide, and a polyimide film.

Aspect 8: The method according to any one of aspects 1-7, wherein:

The substrate containing the IC circuit is rigid or flexible;

A reflective film is also arranged between the substrate and the bonding layer.

Aspect 9: The method according to any one of aspects 1-8, wherein:

The at least one compound semiconductor stack is arranged on the substrate in the form of a planar array, a linear array or four quadrants.

Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims (13)

1. An upper incident light type infrared sensor element, the upper incident light type infrared sensor element comprising:

at least one compound semiconductor stack capable of detecting infrared rays having a wavelength of 1 μm or more and outputting an electrical signal representing the detection;

a substrate including an IC circuit that processes and computes an electric signal output from the at least one compound semiconductor stack to obtain a detection result;

An adhesive layer bonding at least one compound semiconductor stack to a substrate containing an IC circuit;

wherein the electrode of the at least one compound semiconductor stack is electrically connected to a lead terminal of the IC circuit,

one of the at least one compound semiconductor stacks comprises, in order from top to bottom: the semiconductor device comprises an N-type electrode, an N-type electrode ohmic contact and current conducting layer, a P-N or P-i-N type photon absorption layer, a carrier blocking layer, a P-type electrode ohmic contact and current conducting layer and a P-type electrode positioned on a part of the P-type electrode ohmic contact and current conducting layer;

removing only the N-type electrode ohmic contact of the semiconductor single crystal substrate and the mobility of the current conducting layer is greater than 40000 cm ² The thickness of the N-type electrode ohmic contact and current conducting layer is 500nm-10 mu m;

the P-N or P-i-N photon absorption layer has an area defect density of 10-100/cm or less ² 。

2. The upper incident light type infrared sensor element as set forth in claim 1, wherein,

the P-type electrode comprises a metal electrode formed by Au, ge, ni, ti, cr, cu or an alloy thereof;

the carrier blocking layer includes a p-type doped compound semiconductor film containing Ga, al, in, sb or As or a compound semiconductor film containing Sb;

The P-N or P-i-N photon absorption layer comprises a P-N or P-i-N type lightly doped InSb, gaAs, inAs, inGaAs, gaAsSb or InGaP compound semiconductor film,

the N-type electrode comprises a metal electrode formed of Au, ge, ni, ti, cr, cu or an alloy thereof,

the N-type electrode ohmic contact and current conduction layer comprises an N-type heavily doped InSb, gaAs, inAs, inGaAs, gaAsSb or InGaP compound semiconductor film.

3. The upper incident light type infrared sensor element as set forth in claim 1, wherein,

the P-type electrode ohmic contact and current conduction layer comprises a first P-type electrode ohmic contact and current conduction layer and a second P-type electrode ohmic contact and current conduction layer, the first P-type electrode ohmic contact and current conduction layer is positioned on the second P-type electrode ohmic contact and current conduction layer, and the second P-type electrode ohmic contact and current conduction layer is larger than the first P-type electrode ohmic contact and current conduction layer in size.

4. The upper light-entering type infrared sensor element as set forth in claim 3, wherein,

the first P-type electrode ohmic contact and the current conducting layer and the second P-type electrode ohmic contact and the current conducting layer are P-type heavily doped compound semiconductor films.

5. The upper light-entering type infrared sensor element as set forth in claim 3, wherein,

and the part of the second P-type electrode ohmic contact and the current conducting layer which is not contacted by the first P-type electrode ohmic contact and the current conducting layer is provided with a P-type electrode.

6. The upper incident light type infrared sensor element as set forth in claim 5, wherein,

the N-type electrode is electrically connected with the negative electrode lead end of the IC circuit and the P-type electrode is electrically connected with the positive electrode lead end of the IC circuit through metal wire bonding or multi-layer metal interconnection wires formed through photoetching.

7. The upper incident light type infrared sensor element as set forth in claim 6, wherein,

the compound semiconductor laminate is manufactured by the following steps:

a plurality of compound semiconductor films are epitaxially grown on a semiconductor single crystal substrate in a heterogeneous sequence, and an N-type electrode ohmic contact and a current conducting layer, a P-N or P-i-N type photon absorption layer, a carrier blocking layer, a first P-type electrode ohmic contact and current conducting layer, a second P-type electrode ohmic contact and current conducting layer which contain lattice buffer sacrificial layers are respectively formed;

coating an adhesive layer on at least one of the ohmic contact and the current conducting layer of the second P-type electrode and the substrate, and bonding them together face to face through the adhesive layer;

Selectively removing the lattice buffer sacrificial layer in the semiconductor single crystal substrate, the ohmic contact of the N-type electrode and the current conducting layer,

wherein the semiconductor single crystal substrate adopts GaAs, inP, gaN or Si single crystal substrate, and the compound semiconductor film comprises InSb, gaAs, inAs, inGaAs, inAlSb, gaAsSb or InGaP.

8. The upper incident light type infrared sensor element as set forth in claim 7, wherein,

the bonding layer comprises any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, silica gel, silicon dioxide and a polyimide film, and the substrate comprises any one of a Si-based wafer containing an IC circuit, a quartz substrate, an aluminum oxide substrate, an aluminum nitride substrate and a polyimide flexible substrate.

9. The upper incident light type infrared sensor element as set forth in claim 1, wherein,

simultaneously removing the lattice buffer sacrificial layer with poor lattice quality in the semiconductor single crystal substrate, the N-type electrode ohmic contact and the current conducting layer, wherein the mobility of the N-type electrode ohmic contact and the current conducting layer is more than 50000 cm ² Vs less than 78000cm ² and/Vs, wherein the thicknesses of the ohmic contact and the current conducting layer of the N-type electrode are 100nm-9 mu m.

10. The upper incident light type infrared sensor element according to any one of claims 1 to 9, wherein,

The upper incident light type infrared sensor element further includes a protective layer for covering the compound semiconductor stack, but exposing at least a portion of the N-type electrode and the P-type electrode;

the protective layer includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silicon gel, silicon dioxide, and a polyimide film.

11. The upper incident light type infrared sensor element according to any one of claims 1 to 9, wherein,

the substrate containing the IC circuit is rigid or flexible;

and a reflecting film is arranged between the substrate and the bonding layer.

12. The upper incident light type infrared sensor element according to any one of claims 1 to 9, wherein,

the at least one compound semiconductor stack is arranged on the substrate in a planar array, a linear array, or a four-quadrant.

13. A method of manufacturing the upper incident light type infrared sensor element according to any one of claims 1 to 12, the method comprising:

manufacturing at least one compound semiconductor stack capable of detecting infrared rays having a wavelength of 1 μm or more and outputting an electrical signal representing the detection;

providing a substrate including an IC circuit that processes and computes an electrical signal output from the at least one compound semiconductor stack to obtain a detection result;

Providing an adhesive layer to bond at least one compound semiconductor stack to a substrate containing an IC circuit;

wherein the electrode of the at least one compound semiconductor stack is electrically connected to the lead terminal of the IC circuit.