CN113643997A - Groove shape monitoring method and structural device - Google Patents
Groove shape monitoring method and structural device Download PDFInfo
- Publication number
- CN113643997A CN113643997A CN202110873012.5A CN202110873012A CN113643997A CN 113643997 A CN113643997 A CN 113643997A CN 202110873012 A CN202110873012 A CN 202110873012A CN 113643997 A CN113643997 A CN 113643997A
- Authority
- CN
- China
- Prior art keywords
- trench
- layer
- oxide layer
- electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 67
- 238000012544 monitoring process Methods 0.000 title claims abstract description 49
- 238000012360 testing method Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 230000015556 catabolic process Effects 0.000 claims abstract description 45
- 238000012876 topography Methods 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 196
- 239000012790 adhesive layer Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 31
- 238000000206 photolithography Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000011161 development Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000001459 lithography Methods 0.000 claims 2
- 239000010409 thin film Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000001514 detection method Methods 0.000 abstract description 4
- 239000003292 glue Substances 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 238000001259 photo etching Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
一种沟槽形貌监控方法，步骤包括：在衬底硅片上制作沟槽并在沟槽表面氧化生长一层氧化层；再在氧化层表面制作第一测试电极；在第一测试电极与预制在衬底远离沟槽一侧表面的第二测试电极之间进行电压测试，以测得氧化层的击穿电压值；将测得的氧化层的击穿电压值与氧化层的本征击穿电压值进行比对，以判断氧化层的厚度是否均匀，进而可判定与氧化层紧贴设置的沟槽的形貌是否符合标准。还提出一种采用该沟槽形貌监控方法获得的易于沟槽形貌监控的结构器件。本发明仅通过测试沟槽内氧化层的击穿电压即可间接判断沟槽形貌情况，不仅测试结果准确且可监测效率高，且再现检测率高。同时根据这一监控方法获得的沟槽形貌结构稳定，并与实际产线工艺兼容。
A trench topography monitoring method, comprising the steps of: forming a trench on a substrate silicon wafer and oxidizing and growing an oxide layer on the surface of the trench; then making a first test electrode on the surface of the oxide layer; A voltage test is prefabricated between the second test electrodes on the surface of the substrate away from the trench to measure the breakdown voltage value of the oxide layer; the measured breakdown voltage value of the oxide layer is compared with the intrinsic breakdown voltage of the oxide layer. The breakdown voltage values are compared to judge whether the thickness of the oxide layer is uniform, and then it can be judged whether the morphology of the trench arranged in close contact with the oxide layer meets the standard. A structure device which is easy to monitor the trench topography obtained by using the trench topography monitoring method is also proposed. The invention can indirectly judge the trench topography only by testing the breakdown voltage of the oxide layer in the trench, not only the test result is accurate, but also the monitoring efficiency is high, and the reproducing detection rate is high. At the same time, the trench morphology and structure obtained according to this monitoring method are stable and compatible with the actual production line process.
Description
Technical Field
The invention belongs to the technical field of device groove etching processes, and particularly relates to a monitoring method for monitoring the shapes of a side wall and a corner of a groove and a structural device easy for monitoring the shapes of the groove.
Background
The development direction of many devices such as MOS, SGT, IGBT, Trench SBD, etc. is also becoming mainstream, and Trench etching is a key process for device processing. The existing trench etching process usually adopts an optical or step profiler mode to monitor the width and depth of a trench, regularly splits an etched wafer, and measures the profile of the trench through a scanning electron microscope and the like; the process can only confirm whether the side wall and corner appearance of the groove has problems when the electrical performance test is carried out after the product is processed; moreover, the appearance of the SEM monitoring groove after splitting is only confirmed by the appearance of one local point, and large-area chip monitoring cannot be carried out; meanwhile, as special equipment is needed for sample preparation and SEM monitoring, the testing time is relatively long, so that a complex groove structure sample cannot be monitored, all key points of groove etching cannot be completely monitored, the width and the depth of the groove etching are monitored, and the appearance of the side wall and the corner is not effectively monitored. The shapes of the side wall and the corner of the groove seriously affect the product quality, and the delayed discovery of the quality problem caused by the monitoring delay of the side wall and the corner directly results in the rejection of the product, so that the production efficiency is low, and the product quality is unstable.
Disclosure of Invention
The invention provides a groove shape monitoring method and a structural device easy for groove shape monitoring, and solves the technical problem that the shapes of the side wall and the corner of a groove cannot be monitored in the prior art.
In order to solve the technical problems, the invention adopts the technical scheme that:
a method for monitoring a trench profile comprises the following steps:
manufacturing a groove on a substrate silicon chip and oxidizing and growing an oxide layer on the surface of the groove;
manufacturing a first test electrode on the surface of the oxidation layer;
performing voltage test between the first test electrode and a second test electrode prefabricated on the surface of one side, far away from the groove, of the substrate to obtain a breakdown voltage value of the oxide layer;
and comparing the measured breakdown voltage value of the oxide layer with the intrinsic breakdown voltage value of the oxide layer to judge whether the thickness of the oxide layer is uniform or not, and further judging whether the appearance of the groove tightly attached to the oxide layer meets the standard or not.
Further, the thickness of the oxide layer is 50-5000A; and when the measured breakdown voltage value of the oxide layer is not less than 80-90% of the intrinsic breakdown voltage value, the oxide layer is represented to be uniform in thickness.
Furthermore, the method for manufacturing the trench on the substrate silicon wafer and growing the oxide layer on the surface of the trench through oxidation comprises the following steps:
depositing a single-layer or multi-layer mask layer on the front surface of the substrate, and enabling the mask layer to cover the whole surface of the substrate, wherein the thickness of the mask layer is 1000-10000A;
coating a first adhesive layer with the same area as the mask layer on one side of the mask layer away from the substrate;
sequentially carrying out exposure and development in the first adhesive layer to obtain a photoetching pattern;
etching on the substrate based on the photoetching pattern to obtain a plurality of grooves;
growing a layer of the oxide layer on the inner surface of the groove in an oxidation mode;
wherein, the width of the groove is 0.2-10um, and the depth thereof is 0.2-400 um.
Further, before etching the trench, the method further includes:
etching the first adhesive layer along the thickness direction of the first adhesive layer to etch away a position region corresponding to the groove in the first adhesive layer so as to obtain the photoetching pattern;
etching the position area of the groove on the mask layer and the upper surface of the substrate along the thickness of the mask layer based on the photoetching position in the first adhesive layer;
and removing all the first adhesive layers on the mask layer.
Further, the etching of the position area of the groove in the mask layer is realized by adopting a dry etching process; and removing all the residual glue layers by adopting a dry removing process or a wet removing process.
Further, the step of manufacturing a first test electrode on the surface of the oxide layer includes:
depositing an electrode layer which is 500-60000A thick and is formed by a polycrystalline silicon or metal film on the mask layer, and filling the electrode layer into the groove with the oxide layer;
coating a second adhesive layer with the same area as the electrode layer on the electrode layer, and exposing and developing the second adhesive layer in sequence to define an electrode pattern;
and etching the electrode layer based on the electrode pattern to obtain the first test electrode covering the position of the groove with the oxide layer.
Further, before the etching of the electrode layer based on the electrode pattern, the method further includes:
photoetching the second adhesive layer to remove other areas except the position of the groove with the oxide layer;
etching the electrode layer along the photoetching position of the second adhesive layer to reserve a to-be-tested area of the first testing electrode corresponding to the position of the oxide layer;
and removing all the residual second glue layers.
Further, the etching of the region of the electrode layer, where the groove is not located, is performed by a dry etching process or a wet etching process; and removing all the residual glue layers by adopting a dry removing process or a wet removing process.
A structural device obtained with a trench monitoring method as described in any one of the preceding claims, comprising at least:
the substrate; and
the trench defined within the substrate;
the oxide layer is arranged in the groove and clings to the inner wall of the groove;
and arranging the first test electrode on one side of the substrate, which is far away from the groove, wherein the first test electrode is filled in the groove with the oxide layer and covers the substrate.
Further, the method also comprises the following steps: a dielectric mask layer is arranged between the substrate and the first test electrode;
the mask layer is arranged by penetrating through the groove, and the upper end face of the oxide layer is flush with the mask layer;
wherein the thickness of the mask layer is 1000A-10000A;
the width of the groove is 0.2-10um, and the depth of the groove is 0.2-400 um;
the thickness of the oxide layer is 50-5000A;
the thickness of the first test electrode is 500-60000A.
Compared with the point monitoring of the conventional SEM monitoring mode of the groove profile morphology, the groove morphology monitoring method provided by the invention can monitor the groove in a certain area, and can indirectly judge the groove morphology condition only by testing the breakdown voltage value of the oxide layer in the groove to judge the thickness quality condition of the oxide layer, so that the testing result is accurate, the monitoring efficiency is high, and the reappearance detection rate is high.
According to the invention, the measured breakdown voltage value of the oxide layer is compared with the intrinsic breakdown voltage value of the oxide layer, so that the side wall and corner appearance of the trench can be accurately monitored, the quality of the trench structure can be timely judged, and the production process can be adjusted in advance. Particularly, when the measured breakdown voltage value of the oxide layer is not less than 80-90% of the intrinsic breakdown voltage value, the thickness of the oxide layer is uniform, and thus the appearance of the whole trench close to the oxide layer is uniform and stable.
Meanwhile, the device which is obtained by the monitoring method and is easy to monitor the groove morphology has strong structural universality and stable structure, can be generally used for the production of groove structural devices with complex structures such as strip-shaped grooves, crossed grooves and the like and the monitoring of the groove morphology, is compatible with the actual production line process, and does not need additional equipment.
Drawings
Fig. 1 is a schematic flow chart of a method for monitoring a trench profile according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the device structure at each step in the testing process according to an embodiment of the present invention.
In the figure:
10. substrate 20, mask layer 30, glue layer one
40. Trench 50, oxide layer 60, electrode layer
70. Adhesive layer two 80 and first test electrode
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
The embodiment provides a method for monitoring a trench profile, the flow of which is shown in fig. 1, and the device structure of each step is shown in fig. 2, specifically, the steps include:
s1, forming a groove 40 on the front side of the substrate 10 and growing an oxide layer 50 on the inner surface of the groove 40 by oxidation.
And S11, oxidizing and growing the mask layer 20 on the front surface of the silicon wafer substrate 10.
As shown in fig. 2a, a single-layer or multi-layer mask layer 20 is grown on the front surface of the silicon wafer substrate 10 by oxidation, the mask layer 20 is generally formed by silicon oxide, silicon nitride or other dielectric films, and the mask layer 50 is disposed to cover the entire surface of the substrate 10, and the thickness of the mask layer 20 is 1000-; masking layer 20 may be provided to facilitate etching of trench 40.
S12, coating a first glue layer 30 on the mask layer 20, and obtaining the pattern after photolithography.
As shown in fig. 2b, a first glue layer 30 having the same area as mask layer 20 is coated on the side of mask layer 20 away from substrate 10.
As shown in fig. 2c, the first glue layer 30 is sequentially exposed and developed, so as to etch the first glue layer 30 along the thickness direction thereof, so that the region corresponding to the trench 40 in the first glue layer 30 is etched away, so as to obtain a desired photoresist pattern, wherein the photoresist pattern is a region where the trench 40 is not reserved, and the defined region of the trench 40 is removed by photolithography.
And S13, etching the mask layer 20.
As shown in fig. 2d, based on the photoetching position in the first adhesive layer 30, a dry etching process is adopted to etch the position region of the trench 40 on the mask layer 20 and along the thickness of the mask layer 20, the etching depth penetrates through the thickness of the mask layer 20 to the upper surface of the substrate 10, namely, the region where the trench 40 is not located is reserved, the region where the trench 40 needs to be etched is exposed, the region of the mask layer 20 corresponding to the position of the trench 40 is completely etched away, and the region is etched to the upper surface of the silicon wafer substrate 10, so that the trench 40 on the substrate 10 can be manufactured in the next step.
And S14, removing the first glue layer 30.
As shown in fig. 2e, all the glue layers one 30 on the mask layer 20 are removed by using a dry removal process or a wet removal process, and only the substrate 10 with the etched mask layer 20 remains.
And S15, etching the groove 40.
As shown in fig. 2f, the areas not to be etched are protected based on the blocking of the photolithography pattern in the mask layer 20, and the areas to be etched are etched on the substrate 10 by dry etching, so as to obtain a plurality of trenches 40 having a depth perpendicular to the thickness direction of the substrate 10 and arranged side by side. Wherein, the width of the groove 40 is 0.2-10um, and the depth thereof is 0.2-400 um. The depth and width of the trench 40 depend on the structural design of the device and are not particularly limited herein.
S16, trench 40 oxidation.
As shown in fig. 2g, oxidation is performed on the silicon surface in the trench 40 to grow an oxide layer 50, that is, to form an oxide layer 50 closely attached to the inner wall of the trench 40, wherein the oxidation process is a conventional oxidation process, and the thickness of the oxide layer 50 is 50-5000A, preferably, when the thickness of the oxide layer 50 is 50A, 100A, 350A, 500A, 850A, 1000A and 5000A. The thickness uniformity of the oxide layer 50 can completely reflect the overall appearance of the trench 40, not only the width and depth of the trench 40, but also the profile of the sidewall and corner, and the upper end surface of the oxide layer 50 is completely flush with the upper end surface of the mask layer 20, that is, the depth of the oxide layer 50 is the sum of the depth of the trench 40 and the thickness of the mask layer 20.
S2, and then forming a first test electrode 80 on the surface of the oxide layer 50.
S21, depositing the electrode layer 60.
As shown in fig. 2h, an electrode layer 60 formed of polysilicon or a metal film with a thickness of 500-.
And S22, coating and forming a second photoresist layer 70.
As shown in fig. 2i, a second adhesive layer 70 having the same area as the electrode layer 60 is coated on the upper end surface of the electrode layer 60.
As shown in fig. 2j, the second adhesive layer 70 is subjected to photolithography to remove the areas other than the location where the oxide layer 50 is located, that is, the second adhesive layer 70 is sequentially subjected to exposure and development to define the electrode pattern, that is, to leave the area to be tested, where the shape of the area to be tested depends on the location area where the trench 40 is located. That is, the first adhesive layer 30 is subjected to photolithography along the thickness direction thereof, so that the non-test region, i.e., the region corresponding to the non-oxide layer 50, is etched away in the second adhesive layer 70, so as to obtain the remaining desired photolithography electrode pattern, wherein the electrode pattern is the test region having the oxide layer 50, and the other non-test regions except the position of the oxide layer 50 are all etched away.
And S23, etching the electrode layer 60.
Etching the electrode layer 60 along the position of the second photoresist layer 70 by photolithography to etch away the unnecessary electrode portion, so as to leave the test region of the first test electrode 80 corresponding to the position of the trench 40 having the oxide layer 50, as shown in fig. 2 k; the etching of the region other than the position of the trench 40 in the electrode layer 60, that is, the non-test region, is performed by using a dry etching process or a wet etching process.
Based on the electrode pattern, etching is performed on the electrode layer 60 to obtain a first test electrode 80 covering the trench 40 having the oxide layer 50.
And S24, removing the second glue layer 70.
And as shown in fig. 2l, removing all the remaining second glue layers 70 by using a dry removal process or a wet removal process, and finally obtaining the device with the trench structure during testing.
S3, performing a voltage test between the first test electrode 80 and a second test electrode prepared on a surface of the substrate 10 away from the trench 40 to measure a breakdown voltage value of the oxide layer 50.
After the first test electrode 80 is manufactured, a back electrode, namely a back second test electrode (not shown) is manufactured on the back of the substrate 10, and a voltage test is performed between the first test electrode 80 and the second test electrode by adopting a common voltage monitoring method, namely the voltage endurance between the substrate 10 and the polycrystalline oxide layer 50 is tested, so that the breakdown voltage value of the oxide layer 50 is obtained; the measured breakdown voltage value of the oxide layer 50 is compared with the intrinsic breakdown voltage value of the oxide layer 50 to determine whether the thickness of the oxide layer 50 is uniform, and further, whether the etched feature of the trench 40 tightly attached to the oxide layer 50 is damaged or abnormal can be determined, and whether the feature meets the standard.
The quality of the oxide layer 50 is mainly related to the topography of the trench 40, since the oxidation covers the inner wall of the entire trench 40, including the sidewall, the bottom and the corners of the sidewall and the bottom thereof, if there are spikes or pits on the sidewall and the corners of the trench 40, the thickness of the oxide layer 50 is not uniform, which affects the thickness of the oxide layer 50, and at this time, the breakdown voltage of the oxide layer 50 is reduced, so that the ratio of the breakdown voltage to the intrinsic breakdown voltage is reduced, when the ratio is lower than 80%, the topography of the trench 40 can be indirectly determined to be problematic, that is, the sidewall and the corners thereof are abnormal, and it can be determined that the overall topography of the trench 40 is problematic.
The voltage value is determined according to the thickness of the oxide layer 50, in this embodiment, the test voltage is 5-500V, and the thickness of the oxide layer 50 is 50-5000A. When the measured breakdown voltage value of the oxide layer 50 is not less than 80-90% of the intrinsic breakdown voltage value, it indicates that the thickness of the oxide layer 50 is uniform, the whole etching process is stable, and the features at the corner positions of the sidewall and the bottom of the etched trench 40 are normal.
The tested breakdown voltage values are obtained by taking the oxide layers 50 with different thicknesses and the corresponding voltage values thereof, and the obtained ratio values are shown in the following table 1 by comparing the tested breakdown voltage values with the intrinsic voltage values, and it can be seen from the table that under the same process conditions, when the thicknesses of the oxide layers 50 are 50A, 100A, 350A, 500A, 850A, 1000A and 5000A, the obtained breakdown voltage values are all greater than 80% of the intrinsic breakdown voltage values. The result is completely consistent with the result obtained by monitoring the groove profile by adopting the SEM in the prior art, and shows that the groove profile obtained by adopting the monitoring method has good reproducibility and strong stability.
TABLE 1 ratio of breakdown voltage values to intrinsic breakdown voltage values obtained for different oxide layer thicknesses
By adopting the monitoring method provided by the embodiment, the measured breakdown voltage value of the oxide layer 50 is compared with the intrinsic breakdown voltage value thereof, so that the side wall and corner appearance of the trench 40 can be accurately monitored, the quality of the structure of the trench 40 can be timely judged, and the production process can be adjusted in advance. In particular, when the measured breakdown voltage value of the oxide layer 50 is not less than 80-90% of the intrinsic breakdown voltage value thereof, it means that the thickness of the oxide layer 50 is uniform, and thus it can be known that the profile of the entire trench 40 close to the oxide layer 50 is uniform and stable, thereby monitoring the profile of the sidewalls and corners of the trench 40. In addition, the trench 40 in a certain area can be monitored, the thickness quality condition of the trench 40 can be judged only by testing the breakdown voltage value of the oxide layer 50 in the trench 40, the topography condition of the trench 40 can be indirectly judged, the test result is accurate, the monitoring efficiency is high, and the reproduction detection rate is high.
A structural device susceptible to trench profile monitoring, as shown in fig. 2l, obtained by the monitoring method as described above, at least comprising:
a silicon wafer substrate 10 and a trench 40 defined within the substrate 10; wherein an oxide layer 50 is disposed in the trench 40 and adjacent to the inner wall of the trench 40.
A first test electrode 80 is arranged on the side of the substrate 10 remote from the trench 40, the first test electrode 80 filling the trench 40 with the oxide layer 50 and being arranged to cover the substrate 10.
Further, a dielectric mask layer 20 is arranged between the substrate 10 and the first test electrode 80; masking layer 20 is disposed to be penetrated by trench 40 and the top surface of oxide layer 50 is disposed flush with masking layer 20.
Wherein, the thickness of the mask layer 20 is 1000A-10000A;
the width of the groove 40 is 0.2-10um, and the depth thereof is 0.2-400 um;
the thickness of the oxide layer 50 is 50-5000A;
the thickness of the first test electrode 80 is 500A 60000A.
Compared with the point monitoring of the conventional SEM monitoring mode of the groove profile morphology, the groove morphology monitoring method provided by the invention can be used for monitoring the groove in a certain area, and the groove morphology can be indirectly judged only by testing the breakdown voltage value of the oxide layer in the groove to judge the thickness quality condition, so that the test result is accurate, the monitoring efficiency is high, and the reappearance and detection rate is high.
According to the invention, the measured breakdown voltage value of the oxide layer is compared with the intrinsic breakdown voltage value of the oxide layer, so that the side wall and corner appearance of the trench can be accurately monitored, the quality of the trench structure can be timely judged, and the production process can be adjusted in advance. Particularly, when the measured breakdown voltage value of the oxide layer is not less than 80-90% of the intrinsic breakdown voltage value, the thickness of the oxide layer is uniform, and thus the appearance of the whole trench close to the oxide layer is uniform and stable.
Meanwhile, the device structure which is obtained by the method and is easy to monitor the groove morphology has strong universality and stable structure, can be universally used for monitoring the groove morphology of groove structure devices with complicated structures such as strip-shaped grooves, crossed grooves and the like, is compatible with an actual production line process, and does not need additional equipment.
The embodiments of the present invention have been described in detail, and the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention shall fall within the scope of the present invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110873012.5A CN113643997A (en) | 2021-07-30 | 2021-07-30 | Groove shape monitoring method and structural device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110873012.5A CN113643997A (en) | 2021-07-30 | 2021-07-30 | Groove shape monitoring method and structural device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113643997A true CN113643997A (en) | 2021-11-12 |
Family
ID=78419115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110873012.5A Pending CN113643997A (en) | 2021-07-30 | 2021-07-30 | Groove shape monitoring method and structural device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113643997A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115101412A (en) * | 2022-07-25 | 2022-09-23 | 山东科芯电子有限公司 | A kind of preparation method of TVS chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040071344A (en) * | 2003-02-05 | 2004-08-12 | 주식회사 하이닉스반도체 | Trench DMOS Transistor and Method for the Same |
| US20060160306A1 (en) * | 2005-01-17 | 2006-07-20 | Min-San Huang | Method for forming trench gate dielectric layer |
| CN104658937A (en) * | 2013-11-20 | 2015-05-27 | 北大方正集团有限公司 | Method for measuring breakdown voltage of gate oxide layer of groove type VDMOS device |
| CN109065637A (en) * | 2018-07-13 | 2018-12-21 | 张家港意发功率半导体有限公司 | A kind of trench schottky barrier diode and its manufacturing method |
| CN112802742A (en) * | 2021-03-24 | 2021-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
-
2021
- 2021-07-30 CN CN202110873012.5A patent/CN113643997A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040071344A (en) * | 2003-02-05 | 2004-08-12 | 주식회사 하이닉스반도체 | Trench DMOS Transistor and Method for the Same |
| US20060160306A1 (en) * | 2005-01-17 | 2006-07-20 | Min-San Huang | Method for forming trench gate dielectric layer |
| CN104658937A (en) * | 2013-11-20 | 2015-05-27 | 北大方正集团有限公司 | Method for measuring breakdown voltage of gate oxide layer of groove type VDMOS device |
| CN109065637A (en) * | 2018-07-13 | 2018-12-21 | 张家港意发功率半导体有限公司 | A kind of trench schottky barrier diode and its manufacturing method |
| CN112802742A (en) * | 2021-03-24 | 2021-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
Non-Patent Citations (2)
| Title |
|---|
| 张威 主编: "《微电子制造原理与工艺》", 30 November 2020, 哈尔滨工业大学出版社, pages: 292 - 293 * |
| 范让萱: ""沟槽MOSFET栅极工艺的应用和优化"", 中国优秀硕士学位论文全文数据库（电子期刊） 信息科技辑》, 15 March 2013 (2013-03-15), pages 135 - 196 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115101412A (en) * | 2022-07-25 | 2022-09-23 | 山东科芯电子有限公司 | A kind of preparation method of TVS chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20130302912A1 (en) | Method to Reduce Magnetic Film Stress for Better Yield | |
| JPS61119058A (en) | Manufacture of semiconductor device | |
| JP2010087300A (en) | Method of manufacturing semiconductor device | |
| KR100216674B1 (en) | Deprocessing method of defect analysis of polysilicon contact | |
| CN113643997A (en) | Groove shape monitoring method and structural device | |
| US20010008795A1 (en) | Semiconductor device and method for manufacturing the same | |
| US6859023B2 (en) | Evaluation method for evaluating insulating film, evaluation device therefor and method for manufacturing evaluation device | |
| JPH11145281A (en) | Method for manufacturing semiconductor device | |
| US8034721B2 (en) | Manufacturing method of semiconductor device | |
| US6858452B2 (en) | Method for isolating self-aligned contact pads | |
| CN119560418B (en) | Semiconductor structure and manufacturing method thereof | |
| CN119361426B (en) | A method for determining AlGaN etching rate | |
| CN108807399B (en) | Preparation method of flash memory | |
| US7498226B2 (en) | Method for fabricating semiconductor device with step gated asymmetric recess | |
| US7189622B2 (en) | Method for fabricating semiconductor device | |
| KR100558038B1 (en) | Manufacturing method of semiconductor device | |
| JP2000173996A (en) | Semiconductor device and manufacture thereof | |
| US20050056883A1 (en) | Method to improve flash forward tunneling voltage (FTV) performance | |
| CN101510497B (en) | Laminated mark and its making method | |
| CN113394127B (en) | Method for monitoring critical dimension of 3D memory bridging structure | |
| KR100807596B1 (en) | Semiconductor device manufacturing method | |
| US5858874A (en) | Method of fabricating semiconductor device having step of forming plug in contact hole | |
| KR20030002114A (en) | Method of forming bit line contact of DRAM | |
| TW202407831A (en) | Critical dimension inspection method and semiconductor device manufacturing method using the same | |
| JPH01117342A (en) | Formation of contact hole |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: 300384 2nd floor, block a, 12 Haitai East Road, Huayuan Industrial Zone, Binhai New Area, Tianjin Applicant after: TCL Huanxin Semiconductor (Tianjin) Co.,Ltd. Address before: 300384 2nd floor, block a, 12 Haitai East Road, Huayuan Industrial Zone, Binhai New Area, Tianjin Applicant before: TIANJIN HUANXIN TECHNOLOGY & DEVELOPMENT Co.,Ltd. Country or region before: China |
|
| CB02 | Change of applicant information | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211112 |
|
| RJ01 | Rejection of invention patent application after publication |