CN113643731A - SRAM reading method, storage device, memory, and electronic device - Google Patents
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Abstract
本申请公开了一种SRAM的读取方法、存储装置、存储器以及电子设备，通过对需要读取数据的第K列第J行的存储单元的接地线施加负电压，加快了第K列存储单元的第一位线和第K列存储单元的第二位线的电压差变化的速度，从而缩短了第K列存储单元的第一位线和第K列存储单元的第二位线的电压差达到预设差值的时间，提高了读取出第K列第J行的存储单元所存储数据的速度，无需增大SRAM存储器的面积，因此可以在提高存储单元的数据读取速度的同时降低SRAM存储器的制造成本。
The present application discloses an SRAM reading method, a storage device, a memory, and an electronic device. By applying a negative voltage to the ground line of the memory cell in the Kth column and the Jth row for which data needs to be read, the speed of the memory cell in the Kth column is accelerated. The speed at which the voltage difference between the first bit line and the second bit line of the memory cell in the Kth column changes, thereby shortening the voltage difference between the first bit line of the memory cell in the Kth column and the second bit line of the memory cell in the Kth column. The time to reach the preset difference increases the speed of reading out the data stored in the memory cells in the Kth column and the Jth row, without increasing the area of the SRAM memory, so the data reading speed of the memory cells can be increased while reducing the Manufacturing cost of SRAM memory.
Description
Technical Field
The present application relates to the field of Static Random-Access memories (SRAMs), and in particular, to a method for reading an SRAM, a storage device, a Memory, and an electronic device.
Background
When the SRAM reads data, two bit lines of an entire column of memory cells to be read are charged in advance. And after the charging is finished, sequentially applying high level to the word lines of the row of the single storage unit according to a preset sequence. When the word line of the row where the current storage unit is located is applied with a high level, the corresponding storage unit pulls down the voltage of one bit line according to the data stored by the corresponding storage unit, pulls up the voltage of the other bit line, and when the voltage difference between the two bit lines meets a preset value, the data of the storage unit can be read. The data reading speed of the SRAM is related to the time period during which the voltage difference between two bit lines of the memory cell reaches a preset value.
The conventional method for improving the data reading speed of the SRAM generally includes: the width of a transistor of the storage unit is increased, so that the on-resistance of the transistor is reduced, the time for pulling up and pulling down the bit line voltage is reduced, and the reading speed of the SRAM is improved. However, this method increases the area of the SRAM and also leads to an increase in manufacturing cost.
Disclosure of Invention
The present application is directed to a method for reading an SRAM, which solves the problem that the manufacturing cost is increased due to the increase of the SRAM area when the data reading speed of the SRAM is increased.
A first aspect of the embodiments of the present application provides an SRAM reading method, which is applied to a memory array including N × M memory cells, where N is a row number of the memory array, and M is a column number of the memory array; applying ground levels to grounding lines of N rows of memory cells, and applying power supply voltages to power supply lines of the N rows of memory cells;
reading the storage data of the memory cell of the Kth column and the J th row comprises the following steps:
precharging a first bit line of a memory cell in a K-th column and a second bit line of the memory cell in the K-th column, so that the voltage of the first bit line and the voltage of the second bit line are equal to the power supply voltage;
applying high level to a word line of a memory cell in a J-th row and applying negative voltage to a grounding line of the memory cell in the J-th row at the same time;
reading the voltage of a first bit line of the Kth column of memory cells and the voltage of a second bit line of the Kth column of memory cells, and obtaining the storage data of the memory cells in the Kth column and the J th row according to the difference value of the voltage of the first bit line of the Kth column of memory cells and the voltage of the second bit line of the Kth column of memory cells;
wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, J is a positive integer less than or equal to N, and K is a positive integer less than or equal to M.
In one embodiment, reading the storage data of the K-th column of storage cells includes:
reading storage data of a memory cell in a Kth column and a J th row;
after reading the storage data of the storage unit in the J-th row of the K column, reading the storage data of the storage unit in the J + 1-th row of the K column; until J +1 is N;
wherein the initial value of J is 1.
In one embodiment, the absolute value of the negative voltage applied to the grounding line of the memory cells in the J-th row is equal to 0.1 to 0.2 times the absolute value of the power supply voltage.
A second aspect of an embodiment of the present application provides an SRAM memory device, including a memory array including N × M memory cells, a row decoder, a column decoder, and a selector; wherein, N is the row number of the memory array, and M is the column number of the memory array;
power supply voltage is applied to power supply lines of the N rows of memory cells; the selector applies ground level to the grounding lines of the N rows of memory cells;
when reading the storage data of the memory cell of the Kth column and the J th row:
the column decoder pre-charges a first bit line of a memory cell in a K-th column and a second bit line of the memory cell in the K-th column to the power supply voltage;
the row decoder applies high level to the word line of the J-th row of memory cells;
the selector applies negative voltage to the grounding line of the J-th row of memory cells;
the column decoder reads the voltage of a first bit line of the memory cell in the Kth column and the voltage of a second bit line of the memory cell in the Kth column, and obtains the storage data of the memory cell in the J-th column and the J-th row according to the difference value of the voltage of the first bit line of the memory cell in the Kth column and the voltage of the second bit line of the memory cell in the Kth column;
wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, J is a positive integer less than or equal to N, and K is a positive integer less than or equal to M.
In one embodiment, the row decoder is further configured to sequentially apply a high level to the word lines of the N rows of memory cells.
In one embodiment, the absolute value of the negative voltage output by the selector is equal to 0.1 to 0.2 times the absolute value of the power supply voltage.
In one embodiment, the memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
a source of the first transistor is connected to a source of the second transistor and to a power line connection terminal of the memory cell, a gate of the first transistor, a drain of the second transistor, a drain of the fourth transistor, and a drain of the sixth transistor are connected in common, a gate of the second transistor, a drain of the first transistor, a drain of the third transistor, and a drain of the fifth transistor are connected in common, a source of the third transistor is connected to a source of the fourth transistor and to a ground line connection terminal of the memory cell, a gate of the fifth transistor is connected to a gate of the sixth transistor and to a word line connection terminal of the memory cell, a source of the fifth transistor is connected to a first bit line connection terminal of the memory cell, and a source of the sixth transistor is connected to a second bit line connection terminal of the memory cell.
A third aspect of the embodiments of the present application provides an SRAM memory, which applies the SRAM reading method according to any one of the first aspects.
A fourth aspect of embodiments of the present application provides an electronic device, comprising the SRAM memory according to the third aspect, a processor, and a computer program stored in the SRAM memory and executable on the processor, the processor implementing the method according to any one of claims 1 to 3 when executing the computer program.
A fifth aspect of embodiments of the present application provides a computer-readable storage medium, in which a computer program is stored, which, when executed by a processor, implements the steps of the method according to any one of the first aspects.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the negative voltage is applied to the grounding wire of the memory cell of the J-th row of the K-th column of the memory cell needing to read data, so that the speed of changing the voltage difference between the first bit line of the memory cell of the K-th column and the second bit line of the memory cell of the K-th column is increased, the time for the voltage difference between the first bit line of the memory cell of the K-th column and the second bit line of the memory cell of the K-th column to reach the preset difference is shortened, the speed of reading the data stored in the memory cell of the J-th row of the K-th column is increased, the area of the SRAM memory is not required to be increased, and the manufacturing cost of the SRAM memory can be reduced while the data reading speed of the memory cell is increased.
Drawings
FIG. 1 is an exemplary circuit schematic diagram of a memory array of an SRAM read method provided by an embodiment of the present application;
FIG. 2 is a flowchart of an example method of an SRAM read method provided by an embodiment of the present application;
FIG. 3 is a flowchart of another example method for reading an SRAM provided by an embodiment of the present application;
FIG. 4 is a schematic circuit diagram of an example of an SRAM memory device provided by an embodiment of the present application;
FIG. 5 is an exemplary schematic circuit diagram of a memory cell provided in an embodiment of the present application
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1, an embodiment of the present invention provides an SRAM reading method applied to a memory array including N × M memory cells (shown as B11 … Bk1 … Bm1 … B1j … Bk j … Bmj … B1N … Bk … Bmn), where N is the number of rows of the memory array, M is the number of columns of the memory array, ground is applied to the ground lines (shown as VSS1 … VSSj … VSSn) of the N rows of memory cells, and a power supply voltage is applied to the power supply lines (shown as VDD1 … VDDj … VDDn) of the N rows of memory cells. Wherein N is an integer of 2 or more, and M is an integer of 2 or more.
The storage units in the same row share one grounding wire, and the storage units in the N rows comprise N grounding wires; the memory cells in the same row share one power line, and the memory cells in N rows comprise N power lines; the memory cells in the same row share one word line, and the memory cells in the N rows comprise N word lines (shown as WL1 … WLj … WLn); the memory cells of the same column share a first bit line and a second bit line, and the memory cells of M columns include M first bit lines (shown as BL1 … BLk … BLm) and M second bit lines (shown as BLB1 … BLBk … BLBm).
Referring to fig. 2, reading the storage data of the memory cell Bkj (J is a positive integer less than or equal to N, and K is a positive integer less than or equal to M) in the jth column and jth row includes the following steps:
s11: the first bit line BLk of the memory cell of the K-th column and the second bit line BLBk of the memory cell of the K-th column are precharged such that the voltage of the first bit line and the voltage of the second bit line are equal to the power supply voltage.
When the storage data of the memory cell Bkj in the jth column and jth row needs to be read, the first bit line BLk of the memory cell in the kth column and the second bit line BLBk of the memory cell in the kth column are precharged until the voltage of the first bit line and the voltage of the second bit line are equal to the power supply voltage. In a specific real-time manner, the first bit line BLk of the K-th column of memory cells and the second bit line BLBk of the K-th column of memory cells may be charged by the power supply, and the charging operation of the first bit line BLk of the K-th column of memory cells and the second bit line BLBk of the K-th column of memory cells is stopped after a preset time, so that the voltages of the first bit line BLk of the K-th column of memory cells and the second bit line BLBk of the K-th column of memory cells are equal to the power supply voltage after the preset time; or the first bit line BLk of the K-th column of memory cells and the second bit line BLBk of the K-th column of memory cells may be charged by a power supply, and the voltage of the first bit line BLk of the K-th column of memory cells and the voltage of the second bit line BLBk of the K-th column of memory cells are detected at the same time, and when both the voltage of the first bit line BLk of the K-th column of memory cells and the voltage of the second bit line BLBk of the K-th column of memory cells reach the power supply voltage, the charging of them is stopped. The preset time can be set according to actual conditions, and the application is not limited herein.
S12: the voltage of the first bit line BLk of the memory cell in the K-th column and the voltage of the second bit line BLBk of the memory cell in the K-th column are read by applying a negative voltage to the ground line VSSj of the memory cell in the J-th row while applying a high level to the word line WLj of the memory cell in the J-th row.
After the voltage of the first bit line BLk of the memory cell in the Kth column and the voltage of the second bit line BLBk of the memory cell in the Kth column reach the power supply voltage, a high level is applied to the word line WLj of the memory cell in the J-th row, and meanwhile, a negative voltage is applied to the ground line VSSj of the memory cell in the J-th row. When the word line WLj of the memory cell in the jth row applies a high level, the memory cell Bkj in the jth column and jth row enters a data read state.
In a reading state, if the data stored in the memory cell Bkj in the jth column and jth row is 0, the power supply line applies a power supply voltage to the first bit line BLk of the memory cell in the kth column through the memory cell, so as to keep the voltage value of the first bit line BLk of the memory cell in the kth column unchanged; the ground line applies a negative voltage to the first bit line BLk of the K-th column of memory cells through the memory cell, thereby pulling down the voltage of the first bit line BLk of the K-th column of memory cells. Because the negative voltage is applied to the wire ground of the jth column and jth row, the speed of pulling down the voltage of the first bit line BLk of the memory cell in the kth column is increased, and therefore, the time that the voltage difference between the first bit line BLk of the memory cell in the kth column and the second bit line BLBk of the memory cell in the kth column is less than the first preset voltage difference (the corresponding voltage difference when the data stored in the memory cell Bkj is 0) can be shortened. Similarly, if the data stored in the memory cell Bkj in the jth column and jth row is 1, the time that the voltage difference between the first bit line BLk of the memory cell in the kth column and the second bit line BLBk of the memory cell in the kth column is greater than the second predetermined voltage difference (the corresponding voltage difference when the data stored in the memory cell Bkj is 1) can be shortened. Besides, the grounding lines VSSj of the memory cells in the J-th row apply negative voltage, and the grounding lines of the memory cells in the other rows keep applying ground level, so the voltage difference between the power lines and the grounding lines of the memory cells in the other rows keeps unchanged, and the memory cells in the other rows cannot have the problems of increased leakage current, increased static power consumption, data inversion and the like.
S13: and obtaining the storage data of the memory cell BKj in the J-th row in the K-th column according to the difference between the voltage of the first bit line BLk of the memory cell in the K-th column and the voltage of the second bit line BLBk of the memory cell in the K-th column.
When the storage data of the memory cell Bkj in the jth column and jth row is 0, and when the difference between the voltage of the first bit line BLk of the memory cell in the kth column and the voltage of the second bit line BLBk of the memory cell in the kth column is smaller than the first preset voltage difference, the storage data of the memory cell Bkj in the jth column and jth row is read to be 0 according to the difference between the voltage of the first bit line BLk of the memory cell in the kth column and the voltage of the second bit line BLBk of the memory cell in the kth column. When the storage data of the memory cell Bkj in the jth column and jth row is 1, reading the storage data of the memory cell Bkj in the jth column and jth row as 1 according to the difference between the voltage of the first bit line BLk of the memory cell in the kth column and the voltage of the second bit line BLBk of the memory cell in the kth column when the difference between the voltage of the first bit line BLk of the memory cell in the kth column and the voltage of the second bit line BLBk of the memory cell in the kth column is greater than a second preset voltage difference.
According to the SRAM reading method, the negative voltage is applied to the ground line of the memory cell BKj of the J-th row of the K-th column of the memory cell needing to read data, the speed of changing the voltage difference between the first bit line BLk of the memory cell of the K-th column and the second bit line BLBk of the memory cell of the K-th column is increased, the time for the voltage difference between the first bit line BLk of the memory cell of the K-th column and the second bit line BLBk of the memory cell of the K-th column to reach the preset difference is shortened, the speed for reading the data stored in the memory cell BKj of the J-th row of the K-th column is increased, the area of the SRAM memory is not required to be increased, and the manufacturing cost of the SRAM memory can be reduced while the data reading speed of the memory cell is increased.
Referring to fig. 3, in an embodiment, reading the storage data of the kth row of memory cells may include the following steps:
s21: and reading the storage data of the memory cell BKj in the Kth column and the J th row.
When reading N storage data of the memory cell in the Kth column, the initial value of J is 1, and the storage data of the memory cell in the 1 st row in the Kth column is read. The steps performed to read the storage data of the 1 st row of the K-th column include the detailed steps of S11 to S13, S11 to S13, please refer to the above description of the embodiments.
S22: after reading the storage data of the memory cell Bkj in the jth column and jth row, the storage data of the memory cell in the jth column and jth +1 row is read until J +1 is equal to N.
After reading the data of the memory cell in the kth column and row 1, the memory data of the memory cell in the kth column and row 1 and the memory data of the memory cell in the kth column and row 2 are read. After reading the data of the memory cell in the 2 nd row in the K column, the memory cell in the next row in the 2 nd row in the K column starts to be read, that is, the memory cell in the 3 rd row in the K column is read, and so on. The data reading logic of the K-th column of memory cells is simple and easy to realize, so that the cost is reduced.
And after the storage data of the storage unit in the Nth row of the Kth column is read, stopping reading the storage data of the storage unit in the Kth column.
In one embodiment, the absolute value of the negative voltage applied to the ground line VSSj of the memory cells in row J is equal to 0.1 to 0.2 times the absolute value of the power supply voltage.
In this embodiment, the absolute value of the negative voltage applied to the ground line VSSj of the jth row of memory cells is equal to 0.1 to 0.2 times the absolute value of the power supply voltage, so that the data reading speed of the memory cell Bkj in the jth column and jth row can be effectively increased, and the problem of excessive leakage current or data inversion caused by the memory cells in the jth rows in the remaining columns and jth rows is avoided.
Referring to fig. 4, an SRAM memory device according to an embodiment of the present invention is further provided, and as shown in fig. 4, the SRAM memory device according to an embodiment of the present invention includes a memory array 100 including N × M memory cells (shown as B11 … Bk1 … Bm1 … B1j … Bk … Bmj … B1N … Bk … Bmn), a row decoder 200, a column decoder 300, and a selector 400.
Where N is the number of rows in the memory array 100 and M is the number of columns in the memory array 100.
The power supply lines (shown as VDD1 … VDDj … VDDnn in the figure) of the N rows of memory cells all apply power supply voltages; the selector 400 applies a ground level to the ground lines (shown as VSS1 … VSSj … VSSn) of the N rows of memory cells.
When reading the storage data of the memory cell Bkj of the Kth column and the J th row:
the column decoder 300 precharges the first bit line BLk of the memory cell of the K-th column and the second bit line BLBk of the memory cell of the K-th column to a power supply voltage;
the row decoder 200 applies a high level to the word line WLj of the jth row of memory cells;
the selector 400 applies a negative voltage to the ground line VSSj of the memory cells in the jth row;
the column decoder 300 reads the voltage of the first bit line BLk of the memory cell in the kth column and the voltage of the second bit line BLBk of the memory cell in the kth column, and obtains the storage data of the memory cell Bkj in the jth column and the jth row according to the difference between the voltage of the first bit line BLk of the memory cell in the kth column and the voltage of the second bit line BLBk of the memory cell in the kth column;
wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, J is a positive integer less than or equal to N, and K is a positive integer less than or equal to M.
In one embodiment, the row decoder 200 is further configured to sequentially apply high levels to word lines (shown as WL1 … WLj … WLn) of the N rows of memory cells.
In one embodiment, the absolute value of the negative voltage output by the selector 400 is equal to 0.1 to 0.2 times the absolute value of the power supply voltage.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a circuit structure of the memory cell Bkj in the jth column and the jth row, and it can be understood that the circuit structures of the other memory cells are the same as the circuit structure of the memory cell Bkj in the jth column and the jth row. The memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor.
The source of the first transistor is connected with the source of the second transistor and is connected to the power line connection end of the storage unit, the grid of the first transistor, the drain of the second transistor, the drain of the fourth transistor and the drain of the sixth transistor are connected in common, the grid of the second transistor, the drain of the first transistor, the drain of the third transistor and the drain of the fifth transistor are connected in common, the source of the third transistor is connected with the source of the fourth transistor and is connected to the ground line connection end of the storage unit, the grid of the fifth transistor is connected with the grid of the sixth transistor and is connected to the word line connection end of the storage unit, the source of the fifth transistor is connected to the first bit line connection end of the storage unit, and the source of the sixth transistor is connected to the second bit line connection end of the storage unit.
The first transistor and the second transistor are P-type transistors, and the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are N-type transistors.
In this embodiment, when the storage data of the memory cell Bkj in the jth column and jth row is 0, both the first transistor and the fourth transistor are turned off, and both the second transistor and the third transistor are turned on; when the storage data of the memory cell Bkj in the jth column and jth row is 1, the first transistor and the fourth transistor are both turned on, and the second transistor and the third transistor are both turned off.
When the storage data of the memory cell Bkj in the jth column and jth row is 0, the storage data of the memory cell Bkj in the jth column and jth row is read. The first bit line BLk of the memory cell of the K-th column and the second bit line BLBk of the memory cell of the K-th column are precharged to the power voltage, and then the high level is applied to the bit line of the J-th row. At this time, the fifth transistor and the sixth transistor are both turned on. The power voltage of the power line acts on the second bit line BLBk of the K-th column of memory cells through the second transistor and the sixth transistor, so that the voltage of the second bit line BLBk of the K-th column of memory cells is kept constant; the negative voltage of the ground line is applied to the first bit line BLk of the K-th column of memory cells through the third transistor and the fifth transistor, so that the voltage of the first bit line BLk of the K-th column of memory cells is reduced from the power supply voltage. When the voltage difference between the voltage of the first bit line BLk of the memory cell in the kth column and the voltage of the second bit line BLBk of the memory cell in the kth column is less than the first preset voltage, the column decoder 300 reads out the stored data of the memory cell Bkj in the jth row in the kth column to be 0. Similarly, when the storage data of the memory cell Bkj in the jth column and jth row is 1, and the voltage difference between the voltage of the first bit line BLk of the memory cell in the kth column and the voltage of the second bit line BLBk of the memory cell in the kth column is greater than or equal to the second preset voltage, the column decoder 300 reads that the storage data of the memory cell Bkj in the jth column and jth row is 1.
The embodiment of the present application further provides an SRAM memory, which employs the SRAM reading method according to any one of the above embodiments, because the SRAM memory of the present embodiment employs the SRAM reading method according to any one of the above embodiments, the SRAM memory of the present embodiment at least includes the beneficial effects corresponding to the SRAM reading method according to any one of the above embodiments.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 6, the electronic apparatus 6 of this embodiment includes: at least one processor 60 (only one processor is shown in fig. 6), an SRAM memory 61, and a computer program 62 stored in the SRAM memory 61 and operable on the at least one processor 60, the steps in any of the various SRAM reading method embodiments described above being implemented when the computer program 62 is executed by the processor 60.
The electronic device 6 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The electronic device 6 may include, but is not limited to, a processor 60, a memory 61. Those skilled in the art will appreciate that fig. 6 is merely an example of the electronic device 6, and does not constitute a limitation of the electronic device 6, and may include more or less components than those shown, or combine some of the components, or different components, such as an input-output device, a network access device, etc.
The Processor 60 may be a Central Processing Unit (CPU), and the Processor 60 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules, so as to perform all or part of the functions described above. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer readable storage medium and used by a processor to implement the steps of the embodiments of the methods described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/electronic device, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method for reading SRAM is characterized in that the method is applied to a storage array comprising N × M storage units, wherein N is the row number of the storage array, and M is the column number of the storage array; applying ground levels to grounding lines of N rows of memory cells, and applying power supply voltages to power supply lines of the N rows of memory cells;
reading the storage data of the memory cell of the Kth column and the J th row comprises the following steps:
precharging a first bit line of a memory cell in a K-th column and a second bit line of the memory cell in the K-th column, so that the voltage of the first bit line and the voltage of the second bit line are equal to the power supply voltage;
applying high level to a word line of a memory cell in a J-th row and applying negative voltage to a grounding line of the memory cell in the J-th row at the same time;
reading the voltage of a first bit line of the Kth column of memory cells and the voltage of a second bit line of the Kth column of memory cells, and obtaining the storage data of the memory cells in the Kth column and the J th row according to the difference value of the voltage of the first bit line of the Kth column of memory cells and the voltage of the second bit line of the Kth column of memory cells;
wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, J is a positive integer less than or equal to N, and K is a positive integer less than or equal to M.
2. The method of claim 1, wherein reading the stored data of the K column of memory cells comprises:
reading storage data of a memory cell in a Kth column and a J th row;
after reading the storage data of the storage unit in the J-th row of the K column, reading the storage data of the storage unit in the J + 1-th row of the K column; until J +1 is N;
wherein the initial value of J is 1.
3. The method of claim 1, wherein an absolute value of the negative voltage applied to the ground line of the jth row of memory cells is equal to 0.1 to 0.2 times an absolute value of a power supply voltage.
4. An SRAM memory device comprises a memory array including N × M memory cells, a row decoder, a column decoder, and a selector; wherein, N is the row number of the memory array, and M is the column number of the memory array;
power supply voltage is applied to power supply lines of the N rows of memory cells; the selector applies ground level to the grounding lines of the N rows of memory cells;
when reading the storage data of the memory cell of the Kth column and the J th row:
the column decoder pre-charges a first bit line of a memory cell in a K-th column and a second bit line of the memory cell in the K-th column to the power supply voltage;
the row decoder applies high level to the word line of the J-th row of memory cells;
the selector applies negative voltage to the grounding line of the J-th row of memory cells;
the column decoder reads the voltage of a first bit line of the memory cell in the Kth column and the voltage of a second bit line of the memory cell in the Kth column, and obtains the storage data of the memory cell in the J-th column and the J-th row according to the difference value of the voltage of the first bit line of the memory cell in the Kth column and the voltage of the second bit line of the memory cell in the Kth column;
wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, J is a positive integer less than or equal to N, and K is a positive integer less than or equal to M.
5. The memory device of claim 4, wherein the row decoder is further configured to sequentially apply a high level to the word lines of the N rows of memory cells.
6. The memory device of claim 4 wherein the absolute value of the negative voltage output by the selector is equal to 0.1 to 0.2 times the absolute value of the supply voltage.
7. The memory device according to claim 4, wherein the memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
a source of the first transistor is connected to a source of the second transistor and to a power line connection terminal of the memory cell, a gate of the first transistor, a drain of the second transistor, a drain of the fourth transistor, and a drain of the sixth transistor are connected in common, a gate of the second transistor, a drain of the first transistor, a drain of the third transistor, and a drain of the fifth transistor are connected in common, a source of the third transistor is connected to a source of the fourth transistor and to a ground line connection terminal of the memory cell, a gate of the fifth transistor is connected to a gate of the sixth transistor and to a word line connection terminal of the memory cell, a source of the fifth transistor is connected to a first bit line connection terminal of the memory cell, and a source of the sixth transistor is connected to a second bit line connection terminal of the memory cell.
8. An SRAM memory characterized in that the SRAM reading method according to any one of claims 1 to 3 is applied.
9. An electronic device comprising the SRAM memory of claim 8, a processor, and a computer program stored in the SRAM memory and executable on the processor, the processor implementing the method of any one of claims 1 to 3 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 3.
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