CN113630935B - Method and device for reducing capacitance howling - Google Patents
Method and device for reducing capacitance howling Download PDFInfo
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- CN113630935B CN113630935B CN202110915365.7A CN202110915365A CN113630935B CN 113630935 B CN113630935 B CN 113630935B CN 202110915365 A CN202110915365 A CN 202110915365A CN 113630935 B CN113630935 B CN 113630935B
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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Abstract
The application discloses a method for reducing capacitance howling, which comprises the following steps: obtaining a target bit number of the resolution of the pulse width modulation signal; the split target number of bits is at least a first sub-number of bits and a second sub-number of bits; wherein the second number of sub-bits is less than the first number of sub-bits, the first number of sub-bits is less than or equal to the howling number of bits threshold; determining non-jitter bits of the digital quantity to be modulated according to the first sub-bit number, and determining jitter bits of the digital quantity to be modulated according to the second sub-bit number; modulating a non-jitter bit of a digital quantity to be modulated and a pulse width modulation signal of a bit number of the non-jitter bit to obtain a first signal, and performing jitter modulation on the jitter bit of the digital quantity to be modulated to obtain a second signal; the first signal and the second signal are added to increase the equivalent number of significant bits of the resolution of the pulse width modulated signal. The method improves the equivalent effective bit number in a digital jitter mode under the condition of not changing the original bit number of the pulse width modulation signal, thereby not only meeting the current level requirement of high resolution, but also not generating capacitor howling.
Description
Technical Field
The application relates to the technical field of light-emitting diode (LED) control, in particular to a method and a device for reducing capacitance howling.
Background
Capacitor squeal refers to the phenomenon that a capacitor on a circuit board deforms to cause the circuit board to vibrate to generate noise. For example, after alternating current is applied to a ceramic capacitor welded on a circuit board, the ceramic capacitor is deformed to stretch in directions perpendicular to and parallel to the circuit board, respectively, thereby inducing vibration of the circuit board. If the vibration frequency of the circuit board is within the audible range of the human ear (20 Hz-20 KHz), the capacitor howling can be heard.
In a light emitting diode (LIGHT EMITTING diode, LED) control scene, in order for the LED to exhibit a better display effect when displaying an image, it is necessary to increase the resolution of LED driving. Typically, resolutions typically require over 9 bits and even higher up to 16 bits, making the color rich and fine.
While achieving rich colors requires high resolution current levels. For example, by means of pulse width modulation (pulse width modulation, PWM) to obtain a high resolution current level. Specifically, a PWM signal having a higher number of original bits of resolution is output, but as the number of original bits of the resolution of the PWM signal increases, a problem of capacitive howling occurs. The problem of capacitive howling is also reduced, for example, by increasing the frequency of the active crystal oscillator (Oscillator Crystal, OSC). However, as the frequency of the active crystal increases, additional circuit costs are incurred and electromagnetic interference (Electromagnetic Interference, EMI) is also incurred.
Disclosure of Invention
In order to solve the technical problems, the application provides a method for reducing capacitor howling, which improves the equivalent effective bit number of the resolution of a pulse width modulation signal in a digital jitter manner under the condition of not changing the original bit number of the pulse width modulation signal, thereby not only meeting the current level requirement of high resolution, but also not generating capacitor howling. The application also provides a device, a device and a medium for reducing capacitance howling.
The embodiment of the application discloses the following technical scheme:
in a first aspect, the present application provides a method for reducing capacitive howling, including:
obtaining a target bit number of the resolution of the pulse width modulation signal;
Splitting the target number of bits into at least a first sub-number of bits and a second sub-number of bits; wherein the second sub-bit number is smaller than the first sub-bit number, and the first sub-bit number is smaller than or equal to a howling bit number threshold;
determining non-jitter bits of the digital quantity to be modulated according to the first sub-bit number, and determining jitter bits of the digital quantity to be modulated according to the second sub-bit number;
modulating the non-jitter bit of the digital quantity to be modulated and a pulse width modulation signal of the bit number of the non-jitter bit to obtain a first signal, and performing jitter modulation on the jitter bit of the digital quantity to be modulated to obtain a second signal;
The first signal and the second signal are added to increase the equivalent number of significant bits of the resolution of the pulse width modulated signal.
As a possible implementation manner, the method further includes:
And outputting the pulse width modulation signal.
As a possible implementation manner,
The step of performing jitter modulation on the jitter bit of the digital quantity to be modulated to obtain a second signal includes:
performing jitter modulation on the jitter bits of the digital quantity to be modulated through a decoder to obtain a second signal; the decoder comprises a preset corresponding relation between the digital quantity to be modulated and the second signal.
As a possible implementation manner, the second sub-bit number is less than or equal to a jitter bit number threshold.
As a possible implementation manner,
The determining the non-jitter bit of the digital quantity to be modulated according to the first sub-bit number comprises the following steps:
Bits corresponding to the first sub-bit number are continuously intercepted from the highest bit of the digital quantity to be modulated as non-jitter bits.
As a possible implementation manner,
The determining the jitter bit of the digital quantity to be modulated according to the second sub-bit number comprises the following steps:
bits corresponding to the second sub-bit number are successively intercepted from the lowest bit of the digital quantity to be modulated as dither bits.
In a second aspect, the present application provides an apparatus for reducing capacitive howling, including:
the acquisition module is used for acquiring the target bit number of the resolution ratio of the pulse width modulation signal;
The splitting module is used for splitting the target digit into at least a first sub-digit and a second sub-digit; wherein the second sub-bit number is smaller than the first sub-bit number, and the first sub-bit number is smaller than or equal to a howling bit number threshold;
The modulation module is used for determining non-jitter bits of the digital quantity to be modulated according to the first sub-bit number and determining jitter bits of the digital quantity to be modulated according to the second sub-bit number; modulating the non-jitter bit of the digital quantity to be modulated and a pulse width modulation signal of the bit number of the non-jitter bit to obtain a first signal, and performing jitter modulation on the jitter bit of the digital quantity to be modulated to obtain a second signal;
and the synthesis module is used for adding the first signal and the second signal to improve the equivalent effective bit number of the resolution of the pulse width modulation signal.
As a possible implementation manner, the apparatus further includes: an output module;
The output module is used for outputting the pulse width modulation signal.
As a possible implementation manner, the modulation module is specifically configured to perform jitter modulation on the jitter bit of the digital quantity to be modulated through a decoder to obtain a second signal; the decoder comprises a preset corresponding relation between the digital quantity to be modulated and the second signal.
As a possible implementation manner, the second sub-bit number is less than or equal to a jitter bit number threshold.
As a possible implementation manner, the modulation module is specifically configured to continuously intercept, from the highest bit of the digital quantity to be modulated, a bit corresponding to the first sub-bit number as a non-jittery bit.
As a possible implementation manner, the modulation module is specifically configured to continuously intercept, from the least significant bit of the digital quantity to be modulated, a bit corresponding to the second sub-bit number as the jitter bit.
In a third aspect, the present application provides an apparatus comprising a memory and a processor;
the processor is configured to execute instructions in the memory to cause the apparatus to perform any one of the possible methods of the first aspect described above.
In a fourth aspect, the present application provides a computer readable storage medium comprising instructions for instructing an apparatus according to the third aspect to perform any one of the possible methods according to the first aspect.
As can be seen from the technical scheme, the application has the following advantages:
The application provides a method for reducing capacitance howling, which improves the equivalent effective bit number of an original pulse width modulation signal under the condition of not changing the original bit number of the pulse width modulation signal in a digital dithering mode. Specifically, the method includes obtaining a target number of bits of a resolution of a pulse width modulation signal, splitting the target number of bits into at least two sub-number of bits, for example, a first sub-number of bits and a second sub-number of bits, wherein the second sub-number of bits is smaller than the first sub-number of bits, and the first sub-number of bits is smaller than or equal to a howling number of bits threshold; determining non-jitter bits of the digital quantity to be modulated according to the first sub-bits, determining jitter bits of the digital quantity to be modulated according to the second sub-bits, modulating the non-jitter bits of the digital quantity to be modulated and pulse width modulation signals of the bits of the non-jitter bits to obtain a first signal, performing jitter modulation on the jitter bits of the digital quantity to be modulated to obtain a second signal, and adding the first signal and the second signal to improve the equivalent effective bit number of the resolution of the pulse width modulation signals. Therefore, the method not only meets the current level requirement of high resolution, but also does not generate the problems of capacitor howling and the like, and further, the method improves the equivalent effective digit of the pulse width modulation signal in a pure digital control mode, does not need to additionally increase a hardware circuit, and reduces the cost.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a monolithic laminated ceramic capacitor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a piezoelectric effect according to an embodiment of the present application;
fig. 3 is a flowchart of a method for reducing capacitive howling according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a digital dithering according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a two-bit digital dithering according to an embodiment of the present application;
fig. 6 is a schematic diagram of an apparatus for reducing capacitive howling according to an embodiment of the present application.
Detailed Description
In order to make the present application better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Technical terms referred to in the present application will be described in the following for the convenience of those skilled in the art.
Capacitor squeal refers to the phenomenon that a capacitor on a circuit board deforms to cause the circuit board to vibrate to generate noise. In general, most of capacitors capable of generating howling are chip-type laminated ceramic capacitors (multi-LAYER CERAMIC capacitors, MLCCs). As shown in fig. 1, fig. 1 shows a schematic diagram of a chip-type laminated ceramic capacitor. The capacitor is formed by overlapping ceramic dielectric films printed with electrodes in a staggered mode, forming a ceramic chip through one-time high-temperature sintering, sealing metal layers at two ends of the chip, wherein terminal electrodes (metal layers) of the chip-type laminated ceramic capacitor can comprise a copper bottom layer 11, a nickel coating 12, a tin coating 13 and the like.
For a better understanding of capacitive howling, the piezoelectric effect is described below.
Piezoelectric effect: when pressure, tension and tangential force are applied to the crystal without the symmetry center, dielectric polarization proportional to the stress occurs, and positive and negative charges appear on two end faces of the crystal, which is called positive piezoelectric effect; conversely, when an electric field is applied to the crystal to induce polarization, deformation or mechanical stress proportional to the electric field strength is generated, and this phenomenon is called an inverse piezoelectric effect. The positive piezoelectric effect and the inverse piezoelectric effect are collectively referred to as piezoelectric effect.
Capacitor howling belongs to the category of inverse piezoelectric effect, under the action of an external electric field, a ceramic medium can stretch and deform, and obvious howling noise can be generated when the degree of stretch and deformation is relatively severe. As shown in fig. 2, the piezoelectric effect is caused by the ferroelectric property of the ceramic dielectric, and the monolithic laminated ceramic capacitor is deformed in a direction (Z axis) parallel to the circuit board (X axis and Y axis) after the alternating current is applied. Because the capacitor is welded on the circuit board, the deformation of the capacitor can pull the circuit board, so that the surface of the circuit board vibrates, and when the vibration frequency is within the audible range of human ears (20 Hz-20 KHz), the capacitor whistle can be heard.
With the progress of the age, the LED lamp is more and more widely applied to the life of people. In a Light Emitting Diode (LED) control scene, in order for the LED to exhibit a better display effect when displaying an image. For example, from monochrome to color to true color, the image display effect is becoming more and more rich and more similar to the displayed color. While in order to present a better display effect, it is necessary to increase the resolution of the LED driving. Typically, resolution typically needs to be over 9 bits and even up to 16 bits to make the color rich and fine.
Currently, the industry adopts high resolution current levels to increase color richness. For example, a PWM signal with a higher number of original bits of resolution is used to obtain a high-resolution current level, but as the number of original bits of the resolution of the PWM signal increases, a problem of capacitive howling occurs. In some implementations, the problem of capacitive howling can also be reduced by increasing the frequency of the active crystal, but with the increase in the frequency of the active crystal, additional circuit costs are incurred and electromagnetic interference phenomena can occur.
In view of the above, the embodiments of the present application provide a method for reducing capacitive howling, which can be performed by a signal processor. Specifically, the method comprises the following steps: the signal processor obtains a target bit number of the resolution of the pulse width modulation signal, splits the target bit number into at least a first sub bit number and a second sub bit number, wherein the second sub bit number is smaller than the first sub bit number, the first sub bit number is smaller than or equal to a howling bit number threshold value, a non-jitter bit of the digital quantity to be modulated is determined according to the first sub bit number, a jitter bit of the digital quantity to be modulated is determined according to the second sub bit number, the non-jitter bit of the digital quantity to be modulated and the pulse width modulation signal of the bit number of the non-jitter bit are modulated to obtain a first signal, the jitter bit of the digital quantity to be modulated is subjected to jitter modulation to obtain a second signal, and then the first signal and the second signal are added to improve the equivalent effective bit number of the resolution of the pulse width modulation signal.
The method improves the equivalent effective bit number of the pulse width modulation signal in a digital dithering mode under the condition of not changing the original bit number of the original pulse width modulation signal in the digital dithering mode. The method not only meets the current level requirement of high resolution, but also does not generate the problems of capacitor howling and the like, and further improves the equivalent effective digit of the pulse width modulation signal in a pure digital control mode, does not need to additionally increase a hardware circuit, and reduces the cost.
In order to make the technical scheme of the application clearer and easier to understand, the method for reducing the capacitor howling provided by the embodiment of the application is described below in terms of a signal processor.
As shown in fig. 3, the present application provides a method for reducing capacitive howling, which includes the following steps:
s301: the signal processor obtains a target number of bits for a resolution of the pulse width modulated signal.
The target number of bits refers to the number of bits of resolution of driving the LED pulse width modulation signal in the case of color enrichment, for example 9 bits, 16 bits. The signal processor may obtain the target number of bits of the resolution in a variety of ways, and in some implementations, the signal processor may determine the target number of bits according to the color level selected by the user based on a correspondence of a preset color level to the target number of bits. In other implementations, the signal processor may also directly receive a user-configured target number of bits to obtain the target number of bits.
The application is not limited to a specific manner of acquiring the target bit number by the signal processor, and a person skilled in the art can select the target bit number according to actual needs.
S302: the signal processor splits the target number of bits into at least a first sub-number of bits and a second sub-number of bits.
The present application is not limited to splitting the target number of bits into two sub-numbers, and in some embodiments, the target number of bits may be split into more sub-numbers, such as three sub-numbers, four sub-numbers. The sum of the plurality of sub-digits is the target digit. For convenience of description, the following description will take the split target number of bits as two sub-numbers as an example.
In some embodiments, the signal processor splits the target number of bits into a first number of sub-bits and a second number of sub-bits, the second number of sub-bits being less than the first number of sub-bits, the first number of sub-bits being less than or equal to a howling number of bits threshold. The howling bit number threshold refers to a threshold value of the number of bits of the resolution of the pulse width modulation signal when howling occurs.
Please refer to the following table 1:
In table 1, the first row represents the frequency variation of the active crystal oscillator and the first column represents the variation of the PWM signal resolution.
Taking 16MHz as an example of the frequency of an active crystal oscillator, when the resolution of PWM signals is 8 bits and 9 bits, the carrier frequency is 62.5KHz and 31.25KHz respectively, and when the resolution of PWM signals is 12 bits, the carrier frequency is 3.9KHz, and at this time, the frequency is in the audible range of human ears (20 Hz-20 KHz), and capacitor howling can be heard. In some embodiments, 9 bits may be used as the howling bit number threshold, and capacitive howling is considered to occur when the PWM signal exceeds 9 bits.
For ease of understanding, taking the example of a target bit number of 12 bits, the signal processor may split the target bit number into 9 bits and 3 bits. Wherein 9 bits are the first sub-bit number and 3 bits are the second sub-bit number. In some embodiments, the second sub-bit number is less than or equal to a jitter bit number threshold, where the jitter bit number threshold refers to a threshold value of the jitter bit number, for example, the jitter bit number threshold may be 3 bits, when the jitter causes the low frequency ripple to be unable to be filtered out by the output filter.
The above description will be given by taking the example that the target bit number is 12 bits, the first sub-bit number is 9 bits, and the second sub-bit number is 3 bits. In other embodiments, the target bit number is 11 bits, the first sub-bit number may be 9 bits, the second sub-bit number may be2 bits, and for example, the target bit number is 10 bits, the first sub-bit number may be 8 bits, and the second sub-bit number may be2 bits. The application is not limited thereto, and a person skilled in the art can select an appropriate splitting manner according to actual needs.
S303: the signal processor determines non-jittered bits of the digital quantity based on the first sub-bit number and jittered bits of the digital quantity based on the second sub-bit number.
The digital quantity includes non-jittered bits and jittered bits, for example, a 12bit digital quantity, which may be [0000 0011 1111].
In some embodiments, the signal processor may determine the number of bits of the non-jittered bits based on the first sub-bit number, e.g., when the first sub-bit number is 9 bits, then determine the number of bits of the non-jittered bits to be 9. In some implementations, the signal processing system successively intercepts bits corresponding to the first sub-bit number from the most significant bit of the digital quantity as non-dithered bits. As in the example above, the non-dithered bits [0000 0011 1] are obtained by successively truncating 9 bits from the most significant bits of the digital quantity [0000 0011 1111], and then taking the remaining low 3 bits as the dithered bits [111].
In some embodiments, the signal processor may determine the number of bits of the dither bit based on the second sub-bit number, e.g., when the second sub-bit number is 3 bits, then determine the number of bits of the dither bit to be 3. In some implementations, the signal processing system successively intercepts bits corresponding to the second sub-bit number from the lowest bit of the digital quantity as dither bits. For example, 3 bits are successively truncated from the lowest bit of the digital quantity [0000 0011 1111] to obtain a wobble bit [111], and then the remaining upper 9 bits are regarded as non-wobble bits [0000 00111 ].
S304: the signal processor adjusts the non-jitter bit of the digital quantity to be modulated and the pulse width modulation signal of the bit number of the non-jitter bit to obtain a first signal, and carries out jitter modulation on the jitter bit of the digital quantity to be modulated to obtain a second signal.
For example, when the non-jittered bit is [00000011 1], the number of bits of the non-jittered bit is 9 bits, and the signal processor modulates the non-jittered bit with a pulse width modulation signal of 9 bits and the digital quantity to be modulated, so as to obtain a first signal. In some embodiments, the first signal is [00000011 1] when the non-jittered bits are [00000011 1].
In some embodiments, the signal processor may perform jitter modulation on the digital quantity of the jittered bits through the decoder to obtain a second signal to be output; the decoder comprises a preset corresponding relation between the digital quantity to be modulated and the second signal. As shown in table 2 below:
| Dithering bits | A second signal to be output |
| 000 | 0000 0000 |
| 001 | 0000 0001 |
| 010 | 0001 0001 |
| 011 | 0010 0101 |
| 100 | 0101 0101 |
| 101 | 0101 1011 |
| 110 | 0111 0111 |
| 111 | 0111 1111 |
The signal processor may obtain the second signal by referring to the table and performing jitter modulation on the jitter bit by the decoder. For example, when the jitter bit is [111], the second signal obtained by jitter modulation by the signal processor is [0111 1111]. For another example, when the jitter bit is [101], the second signal obtained by jitter modulation by the signal processor is [0101 1011].
In other embodiments, when the dither bits include 2 bits, the dither bits may be dither modulated to obtain the second signal to be output, as described in table 3 below.
| Dithering bits | A second signal to be output |
| 00 | 0000 |
| 01 | 0001 |
| 10 | 0101 |
| 11 | 0111 |
For ease of understanding, the principles of digital dithering are described below.
Digital dithering is based on the principle of output voltage averaging. Referring to fig. 4, fig. 4 shows a schematic diagram of digital dithering, from which it can be seen that there is 1 pulse added to the least significant bit (LEAST SIGNIFICANT bits, LSB) of the 4 pulses of a group of 4 pulses. Thus, the average value of the output voltage is increasedOutput voltage values corresponding to the LSBs. Accordingly, the output accuracy of PWM is improvedThe LSBs, namely:
Wherein Δu 0 is a variation of an average value of the output voltage, N PWM is an input bit number of the digital value, and U i is the input voltage.
Based on the principle, the average value of the output voltage can be increasedLSB,The LSBs, as shown in fig. 5, show a schematic diagram of a two-bit digital dither. As can be seen from the figure, the minimum variation of the average value of the output voltage of the two-bit digital dither is:
Where Δu 0min is the minimum variation of the average value of the output voltage, and N dither is 2, i.e. the jitter bit number. Let N eff＝NPWM+Ndither, namely the equivalent effective bit number N eff of PWM output be the sum of N PWM and N dither, so, the equivalent effective bit number of PWM output is improved.
The principle of 2-bit digital dithering is introduced above, and the principle of 3-bit digital dithering is similar, and is not repeated here.
S305: the signal processor adds the first signal and the second signal to increase the equivalent effective number of bits of the resolution of the pulse width modulated signal.
In some embodiments, one switching action refers to outputting one pulse, e.g., 5 switching actions, then outputting 5 pulses. In this embodiment, the signal processor may take a plurality of switching actions of the bits of the second signal as one period, for example, the second signal [0111 1111] includes 8 bits, and then takes 8 switching actions as one period.
For example, the first signal is [0000 0011 1], and each sub-signal in the second signal is, in order, [0000 0000], [0000 0001], [0001 0001], [0010 0101], [0101 0101], [0101 1011], [0111 0111], and [0111 1111]. Taking the second signal as [0111 1111] as an example, the duty ratio of the pulse width modulation signal output by the signal processor in one switching period is And then the average duty cycle of the pulse width modulation signal is obtained as follows:
It can be seen that the minimum variation of the duty cycle of the pulse width modulation signal is As shown in table 4 below.
In some embodiments, the signal processor may output the summed pulse width modulated signal. Therefore, the signal processor realizes that the equivalent effective bit number of the resolution of the pulse width modulation signal is 12 bits on the basis of the original bit 9-bit PWM signal through 3-bit digital dithering. The equivalent effective bit number of the resolution of the pulse width modulation signal is improved without changing the original bit number. Referring to table 1 above, when the frequency of the active crystal oscillator is 16MHz, the equivalent effective bit number of the resolution of the pulse width modulation signal is 12bit by the original bit number of 9bit and 3bit digital dithering mode, the frequency of the carrier wave is 31.25KHz, which is not in the audible range of the human ear (20 Hz-20 KHz), therefore, the capacitor howling will not be heard. Further, by the method, no additional circuit is needed, and cost is saved.
Based on the above description, the present application provides a method for reducing capacitive howling, which improves the equivalent effective bit number of the resolution of the pulse width modulation signal without changing the original bit number of the original pulse width modulation signal by means of digital dithering. Specifically, the method includes obtaining a target number of bits of a resolution of a pulse width modulation signal, splitting the target number of bits into at least two bits, such as a first sub-number of bits and a second sub-number of bits, wherein the second sub-number of bits is smaller than the first sub-number of bits, and the first sub-number of bits is smaller than or equal to a howling number of bits threshold; determining non-jitter bits of the digital quantity according to the first sub-bit number, determining jitter bits of the digital quantity according to the second sub-bit number, modulating pulse width modulation signals of the non-jitter bits of the digital quantity to obtain a first signal, performing jitter modulation on the jitter bits of the digital quantity to obtain a second signal, and adding the first signal and the second signal to improve the equivalent effective bit number of the pulse width modulation signals. Therefore, the method not only meets the current level requirement of high resolution, but also can not generate the problems of capacitor howling and the like, and further, the method improves the equivalent effective bit number of the resolution of the pulse width modulation signal in a pure digital control mode, does not need to additionally increase a hardware circuit, and reduces the cost.
The embodiment of the application also provides a device for reducing capacitance howling, as shown in fig. 6, the device comprises: the device comprises an acquisition module 601, a splitting module 602, a modulation module 603 and a synthesis module 604.
An obtaining module 601, configured to obtain a target number of bits of resolution of the pulse width modulation signal;
A splitting module 602, configured to split the target number of bits into at least a first sub-number of bits and a second sub-number of bits; wherein the second sub-bit number is smaller than the first sub-bit number, and the first sub-bit number is smaller than or equal to a howling bit number threshold;
A modulation module 603, configured to determine a non-jitter bit of a digital quantity to be modulated according to the first sub-bit number, and determine a jitter bit of the digital quantity to be modulated according to the second sub-bit number; modulating the non-jitter bit of the digital quantity to be modulated and a pulse width modulation signal of the bit number of the non-jitter bit to obtain a first signal, and performing jitter modulation on the jitter bit of the digital quantity to be modulated to obtain a second signal;
A synthesizing module 604, configured to add the first signal and the second signal to increase the equivalent effective number of bits of the resolution of the pulse width modulated signal.
As a possible implementation manner, the apparatus further includes: an output module;
The output module is used for outputting the pulse width modulation signal.
As a possible implementation manner, the modulation module 603 is specifically configured to perform jitter modulation on the jitter bit of the digital quantity to be modulated through a decoder to obtain a second signal; the decoder comprises a preset corresponding relation between the digital quantity to be modulated and the second signal.
As a possible implementation manner, the second sub-bit number is less than or equal to a jitter bit number threshold.
As a possible implementation manner, the modulation module 603 is specifically configured to continuously intercept, from the highest bit of the digital quantity to be modulated, a bit corresponding to the first sub-bit number as a non-jittery bit.
As a possible implementation manner, the modulation module 603 is specifically configured to continuously intercept, from the least significant bit of the digital quantity to be modulated, a bit corresponding to the second sub-bit number as a jitter bit.
The embodiment of the application provides equipment, which comprises a memory and a processor;
The processor is configured to execute the instructions in the memory to cause the apparatus to perform any one of the possible methods of the method embodiments described above.
Embodiments of the present application provide a computer-readable storage medium comprising instructions for instructing the above-described apparatus to perform any of the possible methods of the above-described method embodiments.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points. The apparatus embodiments described above are merely illustrative, wherein the units and modules illustrated as separate components may or may not be physically separate. In addition, some or all of the units and modules can be selected according to actual needs to achieve the purpose of the embodiment scheme. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The above is merely a preferred embodiment of the present application, and is not intended to limit the present application in any way. While the application has been described with reference to preferred embodiments, it is not intended to be limiting. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present application or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application.
Claims (10)
1. A method of reducing capacitive howling, comprising:
obtaining a target bit number of the resolution of the pulse width modulation signal;
Splitting the target number of bits into at least a first sub-number of bits and a second sub-number of bits; wherein the second sub-bit number is smaller than the first sub-bit number, and the first sub-bit number is smaller than or equal to a howling bit number threshold;
determining non-jitter bits of the digital quantity to be modulated according to the first sub-bit number, and determining jitter bits of the digital quantity to be modulated according to the second sub-bit number;
Modulating the non-jitter bit of the digital quantity to be modulated and a pulse width modulation signal with the bit number equal to the bit number of the non-jitter bit to obtain a first signal, and performing jitter modulation on the jitter bit of the digital quantity to be modulated to obtain a second signal;
The first signal and the second signal are added to increase the equivalent number of significant bits of the resolution of the pulse width modulated signal.
2. The method according to claim 1, wherein the method further comprises:
And outputting the pulse width modulation signal.
3. The method of claim 1, wherein dithering the dithered bits of the digital quantity to be modulated to obtain a second signal comprises:
performing jitter modulation on the jitter bits of the digital quantity to be modulated through a decoder to obtain a second signal; the decoder comprises a preset corresponding relation between the digital quantity to be modulated and the second signal.
4. The method of claim 1, wherein the second number of sub-bits is less than or equal to a jitter number of bits threshold.
5. The method of claim 1, wherein said determining non-dithered bits of a digital quantity to be modulated from said first sub-bit number comprises:
Bits corresponding to the first sub-bit number are continuously intercepted from the highest bit of the digital quantity to be modulated as non-jitter bits.
6. The method of claim 1, wherein said determining the dither bits of the digital quantity to be modulated based on the second sub-bit number comprises:
bits corresponding to the second sub-bit number are successively intercepted from the lowest bit of the digital quantity to be modulated as dither bits.
7. An apparatus for reducing capacitive howling, comprising:
the acquisition module is used for acquiring the target bit number of the resolution ratio of the pulse width modulation signal;
The splitting module is used for splitting the target digit into at least a first sub-digit and a second sub-digit; wherein the second sub-bit number is smaller than the first sub-bit number, and the first sub-bit number is smaller than or equal to a howling bit number threshold;
The modulation module is used for determining non-jitter bits of the digital quantity to be modulated according to the first sub-bit number and determining jitter bits of the digital quantity to be modulated according to the second sub-bit number; modulating the non-jitter bit of the digital quantity to be modulated and a pulse width modulation signal with the bit number equal to the bit number of the non-jitter bit to obtain a first signal, and performing jitter modulation on the jitter bit of the digital quantity to be modulated to obtain a second signal;
and the synthesis module is used for adding the first signal and the second signal to improve the equivalent effective bit number of the resolution of the pulse width modulation signal.
8. The apparatus of claim 7, wherein the apparatus further comprises: an output module;
The output module is used for outputting the pulse width modulation signal.
9. The apparatus of claim 7, wherein the modulation module is configured to perform jitter modulation on the jittered bits of the digital quantity to be modulated to obtain a second signal through a decoder; the decoder comprises a preset corresponding relation between the digital quantity to be modulated and the second signal.
10. The apparatus of claim 7, wherein the second number of sub-bits is less than or equal to a jitter number of bits threshold.
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