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CN113626201A - A computer task management method and computer equipment - Google Patents

A computer task management method and computer equipment Download PDF

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CN113626201A
CN113626201A CN202110991931.2A CN202110991931A CN113626201A CN 113626201 A CN113626201 A CN 113626201A CN 202110991931 A CN202110991931 A CN 202110991931A CN 113626201 A CN113626201 A CN 113626201A
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processor
task
arm
arm processor
new task
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CN113626201B (en
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冷迪
陈瑞
李英
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Shenzhen Power Supply Bureau Co Ltd
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Shenzhen Power Supply Bureau Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract

本发明涉及一种计算机任务管理系统及计算机设备，应用于X86和ARM混合架构，包括：第一X86处理器接收新任务；第一X86处理器基于X86复杂指令集分析执行所述新任务所采用的所有复杂指令，根据所述所有复杂指令以及ARM精简指令集判断由第二X86处理器还是ARM处理器执行所述新任务；第一X86处理器根据步骤S20的判断结果，将所述新任务分配至第二X86处理器或ARM处理器，以使得所述第二X86处理器执行所述新任务或所述ARM处理器执行所述新任务。本发明在现有的X86和ARM混合架构处理器系统上加以改进，使其能够同时处理不同指令任务。

Figure 202110991931

The invention relates to a computer task management system and computer equipment, which are applied to the X86 and ARM hybrid architecture, including: a first X86 processor receives a new task; the first X86 processor analyzes and executes the new task based on the X86 complex instruction set. All complex instructions, according to all complex instructions and the ARM reduced instruction set to determine whether the second X86 processor or the ARM processor to perform the new task; the first X86 processor according to the judgment result of step S20, the new task is Assigned to a second X86 processor or an ARM processor such that the second X86 processor executes the new task or the ARM processor executes the new task. The invention improves the existing X86 and ARM mixed architecture processor system, so that it can process different instruction tasks at the same time.

Figure 202110991931

Description

Computer task management method and computer equipment
Technical Field
The invention relates to the technical field of computers, in particular to a computer task management method and computer equipment.
Background
The X86 processor is a CPU architecture processor promoted by Intel, and the X86 processor adopts a complex instruction set, so that the complex computation can be better handled; widely used for PC computers and servers. Meanwhile, the power consumption of the X86 is high, and the heat dissipation requirement is high.
The ARM processor is a RISC microprocessor. The ARM processor is characterized by small volume, low power consumption, low cost and high performance; the instruction execution speed is higher due to the fact that a large number of registers are used; most data operations are done in registers; the addressing mode is flexible and simple, and the execution efficiency is high.
In recent years, in the technical field of information systems, the application of the autonomous controllable core component is more and more extensive. The Feiteng CPU and the Galaxy kylin operating system based on the ARM framework become autonomous controllable core products. Currently, the information system in China is mostly based on an X86 technical system. In the application process of the autonomous controllable product, the system reliability is an important problem to be solved urgently. The length of the instruction executed by the X86-based and ARM mixed-architecture processor is fixed, and only a single instruction can be processed when the instruction is processed, so that the instruction can be detained when a multi-instruction condition is met, and the task cannot be processed in time.
Disclosure of Invention
The invention aims to provide a computer task management method and computer equipment, which are improved on the existing X86 and ARM mixed architecture processor system, so that different instruction tasks can be processed simultaneously.
In order to achieve the above object, an embodiment of the present invention provides a computer task management method applied to an X86 and ARM hybrid architecture, where the method includes the following steps:
step S10, the first X86 processor receives a new task;
step S20, the first X86 processor analyzes all complex instructions adopted for executing the new task based on the X86 complex instruction set, and judges whether the second X86 processor or the ARM processor executes the new task according to all complex instructions and the ARM reduced instruction set;
in step S30, the first X86 processor allocates the new task to the second X86 processor or the ARM processor according to the determination result in step S20, so that the second X86 processor executes the new task or the ARM processor executes the new task.
Preferably, the step S20 includes:
and the first X86 processor acquires all complex instructions adopted for executing the new task by adopting an X86 architecture trial run mode, translates all the complex instructions, judges that the new task is executed by the ARM processor alone or the ARM processor and the second X86 processor execute the new task alternately if at least more than 90% of the complex instructions can be translated into simplified instructions in the ARM simplified instruction set directly, and judges that the new task is executed by the second X86 processor alone.
Preferably, the step S20 includes:
the method comprises the steps that a first X86 processor obtains all complex instructions adopted for executing a new task in an X86 architecture trial operation mode, all the complex instructions are translated, if at least more than 90% of the complex instructions can be directly translated into simplified instructions in an ARM simplified instruction set, the translated instruction amount is not increased by more than 130%, the new task is judged to be executed by an ARM processor alone, or the ARM processor and a second X86 processor alternately execute the new task, and otherwise, the new task is judged to be executed by a second X86 processor alone.
Preferably, the determining whether the new task is executed by the ARM processor alone or the ARM processor alternates with the second X86 processor comprises:
if all the complex instructions can be directly translated into simplified instructions in the ARM simplified instruction set, the ARM processor executes the new task; if a portion of the complex instructions cannot be directly translated into reduced instructions in the ARM reduced instruction set, the new task is executed alternately by the ARM processor and the second X86 processor, the ARM processor processes the portion of the instructions that can be directly translated into reduced instructions in the ARM reduced instruction set, and the second X86 processor processes the portion of the instructions that cannot be directly translated into reduced instructions in the ARM reduced instruction set.
Preferably, the step S30 further includes:
when it is determined at step S20 that the new task is executed alternately by the ARM processor and the second X86 processor, an interrupt point is set for the new task and allocated to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor execute the new task alternately according to the interrupt point.
Preferably, during the process that the second X86 processor and the ARM processor alternately execute the tasks allocated by the first X86 processor,
when the task processed by the second X86 processor reaches an interrupt point, requesting the ARM processor to acquire a related processing result of the ARM processor required by the task processing, performing task interrupt to wait for the related processing result of the ARM processor, and after receiving the related processing result of the ARM processor, continuing to execute the task according to the related processing result of the ARM processor;
when the task processed by the ARM processor reaches an interrupt point, requesting the second X86 processor to acquire a related processing result of the second X86 processor required for processing the task, performing task interrupt to wait for the processing result of the second X86 processor, and after receiving the related processing result of the second X86 processor, continuing to execute the task according to the related processing result of the second X86 processor.
Preferably, the step S30 further includes:
when it is determined at step S20 that the new task is executed by the ARM processor and the second X86 processor alternately, an interrupt point and a priority are set for the new task and allocated to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor alternately execute the new task according to the interrupt point and the priority.
Preferably, during the process that the second X86 processor and the ARM processor alternately execute the tasks allocated by the first X86 processor,
when the second X86 processor receives a request sent by the ARM processor for acquiring a related processing result of the second X86 processor required for processing a task, the request carries a task priority flag, the second X86 processor compares the priority of the task being interrupted by the ARM processor with the priority of the task being processed by the second X86 processor, and the second X86 processor prioritizes the request sent by the ARM processor for acquiring the related processing result of the second X86 processor required for processing the task or the task being processed by the second X86 processor according to the priority comparison result;
when the ARM processor receives a request for acquiring relevant processing results of the ARM processor required by processing tasks, which is sent by the second X86 processor, the request carries a task priority label, the ARM processor compares the priority of the task being interrupted by the second X86 processor with the priority of the task being processed by the ARM processor, and the ARM processor preferentially processes the request for acquiring relevant processing results of the ARM processor required by processing tasks, which is sent by the second X86 processor, or the task being processed by the ARM processor according to the priority comparison result.
Preferably, the processing of the second X86 processor according to the request for obtaining the relevant processing result of the second X86 processor required by the processing task sent by the ARM processor or the task being processed by the second X86 processor by the priority comparison result includes:
when the priority of the task interrupted by the ARM processor is higher, the request for acquiring the relevant processing result of the second X86 processor required by the processing task, sent by the ARM processor, is processed preferentially, the relevant task is processed according to the request of the ARM processor, the processing result is fed back to the ARM processor, and then the task processed by the second X86 processor is continued;
the processing method includes that the ARM processor preferentially processes a request for acquiring a relevant processing result of the ARM processor required by a processing task sent by a second X86 processor or a task being processed by the ARM processor according to a priority comparison result, and includes the following steps:
when the priority of the task being interrupted by the second X86 processor is higher, the request for obtaining the relevant processing result of the ARM processor required by the processing task, sent by the second X86 processor, is processed preferentially, the relevant task is processed according to the request of the second X86 processor, the processing result is fed back to the second X86 processor, and then the task being processed by the ARM processor is continued.
The embodiment of the invention also provides computer equipment which comprises a first X86 processor, a second X86 processor and an ARM processor and is used for realizing the computer task management method.
The embodiment of the invention at least has the following beneficial effects:
the embodiment of the invention is improved on the existing X86 and ARM mixed architecture processor system, so that different instruction tasks can be processed simultaneously, an X86 processor is added for distributing and guiding the execution of the tasks, and the X86 processor and the ARM processor perform operation processing in a division or alternative mode according to the difference of programs or the difference of transactions to be processed, so that the X86 and ARM mixed architecture processor system can process different instruction tasks simultaneously.
Additional features and advantages of embodiments of the invention will be set forth in the description which follows.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a computer task management method according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a computer device according to another embodiment of the present invention.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In addition, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known means have not been described in detail so as not to obscure the present invention.
Referring to fig. 1, an embodiment of the present invention provides a computer task management method applied to an X86 and ARM hybrid architecture, the method including the following steps:
step S10, the first X86 processor receives a new task;
step S20, the first X86 processor analyzes all complex instructions adopted for executing the new task based on the X86 complex instruction set, and judges whether the second X86 processor or the ARM processor executes the new task according to all complex instructions and the ARM reduced instruction set;
in step S30, the first X86 processor allocates the new task to the second X86 processor or the ARM processor according to the determination result in step S20, so that the second X86 processor executes the new task or the ARM processor executes the new task.
Specifically, if the tasks to be processed are suitable for processing by the complex instruction set of X86, the tasks are distributed to the complex instruction set of X86 as much as possible for processing; such as a complex operation, a non-standard task. If the tasks required to be processed are suitable for being processed by the ARM simplified instruction set, the tasks are distributed as much as possible and are processed by the ARM simplified instruction set; such as mathematical operations, image processing, and the like.
The embodiment of the invention is improved on the existing X86 and ARM mixed architecture processor system, so that different instruction tasks can be processed simultaneously, an X86 processor is added for distributing and guiding the execution of the tasks, and the X86 processor and the ARM processor perform operation processing in a division or alternative mode according to the difference of programs or the difference of transactions to be processed, so that the X86 and ARM mixed architecture processor system can process different instruction tasks simultaneously.
In some embodiments, the step S20 includes:
and the first X86 processor acquires all complex instructions adopted for executing the new task by adopting an X86 architecture trial run mode, translates all the complex instructions, judges that the new task is executed by the ARM processor alone or the ARM processor and the second X86 processor execute the new task alternately if at least more than 90% of the complex instructions can be translated into simplified instructions in the ARM simplified instruction set directly, and judges that the new task is executed by the second X86 processor alone.
In some embodiments, the step S20 includes:
the method comprises the steps that a first X86 processor obtains all complex instructions adopted for executing a new task in an X86 architecture trial operation mode, all the complex instructions are translated, if at least more than 90% of the complex instructions can be directly translated into simplified instructions in an ARM simplified instruction set, the translated instruction amount is not increased by more than 130%, the new task is judged to be executed by an ARM processor alone, or the ARM processor and a second X86 processor alternately execute the new task, and otherwise, the new task is judged to be executed by a second X86 processor alone.
In the implementation process of the method, two results appear, a new task is processed by an ARM processor and a second X86 processor in a division manner or alternatively runs, the division manner is simple, and only a single processor is needed to finish the processing in the processing process; for larger tasks, tasks that yield results need to be run alternately through the second X86 processor and the ARM processor, which requires special design, and specifically, in some embodiments, the determining is performed by the ARM processor alone to execute the new task, or the ARM processor is run alternately with the second X86 processor to execute the new task, including:
if all the complex instructions can be directly translated into simplified instructions in the ARM simplified instruction set, the ARM processor executes the new task; if a portion of the complex instructions cannot be directly translated into reduced instructions in the ARM reduced instruction set, the new task is executed alternately by the ARM processor and the second X86 processor, the ARM processor processes the portion of the instructions that can be directly translated into reduced instructions in the ARM reduced instruction set, and the second X86 processor processes the portion of the instructions that cannot be directly translated into reduced instructions in the ARM reduced instruction set.
Further, in some embodiments, the step S30 further includes:
when it is determined at step S20 that the new task is executed alternately by the ARM processor and the second X86 processor, an interrupt point is set for the new task and allocated to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor execute the new task alternately according to the interrupt point.
Further, in the process that the second X86 processor and the ARM processor alternately execute the tasks allocated by the first X86 processor according to the interrupt point,
when the task processed by the second X86 processor reaches an interrupt point, requesting the ARM processor to acquire a related processing result of the ARM processor required by the task processing, performing task interrupt to wait for the related processing result of the ARM processor, and after receiving the related processing result of the ARM processor, continuing to execute the task according to the related processing result of the ARM processor;
when the task processed by the ARM processor reaches an interrupt point, requesting the second X86 processor to acquire a related processing result of the second X86 processor required for processing the task, performing task interrupt to wait for the processing result of the second X86 processor, and after receiving the related processing result of the second X86 processor, continuing to execute the task according to the related processing result of the second X86 processor.
In some embodiments, the step S30, further includes:
when it is determined at step S20 that the new task is executed by the ARM processor and the second X86 processor alternately, setting an interrupt point and a priority to the new task, and assigning the interrupt point and the priority to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor alternately execute the new task according to the interrupt point and the priority;
specifically, the second X86 processor or the ARM processor performs priority comparison on all the tasks being processed or to be processed according to task priorities, and preferentially processes the tasks with higher priorities.
Further, in the process that the second X86 processor and the ARM processor alternately execute the tasks allocated by the first X86 processor according to the interrupt point and the priority,
when the second X86 processor receives a request sent by the ARM processor for obtaining the relevant processing result of the second X86 processor required for processing the task, the request carrying a task priority flag (given by the first X86 processor), the second X86 processor compares the priority of the task being interrupted by the ARM processor with the priority of the task being processed by the second X86 processor, and the second X86 processor prioritizes the request sent by the ARM processor for obtaining the relevant processing result of the second X86 processor required for processing the task or the task being processed by the second X86 processor according to the priority comparison result;
when the ARM processor receives a request for acquiring relevant processing results of the ARM processor required by processing tasks, which is sent by the second X86 processor, the request carries a task priority label (given by the first X86 processor), the ARM processor compares the priority of the task being interrupted by the second X86 processor with the priority of the task being processed by the ARM processor, and the ARM processor preferentially processes the request for acquiring relevant processing results of the ARM processor required by processing tasks, which is sent by the second X86 processor, or the task being processed by the ARM processor according to the priority comparison result;
the data transmission between the second X86 processor and the ARM processor is realized by forwarding through the first X86 processor, that is, the requests and the related processing results between the second X86 processor and the ARM processor are both sent to the first X86 processor by a sender and forwarded to a receiver by the first X86 processor;
when the ARM processor executes a task to a task interrupt point and can continue subsequent processing only when a related processing result which is helped by the second X86 processor to be executed alternately is acquired, the ARM processor makes a request for a part of tasks which need to be processed by the second X86 processor to the first X86 processor, and the first X86 processor sets a priority for the part of tasks and then forwards the priority to the second X86 processor;
when the task executed by the second X86 processor reaches a task interruption point and the subsequent processing can continue without acquiring the related processing result which is helped by the ARM processor to be executed alternately, the second X86 processor requests a part of tasks which need to be processed by the ARM processor to the first X86 processor, and the first X86 processor sets a priority for the part of tasks and then forwards the priority to the ARM processor.
In some embodiments, the processing of the second X86 processor according to the request for obtaining the relevant processing result of the second X86 processor required by the processing task sent by the priority comparison result priority processing ARM processor or the task being processed by the second X86 processor, includes:
when the priority of the task interrupted by the ARM processor is higher, the request for acquiring the relevant processing result of the second X86 processor required by the processing task, sent by the ARM processor, is processed preferentially, the relevant task is processed according to the request of the ARM processor, the processing result is fed back to the ARM processor, and then the task processed by the second X86 processor is continued;
wherein, the processing of the request for obtaining the relevant processing result of the ARM processor required by the processing task sent by the second X86 processor or the task being processed by the ARM processor according to the priority comparison result by the ARM processor includes:
when the priority of the task being interrupted by the second X86 processor is higher, the request for obtaining the relevant processing result of the ARM processor required by the processing task, sent by the second X86 processor, is processed preferentially, the relevant task is processed according to the request of the second X86 processor, the processing result is fed back to the second X86 processor, and then the task being processed by the ARM processor is continued.
Specifically, in the present embodiment, for a task that requires the other party to interrupt the current task processing and perform the insertion processing during the task processing, the following method is implemented: the second X86 processor and the sending party in the ARM processor send the request to the first X86 processor, after receiving the request, the first X86 processor judges the priority of the task being processed by the receiving party, sets a level higher than the priority of the other party for the requested task, and gives the requested task to the other party for priority processing, because the part of tasks needing to be processed by the other party is only few and is processed very fast, the embodiment can avoid the long-time interrupt waiting of the processors in the alternative execution task, thereby improving the efficiency of the alternative execution task.
It should be noted that, in the past, the program interrupt and the priority are both the same processor, the internal setting and allocation is performed, and the scheduling is performed at the chip processing level, and the interrupt and the priority in this embodiment are scheduled at the software level, and the important feature is that, for the X86 and ARM mixed architecture processing, the first X86 processor provided with the preprocessing is scheduled, and the target task is to fully utilize the operation efficiency of different instruction sets of the two processor structures to schedule the program.
Referring to fig. 2, another embodiment of the present invention further provides a computer device, which includes a first X86 processor 1, a second X86 processor 2, and an ARM processor 3, and is configured to implement the steps of the computer task management method according to the above embodiment.
It should be noted that the computer device in this embodiment corresponds to the method in the foregoing embodiment, and therefore, details of the computer device in this embodiment may be obtained by referring to the contents of the method in the foregoing embodiment, which are not described herein again.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1.一种计算机任务管理方法，应用于X86和ARM混合架构，其特征在于，所述方法包括以下步骤：1. a computer task management method, applied to X86 and ARM hybrid architecture, is characterized in that, described method may further comprise the steps: 步骤S10、第一X86处理器接收新任务；Step S10, the first X86 processor receives a new task; 步骤S20、第一X86处理器基于X86复杂指令集分析执行所述新任务所采用的所有复杂指令，根据所述所有复杂指令以及ARM精简指令集判断由第二X86处理器还是ARM处理器执行所述新任务；Step S20, the first X86 processor analyzes all complex instructions used to execute the new task based on the X86 complex instruction set, and judges whether the second X86 processor or the ARM processor executes all complex instructions according to the all complex instructions and the ARM reduced instruction set. describe new tasks; 步骤S30、第一X86处理器根据步骤S20的判断结果，将所述新任务分配至第二X86处理器或ARM处理器，以使得所述第二X86处理器执行所述新任务或所述ARM处理器执行所述新任务。Step S30, the first X86 processor allocates the new task to the second X86 processor or the ARM processor according to the judgment result of the step S20, so that the second X86 processor executes the new task or the ARM processor The processor executes the new task. 2.根据权利要求1所述的计算机任务管理方法，其特征在于，所述步骤S20，包括：2. The computer task management method according to claim 1, wherein the step S20 comprises: 第一X86处理器采用X86架构试运行的方式获取执行所述新任务所采用的所有复杂指令，并对所述所有复杂指令进行翻译，若所述所有复杂指令中至少90％以上能够直接翻译成所述ARM精简指令集中的精简指令，则判断由ARM处理器单独执行所述新任务，或ARM处理器与第二X86处理器交替执行所述新任务，否则，判断由第二X86处理器单独执行所述新任务。The first X86 processor acquires all complex instructions used to execute the new task by using the X86 architecture for trial operation, and translates all complex instructions, if at least 90% of all complex instructions can be directly translated into For the reduced instructions in the ARM reduced instruction set, it is judged that the ARM processor alone executes the new task, or the ARM processor and the second X86 processor alternately execute the new task, otherwise, it is judged that the second X86 processor executes the new task alone Execute the new task. 3.根据权利要求1所述的计算机任务管理方法，其特征在于，所述步骤S20，包括：3. The computer task management method according to claim 1, wherein the step S20 comprises: 第一X86处理器采用X86架构试运行的方式获取执行所述新任务所采用的所有复杂指令，并对所述所有复杂指令进行翻译，若所述所有复杂指令中至少90％以上能够直接翻译成所述ARM精简指令集中的精简指令，且翻译后的指令量增加不超过130％，则判断由ARM处理器单独执行所述新任务，或ARM处理器与第二X86处理器交替执行所述新任务，否则，判断由第二X86处理器单独执行所述新任务。The first X86 processor acquires all complex instructions used to execute the new task by using the X86 architecture for trial operation, and translates all complex instructions, if at least 90% of all complex instructions can be directly translated into The reduced instructions in the ARM reduced instruction set, and the amount of translated instructions does not increase by more than 130%, then it is determined that the ARM processor alone executes the new task, or the ARM processor and the second X86 processor alternately execute the new task. task, otherwise, it is determined that the new task is executed by the second X86 processor alone. 4.根据权利要求2或3所述的计算机任务管理方法，其特征在于，所述判断由ARM处理器单独执行所述新任务，或ARM处理器与第二X86处理器交替执行所述新任务，包括：4. The computer task management method according to claim 2 or 3, wherein the judgment is performed by the ARM processor to perform the new task alone, or the ARM processor and the second X86 processor alternately execute the new task ,include: 若所述所有复杂指令均能够直接翻译成所述ARM精简指令集中的精简指令，则由ARM处理器执行所述新任务；若所述所有复杂指令中的一部分不能够直接翻译成所述ARM精简指令集中的精简指令，则由ARM处理器与第二X86处理器交替执行所述新任务，ARM处理器处理能够直接翻译成所述ARM精简指令集中的精简指令的部分指令，第二X86处理器处理不能够直接翻译成所述ARM精简指令集中的精简指令的部分指令。If all the complex instructions can be directly translated into the reduced instructions in the ARM reduced instruction set, the ARM processor executes the new task; if some of the complex instructions cannot be directly translated into the ARM reduced instructions For the reduced instructions in the instruction set, the ARM processor and the second X86 processor alternately execute the new task. The ARM processor processes some instructions that can be directly translated into the reduced instructions in the ARM reduced instruction set, and the second X86 processor Process some instructions that cannot be directly translated into reduced instructions in the ARM reduced instruction set. 5.根据权利要求4所述的计算机任务管理方法，其特征在于，所述步骤S30，还包括：5. The computer task management method according to claim 4, wherein the step S30 further comprises: 当步骤S20判断由ARM处理器与第二X86处理器交替执行所述新任务时，对所述新任务设置中断点，分配至第二X86处理器或ARM处理器，以使得所述第二X86处理器和所述ARM处理器根据所述中断点交替执行所述新任务。When it is determined in step S20 that the new task is executed alternately by the ARM processor and the second X86 processor, a break point is set for the new task and assigned to the second X86 processor or the ARM processor, so that the second X86 processor The processor and the ARM processor alternately execute the new task according to the interruption point. 6.根据权利要求5所述的计算机任务管理方法，其特征在于，在所述第二X86处理器和所述ARM处理器交替执行所述第一X86处理器分配的任务过程中，6. The computer task management method according to claim 5, wherein, in the process of alternately executing the task assigned by the first X86 processor by the second X86 processor and the ARM processor, 当所述第二X86处理器处理的任务到达中断点时，向所述ARM处理器请求获取处理任务所需的ARM处理器的相关处理结果，进行任务中断等待所述ARM处理器的相关处理结果，并在接收到所述ARM处理器的相关处理结果后，根据所述ARM处理器的相关处理结果继续执行任务；When the task processed by the second X86 processor reaches the interruption point, the ARM processor is requested to obtain the relevant processing result of the ARM processor required for processing the task, and the task is interrupted to wait for the relevant processing result of the ARM processor. , and after receiving the relevant processing result of the ARM processor, continue to perform the task according to the relevant processing result of the ARM processor; 当所述ARM处理器处理的任务到达中断点时，向所述第二X86处理器请求获取处理任务所需的第二X86处理器的相关处理结果，进行任务中断等待所述第二X86处理器的处理结果，并在接收到所述第二X86处理器的相关处理结果后，根据所述第二X86处理器的相关处理结果继续执行任务；When the task processed by the ARM processor reaches the interruption point, request the second X86 processor to obtain the relevant processing results of the second X86 processor required for processing the task, perform task interruption and wait for the second X86 processor and after receiving the relevant processing result of the second X86 processor, continue to perform the task according to the relevant processing result of the second X86 processor; 其中，所述第二X86处理器与所述ARM处理器之间的数据传输通过所述第一X86处理器进行转发实现。Wherein, the data transmission between the second X86 processor and the ARM processor is implemented through forwarding by the first X86 processor. 7.根据权利要求6所述的计算机任务管理方法，其特征在于，所述步骤S30，还包括：7. The computer task management method according to claim 6, wherein the step S30 further comprises: 当步骤S20判断由ARM处理器与第二X86处理器交替执行所述新任务时，对所述新任务设置中断点和优先级，分配至第二X86处理器或ARM处理器，以使得所述第二X86处理器和所述ARM处理器根据所述中断点和优先级交替执行所述新任务。When it is determined in step S20 that the new task is executed alternately by the ARM processor and the second X86 processor, a break point and priority are set for the new task, and assigned to the second X86 processor or the ARM processor, so that the new task is The second X86 processor and the ARM processor alternately execute the new task according to the breakpoint and priority. 8.根据权利要求7所述的计算机任务管理方法，其特征在于，在所述第二X86处理器和所述ARM处理器交替执行所述第一X86处理器分配的任务过程中，8. The computer task management method according to claim 7, characterized in that, in the process of alternately executing the tasks assigned by the first X86 processor by the second X86 processor and the ARM processor, 当所述第二X86处理器接收到所述ARM处理器发送的获取处理任务所需的第二X86处理器的相关处理结果的请求时，该请求携带有任务优先级标记，所述第二X86处理器比较所述ARM处理器正在中断的任务的优先级以及所述第二X86处理器正在处理的任务的优先级，所述第二X86处理器根据优先级比较结果优先处理ARM处理器发送的获取处理任务所需的第二X86处理器的相关处理结果的请求或所述第二X86处理器正在处理的任务；When the second X86 processor receives a request sent by the ARM processor to obtain the relevant processing results of the second X86 processor required for processing tasks, the request carries a task priority flag, and the second X86 processor The processor compares the priority of the task being interrupted by the ARM processor and the priority of the task being processed by the second X86 processor, and the second X86 processor preferentially processes the tasks sent by the ARM processor according to the priority comparison result. A request for obtaining the relevant processing result of the second X86 processor required to process the task or the task being processed by the second X86 processor; 当所述ARM处理器接收到所述第二X86处理器发送的获取处理任务所需的ARM处理器的相关处理结果的请求时，该请求携带有任务优先级标记，所述ARM处理器比较所述第二X86处理器正在中断的任务的优先级以及所述ARM处理器正在处理的任务的优先级，所述ARM处理器根据优先级比较结果优先处理第二X86处理器发送的获取处理任务所需的ARM处理器的相关处理结果的请求或所述ARM处理器正在处理的任务。When the ARM processor receives a request sent by the second X86 processor to obtain the relevant processing results of the ARM processor required for processing tasks, the request carries a task priority flag, and the ARM processor compares all The priority of the task being interrupted by the second X86 processor and the priority of the task being processed by the ARM processor, and the ARM processor preferentially processes the acquisition and processing tasks sent by the second X86 processor according to the priority comparison result. A request for the relevant processing result of the required ARM processor or a task being processed by the ARM processor. 9.根据权利要求8所述的计算机任务管理方法，其特征在于，所述第二X86处理器根据优先级比较结果优先处理ARM处理器发送的获取处理任务所需的第二X86处理器的相关处理结果的请求或所述第二X86处理器正在处理的任务，包括：9. The computer task management method according to claim 8, wherein the second X86 processor preferentially processes the correlation of the second X86 processor required for the acquisition processing task sent by the ARM processor according to the priority comparison result Processing the result of the request or task being processed by the second x86 processor, including: 当所述ARM处理器正在中断的任务的优先级较高时，优先处理ARM处理器发送的获取处理任务所需的第二X86处理器的相关处理结果的请求，根据所述ARM处理器的请求处理相关任务，并将处理结果反馈给所述ARM处理器，然后再继续所述第二X86处理器正在处理的任务；When the priority of the task being interrupted by the ARM processor is higher, the request sent by the ARM processor to obtain the relevant processing result of the second X86 processor required for processing the task is preferentially processed, according to the request of the ARM processor Process related tasks, and feed back the processing results to the ARM processor, and then continue the tasks being processed by the second X86 processor; 所述ARM处理器根据优先级比较结果优先处理第二X86处理器发送的获取处理任务所需的ARM处理器的相关处理结果的请求或所述ARM处理器正在处理的任务，包括：The ARM processor preferentially processes the request sent by the second X86 processor to obtain the relevant processing result of the ARM processor required for the processing task or the task being processed by the ARM processor according to the priority comparison result, including: 当所述第二X86处理器正在中断的任务的优先级较高时，优先处理第二X86处理器发送的获取处理任务所需的ARM处理器的相关处理结果的请求，根据所述第二X86处理器的请求处理相关任务，并将处理结果反馈给所述第二X86处理器，然后再继续所述ARM处理器正在处理的任务。When the priority of the task being interrupted by the second X86 processor is higher, preferentially process the request sent by the second X86 processor to obtain the relevant processing result of the ARM processor required for processing the task, according to the second X86 processor The processor's request processes related tasks, and feeds back the processing results to the second X86 processor, and then continues the tasks being processed by the ARM processor. 10.一种计算机设备，其特征在于，包括第一X86处理器、第二X86处理器和ARM处理器，用于实现权利要求1～9中任一项所述的计算机任务管理方法。10. A computer device, comprising a first X86 processor, a second X86 processor and an ARM processor, for implementing the computer task management method according to any one of claims 1 to 9.
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