CN113612566A - Satellite-borne infrared camera external synchronous response method and system - Google Patents
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- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/18578—Satellite systems for providing broadband data service to individual earth stations
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Abstract
The invention relates to an external synchronous response method and system of a satellite-borne infrared camera, which can ensure that the infrared camera cannot lose frames in the whole external synchronous trigger signal switching process and ensure the continuity of ground images scanned by a satellite. The method mainly comprises the steps of acquiring an external synchronization trigger signal in real time, converting the external synchronization trigger signal into an internal synchronization signal, judging the effectiveness of the internal synchronization signal and executing a current frame period; the system mainly comprises an FPGA programmable logic controller, an external synchronous input unit, a frame effective trigger driving unit, a power supply and distribution unit, a clock unit and a storage unit; the invention provides an effective signal synchronization method for satellite-borne hyperspectral imaging, remote sensing imaging and the like, and meanwhile, the method can also be applied to the field of airborne or some special industrial cameras.
Description
Technical Field
The invention relates to a synchronous response method and system outside a satellite-borne infrared camera.
Background
With the development of the space remote sensing technology, the satellite remote sensing increasingly shows the development trend of high time resolution, high space resolution and high spectral resolution, and the remote sensing load data types are more and more diversified. The remote sensing load is gradually expanded from a visible light wave band to the fields of ultraviolet, short wave infrared, medium and long wave infrared, very long wave infrared and the like.
An infrared imaging system is a system that can detect infrared radiation of a target and convert the infrared radiation of the target into an image by means of photoelectric conversion, signal processing, and the like. The infrared detector is the core of the imaging system, and fundamentally determines the development level of the infrared system, and the driving time sequence required by the work of the infrared detector, the output analog signal and the like all need to be processed by a proper signal processing circuit.
When the infrared imaging system is applied to a satellite load, because the distance between the satellite and the earth is inconsistent in a revisit period (non-sun synchronous orbit), and the orbit of the satellite is often elliptical, in one period of the satellite, if the load needs to be started to work, the speed-height ratio needs to be calculated in real time according to the distance between the satellite and the ground, and the load control system can adjust the working frame frequency of the infrared imaging system in real time according to the speed-height ratio, namely adjust the external synchronous trigger signal in real time.
Disclosure of Invention
The invention aims to provide an external synchronous response method and system of a satellite-borne infrared camera, which can ensure that the infrared camera cannot lose frames in the whole external synchronous trigger signal switching process and ensure the continuity of ground images swept by a satellite. An effective signal synchronization method is provided for satellite-borne hyperspectral imaging, remote sensing imaging and the like, and the method can be applied to the field of airborne or some special industrial cameras.
The technical scheme of the invention is as follows:
a satellite-borne infrared camera external synchronous response method is characterized by comprising the following steps:
step 1, acquiring an external synchronization trigger signal in real time;
the satellite-borne infrared camera equipment receives an external synchronization trigger signal sent by a load control system in real time, converts the external synchronization trigger signal into a data format received by the FPGA programmable logic controller and inputs the data format into the FPGA programmable logic controller;
step 2, converting the external synchronization trigger signal into an internal synchronization signal;
the FPGA programmable logic controller converts the external synchronous trigger signal into a synchronous signal under an internal clock domain through an internal trigger, namely, an internal synchronous signal is obtained;
step 3, judging the validity of the internal synchronizing signal;
step 3.1, measuring a pulse interval period D of the synchronous signal in two continuous times through a first logic counter in the FPGA programmable logic controller;
step 3.2, comparing the pulse interval period D measured by the first logic counter with the frame period range set by the satellite-borne infrared camera equipment:
if the pulse interval period D is located outside the frame period range of the satellite-borne infrared camera equipment, judging that the current pulse interval period D is invalid, namely the current internal synchronizing signal is invalid, and executing a default frame period of the satellite-borne infrared camera equipment; the default frame period is a fixed value set by the satellite-borne infrared camera equipment; the pulse interval period D is located outside the frame period range of the satellite-borne infrared camera device, and includes two conditions, namely that D is larger than the maximum value of the frame period set by the satellite-borne infrared camera device and means that the acquired internal synchronization signal is too slow (abnormal), and D is smaller than the minimum value of the frame period set by the satellite-borne infrared camera device and means that the acquired internal synchronization signal is too block (abnormal).
If the pulse interval period D value is within the range of the design frame period of the satellite-borne infrared camera equipment, judging that the current pulse interval period D is valid, namely the current internal synchronizing signal is valid, taking the current pulse interval period D as the current frame period, finishing the measurement of the current frame period, and executing the step 4;
step 4, executing the current frame period;
step 4.1, executing the current frame period;
step 4.2, judging whether the execution of the current frame period is finished, if so, entering step 4.3, otherwise, entering step 4.4;
4.3, refreshing the count value of the current frame period to be equal to 0, judging whether the next frame period is measured or not, if so, executing the next frame period, otherwise, waiting for the measurement of the next frame period to be finished, and executing the next frame period;
and 4.4, adding 1 to the current frame period count value, updating the previous frame period count value, and returning to the step 4.1.
Further, the process of determining whether the execution of the current frame period is completed in step 4.2 specifically includes:
measuring a current frame period count value by using a second logic counter in the FPGA programmable logic controller;
if the counting value of the current frame period measured by the second logic counter is equal to the pulse interval period D of the synchronous signal in two continuous times measured by the first logic counter or the default frame period of the satellite-borne camera equipment, the current frame period is considered to be completed;
and if the current frame period counting value measured by the second logic counter is smaller than the pulse interval period D of the synchronous signal in two continuous times measured by the first logic counter or the default frame period of the satellite-borne camera equipment, determining that the current frame period is not executed completely.
Further, in the step 1, the satellite-borne infrared camera device converts the differential external synchronous trigger signal into a single end by using an RS485 receiving chip, and inputs the single end to the FPGA programmable logic controller.
The invention also provides an external synchronous response system of the satellite-borne infrared camera equipment, which is characterized in that: the system comprises an FPGA programmable logic controller, an external synchronous input unit, a frame effective trigger driving unit, a power supply and distribution unit, a clock unit and a storage unit;
the FPGA programmable logic controller comprises an external synchronous receiving circuit, a first logic counter and a second logic counter;
the external synchronous input unit, the frame effective trigger driving unit, the clock unit and the storage unit are all connected with the FPGA programmable logic controller;
the external synchronization input unit is used for receiving an external synchronization trigger signal sent by the load control system in real time, converting the external synchronization trigger signal into a data format received by the FPGA programmable logic controller and inputting the data format into the FPGA programmable logic controller;
the FPGA programmable logic controller is used for converting the external synchronous trigger signal into a synchronous signal under an internal clock domain; the detection and interpretation of the internal synchronization signal are realized, and a frame trigger signal is generated according to the detection and interpretation result and is sent to a frame effective trigger driving unit;
the frame effective trigger driving unit is used for converting a frame trigger signal sent by the FPGA programmable logic controller into a driving signal under the level required by a detector in the satellite-borne infrared camera equipment;
the clock unit is used for providing a clock for the FPGA programmable logic controller;
the storage unit is used for providing program loading for the FPGA programmable logic controller and ensuring that the FPGA programmable logic controller can normally run an internal logic program after power failure and restart;
the power supply and distribution unit is used for supplying power to the whole system.
Further, the frame active trigger driving unit is driven by LMH 6628.
Further, the FPGA programmable logic controller adopts Xilinx V2 series XC2V 3000.
Further, the external synchronization input unit adopts a MAX485 chip.
The invention has the beneficial effects that:
1. according to the external synchronous response method of the satellite-borne camera equipment, each external synchronous signal is judged, and the next frame of triggering is immediately started when the previous frame is finished, so that the system can be ensured not to omit any external synchronous triggering signal once, the continuity of remote sensing imaging is ensured, and the ground object interruption and other conditions can not be caused in the ground push-broom image; meanwhile, the relative height and speed change of the satellite and the ground can be responded in time, so that the load-to-ground resolution is relatively consistent;
2. the external synchronization response method provided by the invention can also be popularized and applied to other environments requiring constantly changing frame frequency, such as airborne equipment and other special application requirements which cannot have data omission.
3. The invention does not need to help extra hardware cost, has good economy and practicability and wide and universal applicability.
Drawings
FIG. 1 is a block diagram of an external synchronous response system of a satellite-borne camera device according to the present invention;
FIG. 2 is a diagram illustrating an external synchronization response for switching from a high frame frequency to a low frame frequency;
fig. 3 is a diagram illustrating an external synchronization response when switching from a low frame rate to a high frame rate.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below, and it is apparent that the described embodiments are a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Furthermore, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Furthermore, the terms "first or second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The external synchronization response method provided by the invention can also be popularized and applied to other environments requiring constantly changing frame frequency, such as airborne equipment and other special application requirements which cannot have data omission. The following examples illustrate a satellite-borne infrared camera:
the embodiment is mainly designed for an external synchronization trigger signal response method of a satellite-borne infrared camera based on an FPGA, and provides an external synchronization response system shown in fig. 1, which comprises an FPGA programmable logic controller, an external synchronization input unit, a frame effective trigger driving unit, a power supply and distribution unit, a clock unit, a storage unit and the like.
(1) FPGA programmable logic controller
The FPGA unit is a key link for realizing an internal logic unit and specifically implementing the design flow of the invention. Specifically, in a practical application case of the invention, Xilinx company V2 series XC2V3000 is selected, which comprises an external synchronous receiving circuit, a first logic counter and a second logic counter; the external synchronization trigger signal is converted into a synchronization signal in an internal clock domain; and the detection and interpretation of the internal synchronizing signal are realized, and a frame trigger signal is generated according to the detection and interpretation result and is sent to the frame effective trigger driving unit.
(2) External synchronous input unit
The external synchronization input unit adopts an MAX485 chip and is used for receiving a differential external synchronization trigger signal sent by the real-time receiving load control system, converting the differential external synchronization trigger signal into a single-ended signal and inputting the single-ended signal into the FPGA programmable logic controller after voltage regulation.
(3) Frame active trigger driving unit
The frame effective trigger driving unit is used for converting a frame trigger signal sent by the FPGA programmable logic controller into a driving signal under the level required by a detector in the satellite-borne infrared camera equipment.
(4) Power supply and distribution unit
The power supply and distribution unit is used for providing power distribution for the whole circuit design and mainly comprises a plurality of power supply conversion chips. Specifically, the LDO power supply is adopted, and the LDO power supply has the characteristics of high performance and low noise, and is favorable for ensuring the reliability of data transmission.
(5) Clock unit
The clock unit is used for providing a clock for the FPGA programmable logic controller.
(6) Memory cell
The storage unit is used for providing program loading for the FPGA programmable logic controller and ensuring that the FPGA programmable logic controller can normally run internal logic programs after power failure and restart.
The specific flow of the external synchronous response method of the satellite-borne camera equipment is as follows:
firstly, connecting an external synchronous receiving circuit based on an FPGA with an external synchronous trigger source; a physical interconnection is established.
And step two, the FPGA programmable logic controller operates a starting frame to execute, and simultaneously resets a relevant counter, a register and the like, namely, performs zero returning operation, so that all relevant signal processing is in a uniform zero state:
step three, starting an external synchronization source to enable the external synchronization source to be in a state of continuously sending an external synchronization trigger signal; starting the working hardware environment of the invention to make it in a receiving state;
there are many methods for acquiring the external synchronization trigger signal, and for this embodiment, MAX485 differential reception is adopted; the infrared camera upper computer system sends an external synchronous trigger signal through a 485 interface, and the infrared camera converts a differential signal into a single end through a 485 receiving chip and inputs the single end into the FPGA programmable logic control device.
Fourthly, the FPGA programmable logic control device triggers the external synchronous trigger signal S in real time through an internal logic gate and a clock0Conversion to synchronisation signals in the internal clock domain, i.e. to internal synchronisation signals S1. The embodiment can realize the function through the internal trigger of the FPGA programmable logic control device.
Step five, judging the internal synchronizing signal S1The effectiveness of (a);
measuring S twice continuously through first logic counter in FPGA programmable logic control device1By measuring S twice1The pulse edge of (2) is realized; two times of examination S1If the pulse interval period is within the frame period range set by the infrared camera, D is judged to be valid, namely the internal synchronizing signal S1And if not, determining the result as invalid.
In this embodiment, it is assumed that the maximum value of the frame frequency required by the infrared camera corresponds to the count C in the time domain of the FPGA programmable logic control deviceminThe minimum value of the frame frequency required by the infrared camera corresponds to the count C of the FPGA programmable logic control device in the time domainmaxThe infrared camera requires that the default frame frequency corresponds to the FPGA programmable logic control device, the time domain down count is Cdef。
When D > CmaxIn time, it means that the acquired frame synchronization signal is too slow (abnormal), it is determined that the current intra-synchronization is invalid, and the infrared camera executes a default frame frequency, i.e., executes CdefA frame period of (a);
when D is less than CminIn time, it means that the acquired frame synchronization signal is too fast (abnormal), it is determined that the current intra-synchronization is invalid, and the infrared camera performs a default frame frequency, i.e., performs CdefA frame period of (a);
when Cmin is not more than D and not more than Cmax, judging that the current internal synchronization is effective, taking the current pulse interval period D as the current frame period, finishing the measurement of the current frame period, and executing the step six;
step six, the infrared camera executes the current frame period;
measuring a current frame period count value by using a second logic counter in the FPGA programmable logic control device; by comparing the current frame period count with D or CdefJudging whether the execution of the current frame period is finished or not;
if the current frame period count value C measured by the second logic counter is C and D or CdefIf the current frame period is equal to the current frame period, the current frame period is considered to be completed; entering a seventh step;
if the current frame period count value C measured by the second logic counter is less than D or CdefIf the current frame period is not executed, entering step eight;
step seven, refreshing the count value of the current frame period to be equal to 0, judging whether the next frame period is measured or not, if so, executing the next frame period, otherwise, waiting for the measurement of the next frame period to be finished, and executing the next frame period;
if the current frame period is executed, the next frame period is not measured yet, which means that the frame frequency of the camera is adjusted from large to small; as shown in fig. 2, at this time, the infrared camera needs to wait for the new frame period measurement to end;
if the measurement of the next frame period is finished, the current frame period is not finished, which means that the frame frequency of the camera is adjusted from small to large; as shown in fig. 3, this may cause the fixed phase relationship between the frame execution start point of the infrared camera and the external synchronization trigger signal to be broken; but this is an inevitable situation where the infrared camera can not miss any one time of the requirement of the external synchronization trigger signal.
And step eight, adding 1 to the current frame period count value, updating the previous frame period count value, and returning to the step six.
The complete imaging of the infrared camera in one orbit during the in-orbit operation process of the satellite can be completed through the steps, and the frame frequency is adjusted in real time according to the terrain and the orbit height, so that the ground resolution of the system is kept unchanged.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115297222A (en) * | 2022-07-26 | 2022-11-04 | 贵州航天电子科技有限公司 | Multi-camera synchronization system for bionic compound eye and control method thereof |
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