CN113608769A - Method based on parallel processing and self-upgrading of multiple single-chip microcomputers - Google Patents
Method based on parallel processing and self-upgrading of multiple single-chip microcomputers Download PDFInfo
- Publication number
- CN113608769A CN113608769A CN202110939186.7A CN202110939186A CN113608769A CN 113608769 A CN113608769 A CN 113608769A CN 202110939186 A CN202110939186 A CN 202110939186A CN 113608769 A CN113608769 A CN 113608769A
- Authority
- CN
- China
- Prior art keywords
- upgrading
- processor
- program
- slave
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Stored Programmes (AREA)
Abstract
The invention provides a method for parallel processing and self-upgrading based on multiple single-chip microcomputers, which comprises the steps that after a self-checking flow program is confirmed to enter, a main processor sends an inquiry instruction to each slave processor, the state of a program written in each slave processor is sequentially inquired, whether the current state of a system meets an upgrading standard or not is judged according to related data replied by the slave processors, if the judgment result is yes, the main processor enters a write-in upgrading flow, the upgrading program is sequentially written in each slave processor through a data serial port bus, after the upgrading program is confirmed to be successfully written in all the slave processors, the main processor enters a self-upgrading flow, after the upgrading program is written in the main processor, the slave processors perform detection, and the whole upgrading flow can be completed after the upgrading program is confirmed to be wrongly written in. The invention can improve the stability of the software upgrading process of the modular numerical control system, has high success rate of writing the system chip program and reduces the complicated maintenance operation in the upgrading process of the system user.
Description
Technical Field
The invention relates to the technical field of industrial control, in particular to a method based on parallel processing and self-upgrading of multiple single-chip microcomputers.
Background
With the development of scientific information technology, the remote monitoring of the internet of things is gradually and widely applied to various fields, the working state of field equipment can be monitored at any time and any place through the technology of the internet of things, the field check is not needed, and the remote monitoring of the internet of things is gradually and widely applied as a convenient and quick communication mode. Meanwhile, due to the development and updating of the technology, an unattended modern monitoring mode is gradually favored by customers, but the systems need to be upgraded and maintained regularly, but the field upgrading can consume time and manpower, particularly, the construction is difficult due to high working strength and difficulty, and the problem is well solved by remote automatic upgrading.
Currently, with the development of microcomputer technology and diversification of application functions, a single MCU (Micro Control Unit) cannot meet the requirements of functions or performance, and most products adopt a master-slave MCU (which may include several slaves, and then the slaves Control the multi-stage connection of several slaves) to achieve higher performance and requirements.
However, when the upgrading of the program of the slave controller is required, the prior art cannot meet the upgrading requirement, and the development of products is restricted. Particularly, no digital control system with flexibly configurable upgrading functions exists in the field of industrial control, and no design scheme capable of optimizing and guaranteeing the upgrading process of writing software into a system chip is found.
Disclosure of Invention
The invention mainly aims to provide a method for parallel processing and self-upgrading based on multiple single-chip microcomputers, which can improve the stability of the software upgrading process of a modular numerical control system, can not cause the downtime of equipment due to unexpected faults such as power failure and the like, and can ensure that the writing of system chip programs basically reaches 99.99 percent of success rate in principle, thereby reducing the complicated maintenance operation in the upgrading process of system users.
In order to achieve the main purpose, the invention provides a method for parallel processing and self-upgrading based on multiple single-chip microcomputers, which comprises the steps that after a self-checking flow program is determined to enter, a main processor sends query instructions to each slave processor, the state of a program written in each slave processor is sequentially queried, and whether the current state of a system meets an upgrading standard or not is judged according to related data replied by the slave processors; if the judgment result is yes, the main processor enters a write-in upgrading process and sequentially writes upgrading programs into the slave processors through the data serial port bus; after all the slave processors are confirmed to write the upgrading programs successfully, the master processor enters a self-upgrading process, detection is carried out by the slave processors after the master processor finishes writing the upgrading programs, and the whole upgrading process can be finished after the upgrading programs are confirmed to be written without errors; if faults occur in the upgrading process, the slave processor program is wrong, the upgrading can be simply carried out again, if the master processor fails, the master processor cannot be correctly guided to enter the upgrading process, a manual forced upgrading mode is adopted, the master processor is subjected to forced upgrading process, and then the normal upgrading process is recovered.
In a further scheme, when a self-checking flow program is entered, a main processor sends a query instruction through a communication data interface under the guidance of the program, the state of a program written in each slave processor is sequentially queried, the slave processors can reply corresponding parameter values within a specified time after receiving the query instruction sent by the main processor, and information such as the integrity, the writing time and the version of the program in the current processor is reported; wherein, judging whether the current system state meets the upgrading standard comprises: and judging the current state of the system to determine whether the system enters an automatic upgrading process or normally enters the system.
In a further scheme, if the system enters an automatic upgrading process, reading data transmitted by an external data unit through a data communication interface, and temporarily storing the data in a main processor RAM/FLASH ROM region after verifying the read data; after the external data is read, the main processor enters a downward writing upgrading process, and a mode of reading the upgrading data and upgrading the auxiliary processor simultaneously can be adopted in the processor of the small-capacity ROM/RAM; after the main processor enters a downward write-in upgrading process, the main processor outputs a pin signal to reset a slave processor, the slave processor enters a write-in process of an upgrading program, and the upgrading program is written into the slave processor through a data serial port bus; after the upgrading program of the slave processor is written, a confirmed flag bit is replied through a data serial port bus according to the program requirement, and after the master processor receives the confirmed flag bit, the slave processor can be confirmed to be upgraded successfully, and the next slave processor is entered into the upgrading and writing process; if the main processor does not receive the confirmed flag bit, the upgrading program is determined to be failed to be written, and the main processor writes the upgrading program into the auxiliary processor again.
In a further scheme, after the first slave processor successfully writes the upgrading program, the master processor sequentially writes the upgrading program for the subsequent slave processors, and after the last slave processor successfully upgrades, the master processor jumps to a corresponding boot area to enter a self-upgrading flow; under the self-upgrading process, the main processor firstly carries out erasing and writing work of the program area, and carries out the program erasing and writing process in the boot area after ensuring that the program area is written correctly.
In a further aspect, the self-upgrade process specifically includes: after entering the self-upgrading process, the main processor sets an upgrading identifier, the existence of the identifier indicates that upgrading is necessary, self-upgrading program data of a data communication interface is obtained according to program requirements in a boot area and divided into two areas of the boot area and the program, the boot area is upgraded firstly, the data in the boot area is temporarily stored in the program area, the boot area is upgraded through a specific program preset in the program, after the boot area is upgraded, the processor returns to a new boot area, then the upgrading data in the program area is obtained, the program area is upgraded, and finally the upgrading identifier is removed after verification is completed, so that the upgrading process of the whole system is completed.
In a further scheme, all the upgrading data can be decrypted in a plurality of encryption modes and verified, and the consistency and the confidentiality requirements of the data can be ensured by decrypting the upgrading data in the processor;
if the main processor makes a mistake in the process of writing into the program area when self-upgrading is carried out, the system can automatically send an alarm and needs to manually reset the whole system, when the system is electrified again, a boot area program in the main processor checks the integrity of the program area according to requirements, and after the program writing failure is confirmed, the self-upgrading process is entered again, the content of the upgrading program is read from the data communication interface, and erasing and writing are carried out again in the program area.
In a further scheme, if an error occurs in the process of writing the original boot area of the upgrading slave processor, the upgrading slave processor enters an abnormal mode, executes a manual forced upgrading process and executes upgrading for the master processor again.
In a further scheme, after determining that the writing of the main processor fails and the main processor cannot be automatically recovered, entering a manual forced upgrade flow: the equipment is powered off firstly, the equipment reset key is pressed, meanwhile, in order to ensure that the forced state is accurate, the external key is pressed simultaneously, the system is powered on again, the system is kept for 3-5 seconds, at the moment, the main processor is in the reset state, the main processor reset pin and the auxiliary processor start pin are triggered simultaneously, the auxiliary processor judges that the main processor is forced to reset and enters the takeover, and therefore the manual forced upgrading process is started.
In a further scheme, the slave processor obtains an upgrading program of the master processor through a communication data interface shared by the slave processor and the master processor, executes a mode similar to the upgrading of the slave processor by the master processor, carries out forced upgrading on the master processor, takes over necessary hardware resources of the original master processor by the slave processor at the moment, and carries out human-computer interaction processing through the slave processor.
Therefore, the invention adopts the sequential upgrading scheme of the multiple processors to implement the upgrading process, and the main stream processor in the multiple processors is responsible for allocating upgrading resources and upgrading other slave processors sequentially, thereby realizing the capability of upgrading corresponding software according to hardware functions and ensuring the stability of the software upgrading process.
If the program of the slave processor of the system is erased, written and upgraded and interrupted by accidents in the process of upgrading, the master processor records an upgrade log, when a user upgrades the system again, the system is continuously upgraded from a breakpoint, only when all the slave processors are upgraded, the master processor can perform self-upgrade, and if errors occur accidentally in the process of upgrading the master processor, the slave processor which finishes upgrading can reversely take over the task of upgrading resource allocation to control the process of upgrading the master processor again. Therefore, under the design of taking over the upgrading task scheme, the condition of 'changing bricks' caused by the failure of the system upgrading process can be avoided.
Therefore, the method provided by the invention can effectively reduce the probability of system paralysis caused by the write failure of the chip under the conditions of unexpected power failure, circuit interference and the like in the upgrading process, greatly improves the convenience of maintaining the modular numerical control system and reduces the maintenance cost.
In addition, because the invention adopts the parallel working design of the multiprocessor, the capability of upgrading the corresponding software according to the hardware function can be realized, all the MCUs to be upgraded can be automatically upgraded only by providing the upgrading file for the main processor, and each MCU does not need to be upgraded independently, thereby saving the working time of operators and reducing the time cost of upgrading.
Drawings
Fig. 1 is a flowchart of an embodiment of a method for parallel processing and self-upgrading based on multiple singlechips.
Fig. 2 is a schematic circuit diagram of an embodiment of a method for parallel processing and self-upgrading based on multiple singlechips.
The invention is further explained with reference to the drawings and the embodiments.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It should be noted that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work are within the scope of the present invention.
Referring to fig. 1 and 2, the method for parallel processing and self-upgrading based on multiple single-chip microcomputers of the invention comprises the following steps:
firstly, step S1 is executed to enter the self-test flow program, and after the self-test flow program is determined to enter, step S2 is executed to enable the master processor to send an inquiry command to each slave processor, sequentially inquire the state of the program written in each slave processor, and execute step S3 according to the related data replied by the slave processors to determine whether the current state of the system meets the upgrade standard.
If the judgment result is yes, step S4 is executed, the master processor enters a write-in upgrade process, and sequentially writes upgrade programs into the slave processors through the data serial bus.
When it is confirmed that all the slave processors write the upgrade programs successfully, step S5 is executed, the master processor enters the self-upgrade process, the slave processors perform detection after the master processor writes the upgrade programs, and the whole upgrade process can be completed after the slave processors determine that the upgrade programs are written without errors.
If faults occur in the upgrading process, the slave processor program is wrong, the upgrading can be simply carried out again, if the master processor fails, the master processor cannot be correctly guided to enter the upgrading process, a manual forced upgrading mode is adopted, the master processor is subjected to forced upgrading process, and then the normal upgrading process is recovered. Therefore, the design mode can ensure that the processor is upgraded by 99.99 percent successfully.
Before step S1 is executed, after the system is powered on, the main processor enters the corresponding boot area according to the physical setting to find the beginning segment part of the program, sets the related jump address in the part, and the boot program enters the self-checking flow program, so as to check whether the running program check code of each slave processor program area is complete, and execute the next step according to the judgment result.
In this embodiment, after entering the self-test flow program, the master processor sends an inquiry command through the communication data interface (USB, SPI, serial port, CAN, I2C, bluetooth, network, etc.) under the guidance of the program, and sequentially inquires the state of the program written in each slave processor, and after receiving the inquiry command sent by the master processor, the slave processor replies a corresponding parameter value within a specified time, and reports information such as the integrity, writing time, version, etc. of the program in the current processor.
In the step S3, the step of determining whether the current system state meets the upgrade criterion includes: and judging the current state of the system to determine whether the system enters an automatic upgrading process, a manual forced upgrading process or normally enters the system.
In this embodiment, the execution of the manually forced upgrade flow includes: through two input signal switches, a main processor reset pin and a slave processor start pin are triggered at the same time, the slave processor judges that the main processor is forcibly reset and takes over, and therefore a manual forced upgrading process is started.
In the step S3, if the system enters the automatic upgrade process, the main processor queries the boot program at the corresponding address, starts to read the data transmitted from the external data unit through the data communication interface (USB, SPI, serial port, CAN, I2C, bluetooth, network, etc.), and temporarily stores the data in the RAM/FLASH ROM area of the main processor after verifying the read data; after the external data is read, the main processor enters a downward writing upgrading process, and a mode of reading the upgrading data and upgrading the slave processor simultaneously can be adopted in the processor of the small-capacity ROM/RAM (the data can also be read and the slave processor can be upgraded simultaneously), which is particularly important for the processor of the small-capacity ROM/RAM: after the main processor enters a downward write-in upgrading process, the main processor outputs a pin signal to reset a slave processor, the slave processor enters a write-in process of an upgrading program, and the upgrading program is written into the slave processor through a data serial port bus; after the upgrading program of the slave processor is written, a confirmed flag bit is replied through a data serial port bus according to the program requirement, and after the master processor receives the confirmed flag bit, the slave processor can be confirmed to be upgraded successfully, and the next slave processor is entered into the upgrading and writing process; if the main processor does not receive the confirmed flag bit, the upgrading program is determined to be failed to be written, and the main processor writes the upgrading program into the auxiliary processor again.
After the master processor enters a downward writing upgrading process, a corresponding upgrading object is selected according to a chip selection signal, a slave processor is selected through a pull-up pin P62, a pin P54 of the slave processor is pulled down, the writing process of the slave processor upgrading program is carried out, and the upgrading program is written into the slave processor through a data communication interface.
After the upgrading program of the slave processor is written, a confirmed flag bit is replied through a data serial port bus according to the program requirement, and after the master processor receives the confirmed flag bit, the slave processor can be confirmed to be upgraded successfully, and the next slave processor is entered into the upgrading and writing process; if the main processor does not receive the confirmed flag bit, the upgrading program is determined to be failed to be written, and the main processor writes the upgrading program into the auxiliary processor again.
In this embodiment, after the first slave processor successfully writes the upgrade program, the master processor writes the upgrade program for the subsequent slave processors in sequence, and after the last slave processor successfully upgrades, the master processor jumps to the corresponding boot area to enter a self-upgrade flow; under the self-upgrading process, the main processor firstly carries out erasing and writing work of the program area, and carries out the program erasing and writing process in the boot area after ensuring that the program area is written correctly.
Wherein, the self-upgrading process specifically comprises: after entering the self-upgrading process, the main processor sets an upgrading identifier, the existence of the identifier indicates that upgrading is necessary, self-upgrading program data of a data communication interface is obtained according to program requirements in a boot area and divided into two areas of the boot area and the program area, the boot area is upgraded firstly, the data in the boot area is temporarily stored in the program area, the boot area is upgraded through a specific program preset in the program area, after the boot area is upgraded, the processor returns to a new boot area, then the upgrading data in the program area is obtained, the program area is upgraded, and finally the upgrading identifier is removed after verification is completed, so that the upgrading process of the whole system is completed.
Specifically, after entering the self-upgrade process, the main processor erases the chip memory program storage area according to the program requirement in the boot area, reads the SPI serial port of the pins P13-P16 to obtain the self-upgrade program, and writes the partial program into the chip memory area again, wherein the tail of the upgrade program has the same check bit, the boot program in the boot area after the completion of writing verifies the correctness of the write program, and the boot program enters the upgrade process of the boot program after the correctness is determined.
After the main processor confirms that the program area is upgraded, automatically jumping to a process of reading the content of the program area, switching to erasing from the spare boot program at the tail part of the upgraded program in the program area, writing the spare boot program into the original boot area, and starting to upgrade the boot area program of the main processor; after the upgrade write-in of the main processor boot area is completed, jumping to the end of the related flow to complete the upgrade process of the whole system.
In this embodiment, if the main processor performs self-upgrade, and an error occurs in the process of writing into the program area, the system will automatically issue an alarm and needs to manually reset the entire system, when the system is powered on again, the boot area program in the main processor checks the integrity of the program area as required, and when the program write failure is confirmed, the system enters the self-upgrade flow again, reads the content of the upgrade program from the data communication interface, and erases and writes the program area again.
Furthermore, if the upgrading slave processor makes an error in the process of writing the original boot area of the upgrading slave processor, the upgrading slave processor enters an abnormal mode, executes a manual forced upgrading process and executes upgrading for the master processor again.
Further, when it is determined that the writing of the main processor fails and the main processor cannot be automatically recovered, a manual forced upgrade process is performed: the equipment is powered off firstly, an equipment reset key (a main processor reset end) is pressed, meanwhile, in order to ensure that the forced state is accurate, an external key (another input signal is connected) is pressed simultaneously, the system is powered on again, the system is kept for 3-5 seconds, at the moment, the main processor is in the reset state, a main processor reset pin and a slave processor starting pin are triggered simultaneously, the slave processor judges that the main processor is forced to reset, the slave processor enters take-over, and therefore the manual forced upgrading process is achieved. The method comprises the steps that a reset key and an external key are pressed to be electrified, a reset pin of a main processor and a starting pin of a slave processor are pulled down simultaneously, and a manual forced upgrading process is started; the slave processor reads the pin P37 of the slave processor to determine the state of the reset pin of the master processor, reads the state of the start pin of the slave processor after the reset pin of the master processor is determined to be pulled down and reset for a long time, and executes a manual forced upgrading process through a program after the start pin is determined to be pulled down.
Furthermore, the slave processor obtains the upgrading program of the master processor through the communication data interface shared by the master processor, executes a mode similar to the upgrading of the slave processor by the master processor, and carries out forced upgrading on the master processor, at the moment, the slave processor takes over necessary hardware resources (display, keyboard, FlashRom, communication data interface and the like) of the original master processor, and carries out human-computer interaction processing through the slave processor.
In this embodiment, the entering of the manual forced upgrade flow taken over by the slave processor specifically includes: the slave processor selects a corresponding USB interface through a pin P32/P33, reads upgrading program content transmitted from the outside through an SPI bus, and temporarily stores the upgrading program content in a chip RAM; after the temporary storage and verification of the upgrading program are completed, the slave processor executes a cut-off reset process for the master processor through a signal of a pull-up pin P37, and executes a program data write-in process for the master processor through a data serial port bus; when the write-in upgrade of the main processor is finished, the confirmed flag bit of the upgrade end is fed back through the SPI bus and read by the slave processor, when the slave processor confirms that the flag bit data is correct, the slave processor enters the upgrade end process, at the moment, the system is powered on after being powered off, and the upgrade process taken over by the main processor is recovered.
In practical application, after the system is powered on, the main processor firstly enters a corresponding boot storage area according to physical settings to search for a beginning segment part of a program, and sets a related jump address, so that the boot program enters a self-detection flow.
And when the self-checking flow program is entered, the main processor sequentially inquires the state of the program written in each slave processor in a mode of sending an inquiry instruction through serial port connection pins TXD and RXD under the guidance of the program, and after receiving the sent inquiry instruction, the slave processors reply corresponding parameter values within a specified time and report information such as the integrity, the writing time and the version of the program in the current processor.
Then, the main processor determines the current state of the system according to the responded data value to determine whether the system needs to automatically enter the program upgrading process or normally enter the system, and at this time, the main processor reset pin P54 and the slave processor start pin P10 are triggered simultaneously through two external input signal switches, so that the slave processor determines that the main processor is forcibly reset and enters the takeover process, and then enters the manual forced upgrading process.
If the system enters an automatic upgrading process, the main processor firstly queries a bootstrap program under a corresponding address according to program requirements, starts to read data transmitted by an external data unit through an SPI bus of pins P13-P16, and temporarily stores the data in a RAM area of the main processor after the data are read and verified.
After the external data is read, the master processor enters a downward writing upgrading process, because a plurality of slave processors are all communicated on the bus, corresponding upgrading objects need to be selected according to chip selection signals, the slave processor A is selected by pulling up the pin P62, then the slave processor A enters an upgrading program writing process by pulling down the pin P54 of the slave processor A, and the slave processor A is written with the upgrading program through the data serial port buses P46 and P47 connected with the slave processor A.
After the slave processor A finishes writing, a determined flag bit is replied through serial port data according to program requirements, the slave processor A is confirmed to be upgraded successfully only after the master processor receives the flag, the next slave processor is started to enter an upgrading writing process, if the flag is not received, the master processor is considered to be failed in writing the upgrading program, and the master processor is started to upgrade the slave processors again.
According to the flow, the master processor writes the upgrading programs for the subsequent slave processors in sequence until all the slave processors are upgraded.
And when the last slave processor is successfully upgraded, the master processor jumps to the corresponding boot area according to the program flow and enters a self-upgrading flow. Under the process, the main processor firstly sets an upgrade identifier, and the identifier is cancelled only after all upgrades are completed correctly; reading in new guide area upgrading data through a data communication interface, verifying and decrypting the data, temporarily storing the data at a specific position of a main program area, transferring the main processor into a standby guide program inlet in the new guide area, performing data upgrading coverage on the original guide area, and finally, after verifying the correctness of the data in the guide area, enabling the main processor to enter a main program area upgrading process
After entering the main program upgrading process, the main processor firstly erases the ROM data of the main program area, then reads the content of the new main program area through the data communication interface, writes the content into the main program area after decryption, verifies the correctness of the main program area, and finally eliminates the upgrading identification to complete the upgrading process of the whole main processor.
And after the main processor main program is upgraded and written, skipping to finish the related flow to finish the upgrading process of the whole system.
Furthermore, if the main processor is subjected to self-upgrade, and an accident occurs in the process of writing in the program area, which causes writing errors, interruption and the like, the system automatically gives an alarm, at this time, the whole system needs to be reset manually, when the main processor is powered on again, a boot area program in the main processor checks the integrity of the program area according to requirements, after the program writing fails, the self-upgrade flow is entered again, the upgrade program content is read from the SPI serial port of the pins P13-P16, and erasing and writing are performed again in the program area.
If the host processor encounters unexpected interruption in the process of writing the original boot area of the host processor, at this time, because the boot area based on the bottom layer of the chip is damaged, the chip cannot find out the program entry address after being electrified, and enters an abnormal mode, and a manual forced upgrade flow needs to be executed to re-execute upgrade for the host processor.
And when the main processor is determined to fail to write and cannot be automatically recovered, the main processor is powered on by pressing the reset key and the external key, and simultaneously the main processor reset pin P54 and the slave processor starting pin P10 are pulled down to enter a manual forced upgrading mode. The slave processor can read the pin P37 of the slave processor to determine the state of the reset pin of the master processor, read the state of the start pin of the slave processor after the reset pin of the master processor is determined to be pulled down and reset for a long time, and execute a manual forced upgrading process through a program after the pin P36 is also pulled down, take over all functions including reading data and refreshing display.
Then, entering a manual forced upgrade flow taken over by the slave processor, selecting a corresponding USB interface from the slave processor through P32/P33 pins, reading upgrade program contents transmitted from the outside from the SPI bus of corresponding USB module pins P13-P16, and temporarily storing the upgrade program contents in a chip RAM (for a small-capacity CPU, one sector can be read and written).
After the temporary storage and verification of the program are completed, the slave processor performs a cut-off reset process for the master processor by pulling up a signal of the pin P37, and performs a program data write-in process for the master processor independently at the moment by the serial port communication bus of the pins P46 and P47.
When the upgrade program of the main processor is written into the SPI bus, the mark data related to the end of the upgrade is fed back from the SPI bus and read by the slave processor, when the mark data is confirmed to be correct, the slave processor enters the upgrade end process, and at the moment, the system is powered on after being powered off, and then the system is restored to the logic that the main processor takes over all the processes. If the write mark feedback is abnormal, the default upgrading is not successful, and the upgrading process of the main processor is started again.
Therefore, the invention adopts the sequential upgrading scheme of the multiple processors to implement the upgrading process, and the main stream processor in the multiple processors is responsible for allocating upgrading resources and upgrading other slave processors sequentially, thereby realizing the capability of upgrading corresponding software according to hardware functions and ensuring the stability of the software upgrading process.
If the program of the slave processor of the system is erased, written and upgraded and interrupted by accidents in the process of upgrading, the master processor records an upgrade log, when a user upgrades the system again, the system is continuously upgraded from a breakpoint, only when all the slave processors are upgraded, the master processor can perform self-upgrade, and if errors occur accidentally in the process of upgrading the master processor, the slave processor which finishes upgrading can reversely take over the task of upgrading resource allocation to control the process of upgrading the master processor again. Therefore, under the design of taking over the upgrading task scheme, the condition of 'changing bricks' caused by the failure of the system upgrading process can be avoided.
Therefore, the method provided by the invention can effectively reduce the probability of system paralysis caused by the write failure of the chip under the conditions of unexpected power failure, circuit interference and the like in the upgrading process, greatly improves the convenience of maintaining the modular numerical control system and reduces the maintenance cost.
In addition, because the invention adopts the parallel working design of the multiprocessor, the capability of upgrading the corresponding software according to the hardware function can be realized, all the MCUs to be upgraded can be automatically upgraded only by providing the upgrading file for the main processor, and each MCU does not need to be upgraded independently, thereby saving the working time of operators and reducing the time cost of upgrading.
It should be noted that reference throughout this specification to "one embodiment," "another embodiment," "an embodiment," "a preferred embodiment," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment described generally in this application. The appearances of the same phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments. Although the invention has been described herein with reference to a number of illustrative examples thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope and spirit of the principles of this disclosure. More specifically, other uses will be apparent to those skilled in the art in view of variations and modifications in the subject matter incorporating the components and/or arrangement of the arrangement within the scope of the disclosure, drawings and claims hereof.
Claims (9)
1. A method based on parallel processing and self-upgrading of multiple single-chip microcomputers is characterized by comprising the following steps:
after the self-checking flow program is determined to enter, the main processor sends a query instruction to each slave processor, sequentially queries the program writing state in each slave processor, and judges whether the current state of the system meets the upgrading standard or not according to related data replied by the slave processors;
if the judgment result is yes, the main processor enters a write-in upgrading process and sequentially writes upgrading programs into the slave processors through the data communication interface;
after all the slave processors are confirmed to write the upgrading programs successfully, the master processor enters a self-upgrading process, detection is carried out by the slave processors after the master processor finishes writing the upgrading programs, and the whole upgrading process can be finished after the upgrading programs are confirmed to be written without errors;
if faults occur in the upgrading process, the slave processor program is wrong, the upgrading can be simply carried out again, if the master processor fails, the master processor cannot be correctly guided to enter the upgrading process, a manual forced upgrading mode is adopted, the master processor is subjected to forced upgrading process, and then the normal upgrading process is recovered.
2. The method of claim 1, wherein:
when entering a self-checking flow program, the main processor sends a query instruction through the data communication interface under the guidance of the program, sequentially queries the state of a program written in each slave processor, and after receiving the query instruction sent by the main processor, the slave processors reply corresponding parameter values within a specified time and report information such as the integrity, the writing time and the version of the program in the current processor;
wherein, judging whether the current system state meets the upgrading standard comprises: and judging the current state of the system to determine whether the system enters an automatic upgrading process or normally enters the system.
3. The method of claim 2, wherein:
if the system enters an automatic upgrading process, starting to read data transmitted by an external data unit through a data communication interface, and temporarily storing the data in a main processor RAM/FLASH ROM region after the read data is verified; after the external data is read, the main processor enters a downward write upgrading process;
after the main processor enters a downward write upgrading process, the main processor outputs a pin signal to reset a slave processor, the slave processor enters a write-in process of an upgrading program, and the upgrading program is written into the slave processor through a data communication interface;
after the upgrading program of the slave processor is written, a confirmed flag bit is replied through the data communication interface according to the program requirement, and after the master processor receives the confirmed flag bit, the slave processor can be confirmed to be upgraded successfully, and the next slave processor is entered into the upgrading and writing process;
if the main processor does not receive the confirmed flag bit, the upgrading program is determined to be failed to be written, and the main processor writes the upgrading program into the auxiliary processor again.
4. The method of claim 3, wherein:
after the first slave processor successfully writes the upgrading program, the master processor sequentially writes the upgrading program for the subsequent slave processors, and after the last slave processor successfully upgrades, the master processor jumps to the corresponding boot area to enter a self-upgrading process;
under the self-upgrading process, the main processor firstly carries out erasing and writing work of the program area, and carries out the program erasing and writing process in the boot area after ensuring that the program area is written correctly.
5. The method of claim 4, wherein:
the self-upgrade process specifically includes: after entering the self-upgrading process, the main processor sets an upgrading identifier, the existence of the identifier indicates that the upgrading is necessary, self-upgrading program data of a data communication interface is obtained according to the program requirement in a boot area and divided into two areas of the boot area and the program, the boot area is upgraded firstly, the read boot area data is placed in the program area firstly, the boot area is upgraded through a preset program, after the boot area is upgraded, the processor returns to a new boot area, the program area upgrading data is obtained, the program area is upgraded, and after the verification is completed, the upgrading identifier is removed to complete the upgrading process of the whole system.
6. The method according to any one of claims 1 to 5, wherein:
if the main processor makes a mistake in the process of writing into the program area when self-upgrading is carried out, the system can automatically send an alarm and needs to manually reset the whole system, when the system is electrified again, a boot area program in the main processor checks the integrity of the program area according to requirements, and after the program writing failure is confirmed, the self-upgrading process is entered again, the content of the upgrading program is read from the data communication interface, and erasing and writing are carried out again in the program area.
7. The method of claim 6, wherein:
and if the upgrading slave processor makes an error in the process of writing the original boot area of the upgrading slave processor, entering an abnormal mode, and executing a manual forced upgrading flow to re-execute upgrading for the master processor.
8. The method of claim 7, wherein:
and when the main processor is determined to fail to write and cannot be automatically recovered, entering a manual forced upgrading process: the equipment is powered off firstly, the equipment reset key is pressed, meanwhile, in order to ensure that the forced state is accurate, the external key is pressed simultaneously, the system is powered on again, the system is kept for 3-5 seconds, at the moment, the main processor is in the reset state, the main processor reset pin and the auxiliary processor start pin are triggered simultaneously, the auxiliary processor judges that the main processor is forced to reset and enters the takeover, and therefore the manual forced upgrading process is started.
9. The method of claim 8, wherein:
the slave processor obtains the upgrading program of the master processor through a communication data interface shared by the slave processor and the master processor, executes a mode similar to the upgrading of the slave processor by the master processor, carries out forced upgrading on the master processor, takes over necessary hardware resources of the original master processor by the slave processor at the moment, and carries out man-machine interaction processing through the slave processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110939186.7A CN113608769B (en) | 2021-08-16 | 2021-08-16 | Method for parallel processing and self-upgrading based on multiple single-chip microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110939186.7A CN113608769B (en) | 2021-08-16 | 2021-08-16 | Method for parallel processing and self-upgrading based on multiple single-chip microcomputer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113608769A true CN113608769A (en) | 2021-11-05 |
| CN113608769B CN113608769B (en) | 2024-05-03 |
Family
ID=78308693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110939186.7A Active CN113608769B (en) | 2021-08-16 | 2021-08-16 | Method for parallel processing and self-upgrading based on multiple single-chip microcomputer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113608769B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117422025A (en) * | 2023-12-18 | 2024-01-19 | 青岛本原微电子有限公司 | RISC-V architecture-based random interrupt debugging verification system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5388267A (en) * | 1991-05-29 | 1995-02-07 | Dell Usa, L.P. | Method and apparatus for updating and restoring system BIOS functions while maintaining BIOS integrity |
| US6175919B1 (en) * | 1997-05-02 | 2001-01-16 | Samsung Electronics Co., Ltd. | Method and apparatus for upgrading BIOS using a serial communication |
| CN105259806A (en) * | 2015-10-16 | 2016-01-20 | 珠海格力电器股份有限公司 | Controller upgrading method and system, master controller and slave controller |
| CN106775588A (en) * | 2016-11-30 | 2017-05-31 | 合肥科迈捷智能传感技术有限公司 | A kind of firmware upgrade method based on principal and subordinate processor framework |
| CN107229495A (en) * | 2017-05-25 | 2017-10-03 | 沃太能源南通有限公司 | A kind of system and method for preventing EMS remote upgrade from failing |
| CN109871225A (en) * | 2019-02-22 | 2019-06-11 | 北京经纬恒润科技有限公司 | Electronic control unit ECU upgrade method and ECU |
| CN110096294A (en) * | 2019-05-07 | 2019-08-06 | 柏科智能(厦门)科技有限公司 | It is a kind of can break-point radio upgrade MCU application program method |
-
2021
- 2021-08-16 CN CN202110939186.7A patent/CN113608769B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5388267A (en) * | 1991-05-29 | 1995-02-07 | Dell Usa, L.P. | Method and apparatus for updating and restoring system BIOS functions while maintaining BIOS integrity |
| US6175919B1 (en) * | 1997-05-02 | 2001-01-16 | Samsung Electronics Co., Ltd. | Method and apparatus for upgrading BIOS using a serial communication |
| CN105259806A (en) * | 2015-10-16 | 2016-01-20 | 珠海格力电器股份有限公司 | Controller upgrading method and system, master controller and slave controller |
| CN106775588A (en) * | 2016-11-30 | 2017-05-31 | 合肥科迈捷智能传感技术有限公司 | A kind of firmware upgrade method based on principal and subordinate processor framework |
| CN107229495A (en) * | 2017-05-25 | 2017-10-03 | 沃太能源南通有限公司 | A kind of system and method for preventing EMS remote upgrade from failing |
| CN109871225A (en) * | 2019-02-22 | 2019-06-11 | 北京经纬恒润科技有限公司 | Electronic control unit ECU upgrade method and ECU |
| CN110096294A (en) * | 2019-05-07 | 2019-08-06 | 柏科智能(厦门)科技有限公司 | It is a kind of can break-point radio upgrade MCU application program method |
Non-Patent Citations (1)
| Title |
|---|
| 项小玲: "BIOS升级失败后的补救办法", 电气时代, no. 02, 15 February 2021 (2021-02-15) * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117422025A (en) * | 2023-12-18 | 2024-01-19 | 青岛本原微电子有限公司 | RISC-V architecture-based random interrupt debugging verification system |
| CN117422025B (en) * | 2023-12-18 | 2024-03-29 | 青岛本原微电子有限公司 | Random interrupt debugging verification system based on RISC-V architecture |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113608769B (en) | 2024-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101329632B (en) | Method and apparatus for starting CPU by BOOT | |
| CN106257417B (en) | Boot program upgrading method, embedded equipment, control equipment and embedded system | |
| CN108958787B (en) | Block chain system upgrading method, device, equipment and storage medium | |
| CN105426198A (en) | Vehicle onboard double-control-chip system and auxiliary control chip program update method therefor | |
| CN109032021B (en) | Use method of redundant double-MCU hot backup control system | |
| CN105224362A (en) | Host computer carries out the method and system of program upgrade to slave computer | |
| CN113064748B (en) | Process succession method, device, electronic equipment and storage medium | |
| CN101295255B (en) | Firmware updating system and method | |
| CN105468390B (en) | BOOT online upgrading device and method | |
| CN109525473B (en) | Method and system for expanding CAN by MCU, MCU and computer medium | |
| CN113608769B (en) | Method for parallel processing and self-upgrading based on multiple single-chip microcomputer | |
| WO2023065601A1 (en) | Server component self-test anomaly recovery method and device, system, and medium | |
| CN114138295A (en) | Method, device and system for upgrading application program firmware of electronic equipment | |
| CN107315607B (en) | Drive self-adaptation loading system | |
| CN110532014B (en) | Program upgrading method, device, terminal equipment and computer readable storage medium | |
| CN113434354B (en) | Bus exception handling method and device, electronic equipment and readable storage medium | |
| KR100605031B1 (en) | Fault recovery and upgrade method of embedded system using USB memory device | |
| CN111124455B (en) | Battery management system upgrading method, device, server and storage medium | |
| CN118484212A (en) | Software flashing method and device of vehicle-mounted controller, electric vehicle and medium | |
| CN113377404B (en) | New energy vehicle domain controller safety monitoring chip program updating method and system | |
| CN117687663A (en) | OTA-based partition dynamic adjustment method, device, equipment and storage medium | |
| CN113626229B (en) | Motor control chip awakening method based on SBC | |
| CN111610995B (en) | Device firmware upgrading method and device, electronic device and storage medium | |
| CN113064668B (en) | On-line loading control system for executable file data of embedded platform | |
| CN112202969A (en) | Bluetooth control method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |