CN113595587B - Self-adaptive amplitude recovery system for transform domain interference suppression - Google Patents
Self-adaptive amplitude recovery system for transform domain interference suppression Download PDFInfo
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Abstract
The invention discloses a self-adaptive amplitude recovery system for transform domain interference suppression, and relates to the field of communication. The system comprises a frequency domain cache unit, a frequency domain power adjusting unit, an IFFT converting unit, a time domain cache unit, a time domain power adjusting unit and a clock domain converting unit. The system firstly adjusts the power of the frequency domain signal after interference suppression, then performs IFFT to transform the frequency domain signal into a time domain signal, and then adjusts the power of the time domain signal to realize the purpose of self-adaptive equalization of the time domain signal amplitude. The invention combines the transform domain interference suppression technology, adopts the mode of the combined work of the frequency domain signal power adaptive equalization and the time domain signal power adaptive equalization, and has the advantages of ensuring the stability of the time domain signal output power, being not large or small, simple and effective algorithm realization and the like compared with the existing transform domain interference suppression technology.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to an adaptive amplitude recovery system for transform domain interference suppression.
Background
The suppression of narrowband interference plays a very important role in the research of spread spectrum communication. Transform-domain interference cancellation techniques are widely used because they can cancel multiple narrowband interferences and do not increase the complexity of their algorithms.
At present, common transform domain interference suppression techniques basically adopt a filter structure based on FFT and IFFT and a windowed lapped transform method to achieve interference cancellation. However, the FFT and IFFT operations implemented on the FPGA require processing the input signal in a frame-wise manner in a high-speed clock domain, which may cause the problem of precision in fixed-point word length quantization of the digital signal, i.e., a time domain signal restored after interference is removed in a frequency domain in a frame-wise manner may have power fluctuation, thereby causing fluctuation of a rear-end demodulation signal-to-noise ratio to affect demodulation performance. Therefore, the method for self-adaptive amplitude recovery in the transform domain interference suppression technology is adopted to realize the self-adaptive equalization of the time domain signal amplitude after the interference suppression, and has important application value. However, such a technique is still lacking in the prior art.
Disclosure of Invention
In view of the foregoing, the present invention provides an adaptive amplitude recovery system for transform-domain interference suppression. The system can avoid the problem of power fluctuation of each frame of signal caused by FFT and IFFT operation through dual guarantee of frequency domain power control and time domain power control, thereby realizing the purpose of time domain signal amplitude adaptive equalization after interference suppression.
The purpose of the invention is realized as follows:
a self-adaptive amplitude recovery system for transform domain interference suppression comprises a frequency domain buffer unit 1, a frequency domain power adjusting unit 2, an IFFT transforming unit 3, a time domain buffer unit 4, a time domain power adjusting unit 5 and a clock domain transforming unit 6;
the frequency domain buffer unit 1 buffers externally input frequency domain signals after interference suppression by using an RAM according to frames and outputs the buffered frequency domain signals to the frequency domain power adjusting unit 2;
the frequency domain power adjusting unit 2 calculates the power of the externally input frequency domain signal after interference suppression, compares the frequency domain signal with a preset value to obtain a frequency domain adjusting coefficient, and sends an identifier to the frequency domain caching unit 1 after calculation; in addition, the frequency domain power adjusting unit 2 also multiplies the buffered frequency domain signal sent by the frequency domain buffering unit 1 by a frequency domain adjusting coefficient, and then outputs the result to the IFFT transforming unit 3;
the IFFT unit 3 performs IFFT conversion on the signal sent by the frequency domain power adjusting unit 2, and outputs the obtained time domain signal to the time domain power adjusting unit 5 and the time domain buffer unit 4 respectively;
the time domain buffer unit 4 buffers the time domain signal output by the IFFT unit 3 through the RAM, and outputs the buffered time domain signal to the time domain power adjustment unit 5;
the time domain power adjusting unit 5 calculates the power of the time domain signal output by the IFFT unit 3, compares the calculated power with a preset value to obtain a time domain adjusting coefficient, and sends an identifier to the time domain caching unit 4 after calculation; in addition, the time domain power adjusting unit 5 also multiplies the buffered time domain signal sent by the time domain buffering unit 4 by a time domain adjusting coefficient, and then outputs the result to the clock domain transforming unit 6;
the clock domain transforming unit 6 transforms the burst time domain signal in the high-speed working clock domain sent by the time domain power adjusting unit 5 to a continuous time domain signal in the actual signal clock domain by using the FIFO, so that a continuous time domain signal with balanced amplitude is obtained after the interference suppression of the transform domain.
Further, the externally input frequency domain signal after interference suppression includes IQ two-path frequency domain signals and a frequency domain signal valid identifier.
Further, the frequency domain buffer unit 1 includes a frequency domain write control unit 7, a frequency domain RAM unit 8 and a frequency domain read control unit 9;
under a high-speed working clock domain, the frequency domain write control unit 7 calculates the write address and write enable of the RAM according to the effective identifier of the frequency domain signal and the known frame length, and inputs the externally input frequency domain signal, write address and write enable after interference suppression into the frequency domain RAM unit 8;
after detecting the high pulse of the ending identifier sent by the frequency domain power adjusting unit 2, the frequency domain read control unit 9 calculates the read address and the read enable of the RAM according to the known frame length, and outputs the read address and the read enable to the frequency domain RAM unit 8;
the frequency domain RAM unit 8 buffers the frequency domain signal after interference suppression according to the write address and the write enable under the control of the frequency domain write control unit 7; in addition, the buffered interference-suppressed frequency domain signal is output to the frequency domain power adjustment unit 2 under the control of the frequency domain read control unit 9.
Further, the frequency domain power adjusting unit 2 operates as follows:
step S101, according to the known frame length N, when the effective identifier of the frequency domain signal is high level, power calculation is carried out on the IQ two paths of frequency domain signals, and the calculation mode is as follows:
wherein P1 is the power value, IiFor the power value of the I-path signal at I in the frame, QiThe power value of the Q-path signal at the position i in the frame is obtained;
step S102, a divider of the FPGA is utilized to preset a frequency domain reference value P1rDividing by P1 to obtain a quotient, namely a frequency domain adjustment coefficient alpha; wherein, the preset frequency domain reference value P1rThe calculation method of (c) is as follows:
in the formula, BWfThe BIT BIT width of IQ two-path frequency domain signals is represented;
step S103, completion P1rAfter the calculation, a high pulse is output to the frequency domain cache unit 1, then a frequency domain signal effective identifier in the cached interference-suppressed frequency domain signal sent by the frequency domain cache unit 1 is waited, when a high level is detected, the step S104 is skipped, otherwise, the waiting is continued;
step S104, when detecting the high level of the effective identifier of the frequency domain signal, multiplying the frequency domain adjustment coefficient α by the IQ two-way frequency domain signal in the buffered interference-suppressed frequency domain signal sent from the frequency domain buffering unit 1, and outputting the adjusted frequency domain signal and the effective identifier of the frequency domain signal to the IFFT transforming unit 3.
Further, the IFFT unit 3 performs IFFT on the input adjusted N-point frequency domain signal by using an IFFT kernel of the FPGA, and outputs the obtained N-point IQ two-path time domain signal and the corresponding time domain signal effective identifier to the time domain buffer unit 4 and the time domain power adjustment unit 5 at the same time.
Further, the time domain buffer unit 4 includes a time domain write control unit 10, a time domain RAM unit 11, and a time domain read control unit 12;
under the high-speed working clock domain, the time domain write control unit 10 calculates the write address and write enable of the RAM according to the time domain signal valid identifier and the known frame length sent by the IFFT transforming unit 3, and outputs the three signals sent by the IFFT transforming unit 3 and the write address and write enable to the time domain RAM unit 11;
after detecting the high pulse of the end identifier sent by the time domain power adjusting unit 5, the time domain read control unit 12 calculates the read address and the read enable of the RAM according to the known frame length, and outputs the read address and the read enable to the time domain RAM unit 11;
under the control of the time domain write control unit 10, the time domain RAM unit 11 buffers the three signals sent by the IFFT transforming unit 3 according to the write address and the write enable; further, the buffered signal is output to the time domain power adjusting unit 5 under the control of the time domain read control unit 12.
Further, the time domain power adjusting unit 5 operates as follows:
step S201, according to the known frame length N, when the time domain signal valid identifier sent by the IFFT transforming unit 3 is at a high level, performing power calculation on the IQ two-way time domain signal sent by the IFFT transforming unit 3, where the calculation method is as follows:
wherein P2 is the power value;
step S202, utilizing a divider of the FPGA to preset a frequency domain reference value P2rDividing by P2 to obtain quotient-time domain adjustment coefficient beta; wherein, the preset frequency domain reference value P2rThe calculation method of (c) is as follows:
in the formula, BWMIs BWtAnd BWoMaximum value of (1), BWtBIT BIT width, B representing IQ two-path time domain signalsWoThe BIT BIT width of the IQ two-path time domain signals output after adjustment is represented;
step S203, P2 is completedrAfter the calculation, a high pulse is output to the time domain buffer unit 4, and thenWaiting for the time domain signal valid identifier in the cache signal sent by the time domain cache unit 4, skipping to the step S204 when detecting a high level, otherwise continuing to wait;
step S204, when the high level of the effective identifier of the time domain signal is detected, the time domain adjusting coefficient beta is multiplied by IQ two-path time domain signals in the cache signal sent by the time domain cache unit 4 respectively, and then the high end B is intercepted from the resultWoAnd the signal with the bit width outputs the adjusted time domain signal to the clock domain transformation unit 6 together with the time domain signal effective identifier.
Furthermore, the clock domain transforming unit 6 stores the time domain signal with the adaptively adjusted amplitude sent by the time domain power adjusting unit 5 into the FIFO of the FPGA itself, and then continuously outputs the time domain signal with the adaptively adjusted amplitude after the interference suppression in the signal clock domain, thereby realizing the amplitude adaptive recovery of the time domain signal with the adaptively adjusted amplitude under the transform domain interference suppression.
Compared with the background technology, the invention has the following advantages:
1. the invention does not need complex mathematical operation, only utilizes the divider, the RAM and the FIFO module of the FPGA, has simple and effective algorithm and low realization complexity, and is more beneficial to the programming realization of embedded software (such as VHDL/Verilog) in a receiver.
2. The invention combines the common transform domain interference technology in the direct sequence spread spectrum receiver interference suppression technology, and utilizes the design of frequency domain and time domain signal power double equalization to realize the purpose of time domain signal amplitude self-adaptive equalization after interference suppression, thus being simple and easy to use.
3. The invention reduces the demodulation performance loss caused by FFT and IFFT fixed point operation as much as possible by means of the algorithm of time domain signal amplitude adaptive equalization, and is beneficial to the stability of the demodulation performance of the receiver.
4. The invention is flexible and configurable, has no requirement on an interference suppression algorithm in a transform domain interference technology, and has wide application range.
Drawings
Fig. 1 is a schematic block diagram of an embodiment of the present invention.
Fig. 2 is a schematic block diagram of a frequency domain buffer unit.
Fig. 3 is a flow chart of a frequency domain power adjustment unit.
Fig. 4 is a schematic block diagram of a time domain buffer unit.
Fig. 5 is a flow chart of a time domain power adjustment unit.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description.
As shown in fig. 1-5, an adaptive amplitude recovery system for transform domain interference suppression includes a frequency domain buffer unit 1, a frequency domain power adjustment unit 2, an IFFT transform unit 3, a time domain buffer unit 4, a time domain power adjustment unit 5, and a clock domain transform unit 6;
the frequency domain buffer unit 1 buffers externally input frequency domain signals after interference suppression by using an RAM according to frames and outputs the buffered frequency domain signals to the frequency domain power adjusting unit 2;
the frequency domain power adjusting unit 2 calculates the power of the externally input frequency domain signal after interference suppression, compares the frequency domain signal with a preset value to obtain a frequency domain adjusting coefficient, and sends an identifier to the frequency domain caching unit 1 after calculation; in addition, the frequency domain power adjusting unit 2 also multiplies the buffered frequency domain signal sent by the frequency domain buffering unit 1 by a frequency domain adjusting coefficient, and then outputs the result to the IFFT transforming unit 3;
the IFFT unit 3 performs IFFT conversion on the signal sent by the frequency domain power adjusting unit 2, and outputs the obtained time domain signal to the time domain power adjusting unit 5 and the time domain buffer unit 4 respectively;
the time domain buffer unit 4 buffers the time domain signal output by the IFFT unit 3 through the RAM, and outputs the buffered time domain signal to the time domain power adjustment unit 5;
the time domain power adjusting unit 5 calculates the power of the time domain signal output by the IFFT unit 3, compares the calculated power with a preset value to obtain a time domain adjusting coefficient, and sends an identifier to the time domain caching unit 4 after calculation; in addition, the time domain power adjusting unit 5 also multiplies the buffered time domain signal sent by the time domain buffering unit 4 by a time domain adjusting coefficient, and then outputs the result to the clock domain transforming unit 6;
the clock domain transforming unit 6 transforms the burst time domain signal in the high-speed working clock domain sent by the time domain power adjusting unit 5 to a continuous time domain signal in the actual signal clock domain by using the FIFO, so that a continuous time domain signal with balanced amplitude is obtained after the interference suppression of the transform domain.
Further, the externally input frequency domain signal after interference suppression includes IQ two-path frequency domain signals and a frequency domain signal valid identifier.
Further, the frequency domain buffer unit 1 includes a frequency domain write control unit 7, a frequency domain RAM unit 8 and a frequency domain read control unit 9;
under a high-speed working clock domain, the frequency domain write control unit 7 calculates the write address and write enable of the RAM according to the effective identifier of the frequency domain signal and the known frame length, and inputs the externally input frequency domain signal, write address and write enable after interference suppression into the frequency domain RAM unit 8;
after detecting the high pulse of the end identifier sent by the frequency domain power adjusting unit 2, the frequency domain read control unit 9 calculates the read address and the read enable of the RAM according to the known frame length, and outputs the read address and the read enable to the frequency domain RAM unit 8;
the frequency domain RAM unit 8 buffers the frequency domain signal after interference suppression according to the write address and the write enable under the control of the frequency domain write control unit 7; in addition, the buffered interference-suppressed frequency domain signal is output to the frequency domain power adjustment unit 2 under the control of the frequency domain read control unit 9.
Further, the frequency domain power adjusting unit 2 operates as follows:
step S101, according to the known frame length N, when the effective identifier of the frequency domain signal is high level, carrying out power calculation on the IQ two paths of frequency domain signals, wherein the calculation mode is as follows:
wherein P1 is the power value, IiFor the power value of the I-path signal in the frame I, QiThe power value of the Q-path signal at the position i in the frame is obtained;
step S102, utilizing a divider of the FPGA to preset a frequency domain reference value P1rDividing by P1 to obtain a quotient, namely a frequency domain adjustment coefficient alpha; wherein, the preset frequency domain reference value P1rThe calculation method of (c) is as follows:
in the formula, BWfThe BIT BIT width of IQ two-path frequency domain signals is represented;
step S103, completion P1rAfter the calculation, a high pulse is output to the frequency domain cache unit 1, then the effective identifier of the frequency domain signal in the cached frequency domain signal after interference suppression sent by the frequency domain cache unit 1 is waited, when a high level is detected, the step S104 is skipped, otherwise, the waiting is continued;
step S104, when detecting the high level of the effective identifier of the frequency domain signal, multiplying the frequency domain adjustment coefficient α by the IQ two-way frequency domain signal in the buffered interference-suppressed frequency domain signal sent from the frequency domain buffering unit 1, and outputting the adjusted frequency domain signal and the effective identifier of the frequency domain signal to the IFFT transforming unit 3.
Further, the IFFT unit 3 performs IFFT on the input adjusted N-point frequency domain signal by using an IFFT kernel of the FPGA, and outputs the obtained N-point IQ two-path time domain signal and the corresponding time domain signal effective identifier to the time domain buffer unit 4 and the time domain power adjustment unit 5 at the same time.
Further, the time domain buffer unit 4 includes a time domain write control unit 10, a time domain RAM unit 11, and a time domain read control unit 12;
under the high-speed working clock domain, the time domain write control unit 10 calculates the write address and write enable of the RAM according to the time domain signal valid identifier and the known frame length sent by the IFFT transforming unit 3, and outputs the three signals sent by the IFFT transforming unit 3 and the write address and write enable to the time domain RAM unit 11;
after detecting the high pulse of the end identifier sent by the time domain power adjusting unit 5, the time domain read control unit 12 calculates the read address and the read enable of the RAM according to the known frame length, and outputs the read address and the read enable to the time domain RAM unit 11;
the time domain RAM unit 11 buffers the three signals sent by the IFFT transforming unit 3 according to the write address and the write enable under the control of the time domain write control unit 10; further, the buffered signal is output to the time domain power adjusting unit 5 under the control of the time domain read control unit 12.
Further, the time domain power adjusting unit 5 operates as follows:
step S201, according to the known frame length N, when the time domain signal valid identifier sent by the IFFT transforming unit 3 is at a high level, performing power calculation on the IQ two-way time domain signal sent by the IFFT transforming unit 3, where the calculation method is as follows:
wherein P2 is the power value;
step S202, utilizing a divider of the FPGA to preset a frequency domain reference value P2rDividing by P2 to obtain quotient-time domain adjustment coefficient beta; wherein, the preset frequency domain reference value P2rThe calculation method of (c) is as follows:
in the formula, BWMIs BWtAnd BWoMaximum value of (1), BWtBIT width, B, representing IQ two-path time domain signalsWoThe BIT BIT width of the IQ two-path time domain signals output after adjustment is represented;
step S203, P2 is completedrAfter the calculation, a high pulse is output to the time domain cache unit 4, then a time domain signal effective identifier in a cache signal sent by the time domain cache unit 4 is waited, when a high level is detected, the step S204 is skipped to, otherwise, the waiting is continued;
step S204, when the high level of the effective identifier of the time domain signal is detected, the time domain adjusting coefficient is divided into betaMultiplying IQ two paths of time domain signals in the buffer signals sent by the time domain buffer unit 4 respectively, and then intercepting the result to a high end BWoAnd the signal with the bit width outputs the adjusted time domain signal and the effective identifier of the time domain signal to the clock domain transformation unit 6.
Further, the clock domain transforming unit 6 stores the amplitude adaptively adjusted time domain signal sent by the time domain power adjusting unit 5 into the FIFO of the FPGA itself, and then continuously outputs the amplitude adaptively adjusted time domain signal after the interference suppression in the signal clock domain, thereby realizing the amplitude adaptive recovery of the time domain signal under the transform domain interference suppression.
The following is a more specific example:
a self-adaptive amplitude recovery system for transform domain interference suppression comprises a frequency domain cache unit 1, a frequency domain power adjusting unit 2, an IFFT (inverse fast Fourier transform) converting unit 3, a time domain cache unit 4, a time domain power adjusting unit 5, a clock domain converting unit 6, a frequency domain write control unit 7, a frequency domain RAM (random access memory) unit 8, a frequency domain read control unit 9, a time domain write control unit 10, a time domain RAM unit 11 and a time domain read control unit 12.
Wherein, the frequency domain buffer unit 1 is used for buffering the frequency domain signal which is input from outside and has suppressed interference and is segmented according to the length of a fixed frame into a RAM according to the frame and outputting the signal after waiting for marking a high pulse, the frequency domain power adjusting unit 2 is used for calculating the signal power of each frame and calculating according to a preset signal power value to obtain an adjusting coefficient, then multiplying the buffered frame frequency domain signal by the adjusting coefficient and sending the signal to an IFFT module, the IFFT converting unit 3 is used for carrying out IFFT conversion on the input frame frequency domain signal to obtain a frame time domain signal after interference suppression, the time domain buffer unit 4 is used for buffering the time domain signal in the RAM according to the frame and outputting the signal after waiting for marking a high pulse, the time domain power adjusting unit 5 is used for calculating the signal power of each frame and calculating according to a preset signal power value to obtain an adjusting coefficient, then multiplying the buffered frame frequency domain signal by the adjusting coefficient and outputting the signal after combining with the bit width quantization, the clock domain transforming unit 6 is used for transforming the burst time domain signal in the high-speed working clock domain into the continuous time domain signal in the actual signal clock domain.
The frequency domain write control unit 7 is used for calculating the write address and the write enable of the RAM according to the effective identifier of the input frequency domain signal and the known frame length, the frequency domain RAM unit 8 is used for buffering the input effective frequency domain signal, and the frequency domain read control unit 9 is used for calculating the read address and the read enable of the RAM according to the known frame length after detecting the high pulse of the input identifier.
The frequency domain power adjusting unit works as follows:
step S1, according to the known frame length N, when the input effective identifier is high level, calculating the power P1 of the input signal, and after the calculation is finished, jumping to step S2;
step S2, according to the preset frequency domain reference value P1rObtaining an adjustment coefficient alpha by P1, and jumping to step S3 after the calculation is finished;
step S3, outputting a high pulse to the frequency domain buffer unit, and jumping to step S4 after detecting the high level of the identifier input by the frequency domain buffer unit;
and step S4, multiplying the adjustment coefficient alpha by the IQ two paths of frequency domain signals input by the frequency domain buffer unit respectively, and outputting the adjusted frequency domain signals and the effective identifier.
The time domain write control unit 10 is used for calculating the write address and the write enable of the RAM according to the effective identifier of the input time domain signal and the known frame length, the time domain RAM unit 11 is used for buffering the input effective time domain signal, and the time domain read control unit 12 is used for calculating the read address and the read enable of the RAM according to the known frame length after detecting the high pulse of the input identifier.
The time domain power adjusting unit works as follows:
step S1, according to the known frame length N, when the input effective identifier is high level, calculating the power P2 of the input signal, and after the calculation is finished, jumping to step S2;
step S2, according to the preset frequency domain reference value P2rObtaining an adjustment coefficient beta by P2, and jumping to step S3 after the calculation is finished;
step S3, outputting a high pulse to the time domain buffer unit, and jumping to step S4 after detecting the high level of the identifier input by the time domain buffer unit;
step S4, the adjustment coefficient beta is multiplied by IQ two paths of time domain signals input by the time domain buffer unit respectively, and then the result is intercepted to obtain the high end BWoAnd outputting the adjusted time domain signal and the effective identifier by using the bit width signal.
The system briefly works on the following principle:
the system adopts a mode of combining frequency domain signal power adaptive equalization and time domain signal power adaptive equalization to solve the problem of time domain signal power jitter caused by FFT and IFFT fixed point operation in FPGA development. The device mainly comprises a frequency domain buffer unit 1, a frequency domain power adjusting unit 2, an IFFT converting unit 3, a time domain buffer unit 4, a time domain power adjusting unit 5, a clock domain converting unit 6, a frequency domain write control unit 7, a frequency domain RAM unit 8, a frequency domain read control unit 9, a time domain write control unit 10, a time domain RAM unit 11 and a time domain read control unit 12. The frequency domain buffer unit buffers the frequency domain signal input by the external according to the fixed frame length in the RAM and outputs the signal after waiting for marking the high pulse. And the frequency domain power adjusting unit calculates an adjusting coefficient of each frame and adjusts and outputs the frame frequency domain signal. The IFFT unit performs IFFT on an input frame frequency domain signal to obtain a time domain signal. And the time domain buffer unit is used for buffering the time domain signal input by the outside according to the fixed frame length in the RAM and outputting the time domain signal after waiting for marking the high pulse. And the time domain power adjusting unit calculates to obtain an adjusting coefficient of each frame and adjusts and quantizes the time domain signal of the frame and outputs the time domain signal according to the required bit width. The clock domain transforming unit transforms the time domain signal input by frames to a continuous time domain signal under an actual signal clock domain. The frequency domain write control unit calculates a write address and a write enable of the RAM according to an input frequency domain signal valid identifier and a known frame length. The frequency domain RAM unit buffers and inputs the effective frequency domain signal according to the frame. And after detecting the input identifier high pulse, the frequency domain reading control unit calculates the reading address and the reading enable of the RAM according to the known frame length. The time domain write control unit calculates a write address and a write enable of the RAM according to an input time domain signal valid identifier and a known frame length. The time domain RAM unit inputs effective time domain signals according to frame buffer. And after detecting the input identifier high pulse, the time domain read control unit calculates the read address and the read enable of the RAM according to the known frame length.
The working process of the system is as follows:
the direct sequence spread spectrum receiver receives an analog signal, and after AD sampling and narrow-band interference suppression processing in a frequency domain, the digital baseband signal is sent to a frequency domain buffer unit 1 and a frequency domain power adjusting unit 2. The frequency domain write control unit 7 in the frequency domain cache unit 1 calculates write enable and write addresses according to the input signal valid identifiers and outputs the write enable and write addresses to the frequency domain RAM unit 8, and the frequency domain RAM unit 8 caches the two input paths of valid signals according to frames. Meanwhile, the frequency domain power adjusting unit 2 calculates the power value P1 of the input effective digital baseband signal and obtains a frequency domain reference value P1rAnd calculating to obtain an adjustment coefficient alpha, and outputting a high pulse to a frequency domain read control unit 9 in the frequency domain cache unit 1 after the calculation is finished. After detecting the high pulse, the frequency domain read control unit 9 starts to calculate the read address and the read enable of the RAM and outputs the read address and the read enable to the frequency domain RAM unit 8, so that the frequency domain read control unit outputs a buffered frame frequency domain digital baseband signal to the frequency domain power adjustment unit 2. The frequency domain power adjusting unit 2 multiplies the input buffer frame by the adjusting coefficient α and outputs the result to the IFFT transforming unit 3. The IFFT converting unit 3 performs IFFT conversion on the input frequency domain digital baseband signal by using the IP core of the FPGA itself on a frame-by-frame basis, and outputs the obtained time domain digital baseband signal to the time domain buffer unit 4 and the time domain power adjusting unit 5 on a frame-by-frame basis. The time domain write control unit 10 in the time domain buffer unit 4 calculates write enable and write address according to the input signal valid identifier and outputs the write enable and write address to the time domain RAM unit 11, and the time domain RAM unit 11 buffers the two input valid signals according to frames. Meanwhile, the time domain power adjusting unit 5 calculates the power value P2 of the input effective digital baseband signal and obtains the frequency domain reference value P2rAnd calculating to obtain an adjustment coefficient beta, and outputting a high pulse to a time domain read control unit 12 in the time domain cache unit 4 after the calculation is finished. After detecting the high pulse, the time domain read control unit 12 starts to calculate the read address and the read enable of the RAM and outputs the read address and the read enable to the time domain RAM unit 11, so that the time domain RAM unit outputs a frame of buffered time domain digital baseband signal to the time domain power adjustment unit 5. The time domain power adjusting unit 5 multiplies the input buffer frame by the adjusting coefficient beta, and quantizes the result to the bit width B of the output time domain signalWoAnd then output to the clock domain conversion unit 6. The clock domain conversion unit 6 converts the burst time domain digital baseband signal input according to the frame under the high-speed clock domain into the actual low-speed signal clock domain for continuous output through the FIFO of the FPGA, thereby realizing the purpose of self-adaptive recovery of the time domain signal amplitude in the transform domain interference suppression technology.
In summary, the invention firstly caches the frequency domain signal which has been inhibited from interference and is segmented according to the length of a fixed frame according to the frame, calculates the signal power of each frame, calculates the adjustment coefficient according to the preset signal power value and the actual frequency domain signal power of each frame, multiplies the cached frame frequency domain signal by the adjustment coefficient, sends the signal to the IFFT module for the calculation of the transformation domain, caches the time domain signal according to the frame, calculates the signal power of each frame, calculates the adjustment coefficient according to the preset signal power value and the actual time domain signal power of each frame, multiplies the cached frame time domain signal by the adjustment coefficient, outputs the signal, performs clock domain transformation, and continuously outputs the signal to the rear end for demodulation, thereby realizing the purpose of IFFT output time domain signal power self-adaptive equalization.
The invention combines the transform domain interference suppression technology, adopts the mode of the combined work of the frequency domain signal power self-adaptive equalization and the time domain signal power self-adaptive equalization, has the advantages of ensuring that the output power of the time domain signal is stable and can not be neglected, the algorithm is simple and effective, and the like compared with the existing transform domain interference suppression technology, has limited expense of added storage resources, can overcome the defect of discontinuous rear-end digital signal processing amplitude caused by the power jitter of each frame signal brought by the IFFT fixed-point operation in the FPGA development, and is particularly suitable for the condition that the transform domain interference suppression technology is adopted in a direct sequence spread spectrum receiver.
Claims (6)
1. A self-adaptive amplitude recovery system for transform domain interference suppression is characterized by comprising a frequency domain buffer unit (1), a frequency domain power adjusting unit (2), an IFFT (inverse fast Fourier transform) unit (3), a time domain buffer unit (4), a time domain power adjusting unit (5) and a clock domain transforming unit (6);
the frequency domain buffer unit (1) buffers externally input frequency domain signals after interference suppression by using an RAM according to frames and outputs the buffered frequency domain signals to the frequency domain power adjusting unit (2);
the frequency domain power adjusting unit (2) calculates the power of the externally input frequency domain signal after interference suppression, compares the frequency domain signal with a preset value to obtain a frequency domain adjusting coefficient, and sends a corresponding ending identifier to the frequency domain cache unit (1) after calculation is finished; in addition, the frequency domain power adjusting unit (2) also multiplies the buffered frequency domain signal sent by the frequency domain buffering unit (1) by a frequency domain adjusting coefficient, and then outputs the frequency domain signal to the IFFT transforming unit (3); the frequency domain power adjusting unit (2) works in the following way:
step S101, according to the known frame length N, when the effective identifier of the frequency domain signal is high level, carrying out power calculation on the IQ two paths of frequency domain signals, wherein the calculation mode is as follows:
wherein P1 is the power value, IiFor the power value of the I-path signal at I in the frame, QiThe power value of the Q-path signal at the position i in the frame is obtained;
step S102, utilizing a divider of the FPGA to preset a frequency domain reference value P1rDividing by P1 to obtain a quotient, namely a frequency domain adjustment coefficient alpha; wherein, the preset frequency domain reference value P1rThe calculation method of (c) is as follows:
in the formula, BWfThe BIT BIT width of IQ two-path frequency domain signals is represented;
step S103, completion P1rAfter the calculation, a high pulse is output to the frequency domain cache unit (1), then the effective identifier of the frequency domain signal in the cached frequency domain signal after interference suppression sent by the frequency domain cache unit (1) is waited, when a high level is detected, the step S104 is skipped, otherwise, the waiting is continued;
step S104, when detecting the high level of the effective identifier of the frequency domain signal, multiplying the frequency domain adjusting coefficient alpha by IQ two paths of frequency domain signals in the frequency domain signal after the interference suppression which is cached by the frequency domain caching unit (1) respectively, and outputting the adjusted frequency domain signal and the effective identifier of the frequency domain signal to the IFFT converting unit (3);
an IFFT conversion unit (3) performs IFFT conversion on the signal sent by the frequency domain power adjustment unit (2), and outputs the obtained time domain signal to a time domain power adjustment unit (5) and a time domain buffer unit (4) respectively;
the time domain buffer unit (4) buffers the time domain signal output by the IFFT conversion unit (3) through an RAM and outputs the buffered time domain signal to the time domain power adjustment unit (5);
the time domain power adjusting unit (5) calculates the power of the time domain signal output by the IFFT unit (3), compares the time domain signal with a preset value to obtain a time domain adjusting coefficient, and sends a corresponding ending identifier to the time domain cache unit (4) after the time domain adjusting coefficient is calculated; in addition, the time domain power adjusting unit (5) multiplies the buffered time domain signal sent by the time domain buffering unit (4) by a time domain adjusting coefficient, and then outputs the time domain signal to the clock domain transforming unit (6); the working mode of the time domain power adjusting unit (5) is as follows:
step S201, according to the known frame length N, when the effective identifier of the time domain signal sent by the IFFT unit (3) is high level, the power calculation is carried out on the IQ two paths of time domain signals sent by the IFFT unit (3), and the calculation mode is as follows:
wherein P2 is the power value;
step S202, utilizing a divider of the FPGA to preset a frequency domain reference value P2rDividing by P2 to obtain quotient, i.e. time domain adjustment coefficient beta; wherein, the preset frequency domain reference value P2rThe calculation method of (c) is as follows:
in the formula, BWMIs BWtAnd BWoMaximum value of (1), BWtBIT width, B, representing IQ two-path time domain signalsWoBIT width of IQ two-path time domain signals output after adjustment is represented;
step S203, P2 is completedrAfter the calculation, a high pulse is output to the time domain cache unit (4), then a time domain signal effective identifier in a cache signal sent by the time domain cache unit (4) is waited, when a high level is detected, the step S204 is skipped to, otherwise, the waiting is continued;
step S204, when the high level of the effective identifier of the time domain signal is detected, the time domain adjusting coefficient beta is respectively multiplied by IQ two paths of time domain signals in the cache signal sent by the time domain cache unit (4), and then the high end B is intercepted from the resultWoThe bit width signal outputs the adjusted time domain signal and the time domain signal effective identifier to a clock domain conversion unit (6);
the clock domain conversion unit (6) converts the burst time domain signal under the high-speed working clock domain sent by the time domain power adjustment unit (5) into a continuous time domain signal under an actual signal clock domain by using FIFO, so that the continuous time domain signal with balanced amplitude is obtained after the interference of the conversion domain is suppressed.
2. The adaptive amplitude recovery system for transform-domain interference suppression according to claim 1, wherein the externally input interference-suppressed frequency-domain signal comprises an IQ two-way frequency-domain signal and a frequency-domain signal valid identifier.
3. An adaptive amplitude restoration system for transform domain interference suppression according to claim 2, characterized in that the frequency domain buffering unit (1) comprises a frequency domain write control unit (7), a frequency domain RAM unit (8) and a frequency domain read control unit (9);
under a high-speed working clock domain, a frequency domain write control unit (7) calculates the write address and write enable of the RAM according to the effective identifier of the frequency domain signal and the known frame length, and inputs the externally input frequency domain signal, write address and write enable after interference suppression into a frequency domain RAM unit (8);
after detecting the end identifier sent by the frequency domain power adjusting unit (2), the frequency domain reading control unit (9) calculates the reading address and the reading enable of the RAM according to the known frame length and outputs the reading address and the reading enable to the frequency domain RAM unit (8);
under the control of the frequency domain write control unit (7), the frequency domain RAM unit (8) buffers the frequency domain signal after interference suppression according to the write address and the write enable; in addition, the buffered frequency domain signal after interference suppression is output to the frequency domain power adjusting unit (2) under the control of the frequency domain reading control unit (9).
4. The adaptive amplitude restoration system for transform domain interference suppression according to claim 3, wherein the IFFT transformation unit (3) performs IFFT transformation on the input adjusted N-point frequency domain signal by using an IFFT kernel of the FPGA itself, and outputs the obtained N-point IQ two-path time domain signal and the corresponding time domain signal effective identifier to the time domain buffer unit (4) and the time domain power adjustment unit (5) at the same time.
5. An adaptive amplitude recovery system for transform domain interference suppression according to claim 4, characterized in that the time domain buffer unit (4) comprises a time domain write control unit (10), a time domain RAM unit (11) and a time domain read control unit (12);
under a high-speed working clock domain, a time domain write control unit (10) calculates the write address and write enable of the RAM according to the effective identifier of the time domain signal sent by the IFFT unit (3) and the known frame length, and outputs three signals sent by the IFFT unit (3) and the write address and write enable to a time domain RAM unit (11);
after detecting the end identifier sent by the time domain power adjusting unit (5), the time domain reading control unit (12) calculates the reading address and the reading enable of the RAM according to the known frame length and outputs the reading address and the reading enable to the time domain RAM unit (11);
under the control of the time domain write control unit (10), the time domain RAM unit (11) buffers the three signals sent by the IFFT conversion unit (3) according to the write address and the write enable; in addition, the buffered signal is output to a time domain power adjustment unit (5) under the control of a time domain read control unit (12).
6. The adaptive amplitude recovery system for transform domain interference suppression according to claim 5, wherein the clock domain transforming unit (6) stores the amplitude adaptively adjusted time domain signal sent by the time domain power adjusting unit (5) into the FIFO of the FPGA itself, and then continuously outputs the amplitude adaptively adjusted time domain signal after the interference suppression in the signal clock domain, thereby achieving the amplitude adaptive recovery of the time domain signal under the transform domain interference suppression.
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