CN113589642A - Method, apparatus, computer device and medium for predicting open circuit defect of integrated circuit - Google Patents
Method, apparatus, computer device and medium for predicting open circuit defect of integrated circuit Download PDFInfo
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Abstract
本发明能够提供集成电路开路缺陷预测的方法、装置、计算机设备及介质，该方法可包括如下步骤。对集成电路设计版图包含的光刻图形进行光学邻近效应矫正，以得到第一仿真图形。基于刻蚀第一仿真图形的过程对第一仿真图形进行修正，以得到第二仿真图形。基于化学机械平坦化处理第二仿真图形的过程对第二仿真图形进行修正，以得到第三仿真图形。通过对第三仿真图形包含的目标线条图形进行分段划分的方式确定多个图形片段。根据所有图形片段的形貌特征预测目标线条图形是否存在开路缺陷。本发明结合了光学邻近效应、刻蚀、化学机械平坦化等多种工艺的涨落因素，实现一种抗工艺涨落的集成电路开路缺陷预测方法，提升了集成电路的良率和可靠性。
The present invention can provide a method, apparatus, computer equipment and medium for predicting an open circuit defect of an integrated circuit. The method may include the following steps. The optical proximity effect correction is performed on the lithography pattern included in the design layout of the integrated circuit to obtain the first simulation pattern. The first simulation figure is modified based on the process of etching the first simulation figure to obtain the second simulation figure. The second simulated graphic is modified based on the process of processing the second simulated graphic by chemical mechanical planarization, so as to obtain a third simulated graphic. A plurality of graphic segments are determined by segmenting the target line graphic included in the third simulation graphic. Predict whether there is an open circuit defect in the target line pattern according to the topographic features of all pattern segments. The invention combines the fluctuation factors of various processes such as optical proximity effect, etching, chemical mechanical planarization, etc., to realize an integrated circuit open circuit defect prediction method that resists process fluctuation, and improves the yield and reliability of the integrated circuit.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a method, an apparatus, a computer device, and a medium for predicting an open defect of an integrated circuit.
Background
The development speed of moore's law is gradually slowed down with the evolution of integrated circuit process nodes, and the manufacturing difficulty and cost of integrated circuits are continuously increased. With the increase of the complexity of chip manufacturing, the simulation verification before chip casting is particularly important, and the rework in the subsequent flow sheet is avoided to the greatest extent possible. Conventional Check before tape-out is generally DRC (Design Rule Check), but this method still cannot sufficiently ensure yield, and improvement or optimization is urgently needed.
Disclosure of Invention
In order to solve the problem that the traditional inspection scheme before tape-out cannot fully ensure the yield, the invention can provide a method, a device, computer equipment and a medium for predicting the open-circuit defect of the integrated circuit, which can predict the open-circuit defect before tape-out, improve the yield of the integrated circuit and enhance the reliability of the integrated circuit.
To achieve the above technical objectives, the present invention discloses a method for predicting open defects of an integrated circuit, which may include, but is not limited to, one or more of the following steps.
And carrying out optical proximity effect correction on the photoetching pattern contained in the integrated circuit design layout to obtain a first simulation pattern.
And correcting the first simulation graph based on the process of etching the first simulation graph to obtain a second simulation graph.
And correcting the second simulation graph based on the process of chemically and mechanically flattening the second simulation graph to obtain a third simulation graph.
And determining a plurality of graphic segments by segmenting and dividing the target line graphic contained in the third simulation graphic.
And predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments.
Further, the topographical feature comprises a minimum width.
The predicting whether the target line graph has the open circuit defect according to the morphological characteristics of all the graph segments comprises the following steps:
and determining that the target line pattern has an open defect according to the condition that the minimum width of any pattern segment is smaller than an open defect threshold.
Or determining that the target line pattern has no open defects according to the fact that the minimum widths of all the pattern segments are larger than or equal to the open defect threshold value.
Further, the determining that the target line pattern has the open defect according to the fact that the minimum width of any pattern segment is smaller than the open defect threshold value includes:
and determining the open circuit probability of the graph segment according to the fact that the minimum width of the graph segment is smaller than the open circuit defect threshold value.
And determining the open circuit probability of the target line graph according to the open circuit probability of the graph fragment.
Further, the correcting the first simulation pattern based on the process of etching the first simulation pattern includes:
and forming an etching deviation matrix group based on the simulation process of etching the first simulation graph, wherein the etching deviation matrix group is used for representing the profile change of the first simulation graph generated by etching.
And correcting the first simulation graph through the etching deviation matrix group.
Further, the determining the plurality of graphic segments by segmenting and dividing the target line graphic included in the third simulation graphic includes:
and traversing all the target line graphs contained in the third simulation graph.
And respectively removing the tail end of each target line graph.
And segmenting and dividing the target line graph with the tail end removed to obtain a plurality of graph segments.
Further, the topographical feature comprises edge roughness.
The predicting whether the target line graph has the open circuit defect according to the morphological characteristics of all the graph segments comprises the following steps:
and predicting whether the target line graph has open circuit defects according to the edge roughness of the two sides of all the graph segments.
Further, the target line pattern is a metal line pattern.
To achieve the above technical objective, the present invention discloses an apparatus for predicting open defects of an integrated circuit, which includes, but is not limited to, a pattern correction module, a first modification module, a second modification module, a pattern segmentation module, and a defect prediction module.
And the figure correction module is used for carrying out optical proximity effect correction on the photoetching figures contained in the integrated circuit design layout so as to obtain a first simulation figure.
And the first correction module is used for correcting the first simulation graph based on the process of etching the first simulation graph so as to obtain a second simulation graph.
And the second correction module is used for correcting the second simulation graph based on the process of chemically and mechanically flattening the second simulation graph to obtain a third simulation graph.
And the graph segmenting module is used for determining a plurality of graph segments in a manner of segmenting and dividing the target line graph contained in the third simulation graph.
And the defect prediction module is used for predicting whether the target line graph has open circuit defects according to the morphological characteristics of all the graph segments.
To achieve the above technical object, the present invention can also provide a computer device, which includes a memory and a processor, wherein the memory stores computer readable instructions, and the computer readable instructions, when executed by the processor, cause the processor to execute the steps of the method for predicting open defects of an integrated circuit according to any embodiment of the present invention.
To achieve the above technical objects, the present invention may also provide a storage medium storing computer readable instructions, which when executed by one or more processors, cause the one or more processors to perform the steps of the method for integrated circuit open defect prediction according to any one of the embodiments of the present invention.
The invention has the beneficial effects that:
the technical scheme for predicting the open circuit defect combines fluctuation factors of various processes such as optical proximity effect, etching, chemical mechanical planarization and the like, so that the method for predicting the open circuit defect of the integrated circuit resisting the process fluctuation can be provided, and the reliability of the integrated circuit is obviously improved.
The method can better predict the open circuit defect of the metal wire, can pre-treat the open circuit defect problem by adjusting a design layout and other modes before sheet throwing, greatly reduces the high cost caused by defect reworking in the sheet flowing process, improves the yield of an integrated circuit, and has wide application range.
Drawings
FIG. 1 is a flow diagram illustrating a method for integrated circuit open defect prediction in one or more embodiments of the invention.
FIG. 2 is a schematic diagram illustrating the change of the profile of the pattern after two corrections according to one or more embodiments of the invention.
FIG. 3 is a diagram illustrating segmentation of a target line graph in one or more embodiments of the invention.
Fig. 4 is a schematic block diagram of an apparatus for integrated circuit open defect prediction in one or more embodiments of the invention.
FIG. 5 is a schematic diagram illustrating the internal components of a computer device in one or more embodiments of the invention.
Detailed Description
The method, apparatus, computer device and medium for predicting open defects of an integrated circuit according to the present invention will be explained and explained in detail with reference to the drawings.
As shown in fig. 1, one or more embodiments of the invention may particularly provide a method for predicting an open defect of an integrated circuit, where the method for predicting an open defect includes, but is not limited to, one or more of the following steps.
In step 100, the invention first performs Optical Proximity Correction (OPC) on a lithographic pattern included in an integrated circuit design layout to obtain a first simulation pattern.
It should be understood that the lithographic pattern in the embodiments of the present invention is an exposed simulated pattern in the circuit design layout, which is consistent with the pattern formed after actual exposure. The invention can carry out photoetching target reset (target) on the integrated circuit design layout, and enter optical proximity effect correction.
As shown in fig. 2, in the embodiment of the present invention, a second simulation pattern is formed after the size of the first simulation pattern corrected based on etching is reduced, and the etched pattern profile of the second simulation pattern is consistent with the pattern profile formed after etching the real wafer or the related material layer formed on the wafer.
Optionally, the modifying the first simulation pattern based on the process of etching the first simulation pattern in the embodiment of the present invention includes: forming an etching deviation matrix group based on a simulation process of etching the first simulation graph, wherein the etching deviation matrix group is used for representing the profile change of the first simulation graph generated due to etching; and correcting the first simulation graph through the etching deviation matrix group, specifically, superposing the etching deviation matrix on the basis of the data of the first simulation graph. Preferably, the etching deviation matrix set is obtained by means of a lookup table (lookup table) based method, as shown in the lookup table below.
| F(W,S) | 100 | 110 | 120 | 130 |
| 40 | 18 | 17 | 16 | 16 |
| 50 | 18 | 17 | 16 | 15 |
| 60 | 19 | 18 | 17 | 17 |
| 70 | 19 | 18 | 17 | 17 |
| 80 | …… | …… | …… | …… |
| 90 | …… | …… | …… | …… |
Wherein, the etching deviation Bias is F (W, S), F represents a combination function, W represents Line Width, and S represents Space (pattern pitch); taking W60 and S110 as examples, the etching Bias is F (W, S) 18.
In general, the two effects of the aperture effect and the micro-loading effect are referred to as an etching proximity effect. In the etching process of the silicon substrate, the reaction gas can etch the side wall and the bottom of the pattern at the same time, so the etching proximity effect can cause the deviation of the size and the etching depth of the etched pattern at the same time. Based on the strong correlation between the two, the deviation on the etching depth is compensated for the correction of the graph size generally, so the domain correction of the etching proximity effect only aims at the etching graph size, and the etching depth factor is not considered. Therefore, the etching deviation on the basis of the method can also be a uniform value, and the mode of taking the uniform value as the etching deviation is taken as the parallel scheme of the etching deviation matrix group, so that the mode can further improve the running speed of the algorithm for realizing the method on the computer.
As shown in fig. 2, the second simulation pattern corrected by the chemical mechanical planarization of the present invention has a reduced size, and a third simulation pattern is formed, wherein the pattern profile of the third simulation pattern is identical to the pattern profile formed after the material layer on the chemical mechanical planarization wafer is planarized.
In step 400, a plurality of graphic segments (segments) are determined by segmenting the target line graph included in the third simulation graph. The target line pattern in the embodiment of the present invention may include, for example, but is not limited to, a metal line pattern.
Optionally, the length of one pattern segment in the embodiment of the present invention is less than or equal to 1 μm, so as to cover the main optical influence range. In addition, the lengths of the plurality of graphic segments may be the same or different in the embodiments of the present invention.
As shown in fig. 3, the determining the plurality of graphic segments by segmenting and dividing the target line graph included in the third simulation graph according to the embodiment may include: traversing all target Line graphs contained in the third simulation graph, and respectively removing tail ends (Line End) of all the target Line graphs, wherein one target Line graph of the invention usually has two tail ends; and then segmenting and dividing the target line graph with the tail end removed to obtain a plurality of graph segments.
The invention can help to improve the accuracy of subsequent measurement of the width and/or roughness of the target line pattern by removing the tail end part, and simultaneously can improve the running speed of the algorithm for realizing the invention in a computer.
And 500, predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments.
Optionally, the topographic feature in the embodiments of the present invention comprises a minimum width S of the graphic segmentminI.e. the minimum distance between the two sides of the graphics segment. According to all graphic segmentsThe method for predicting whether the target line graph has the open circuit defects by the topographic features comprises the following steps: according to the minimum width of any graphic segment being less than the open-circuit defect threshold dopenThe graph segments are indicated to have open circuit defects, and the open circuit defects of the target line graph are determined; or according to the minimum width of all the graphic segments being greater than or equal to the open defect threshold dopenAnd (5) showing that the pattern segment has no open circuit defect, and determining that the target line pattern has no open circuit defect.
Optionally, the determining that the target line pattern has the open defect according to the fact that the minimum width of any pattern segment is smaller than the open defect threshold value includes: determining the open-circuit probability of the graph segment according to the fact that the minimum width of the graph segment is smaller than the open-circuit defect threshold value, for example, determining the open-circuit probability through the functional relation between the minimum width of the graph segment and the open-circuit probability; the open probability of the target line graph where the graph segment is located is determined according to the open probability of the graph segment, and the maximum open probability of all the graph segments in the target line segment graph is used as the open probability of the current target line graph in the embodiment. For the metal wire line pattern, the open circuit probability of the metal wire can be determined.
Optionally, the topographic features in the embodiment of the present invention include Edge Roughness (LER), and specifically may include Roughness of two sides of the pattern segment: first roughness σLER1And a second roughness σLER2. Predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments comprises the following steps: and predicting whether the target line graph has open circuit defects according to the edge roughness of the two sides of all the graph segments. In some embodiments of the invention, the open-circuit probability can be calculated in a mathematical distribution mode on the basis of the edge roughness and the minimum width of the two sides, for example, the open-circuit probability is determined in a normal distribution analytic solution mode, so that the method is more suitable for predicting the open-circuit defects of the metal wires of the large-scale layout.
Optionally, some embodiments of the invention can determine the open probability P of the target line patternfailureAnd setting the early warning probability PopenAnd (6) comparing. If probability of open circuit PfailureLess than the set pre-warning probability PopenDescription of the inventionOpen circuit defects do not occur on the graph at a high probability, and the layout can not be modified or optimized under the general process requirement; if probability of open circuit PfailureGreater than or equal to the set early warning probability PopenIt is indicated that the layout has a very high probability of generating an open circuit problem, the layout can be modified by widening lines and the like, and the method can be executed again on a new design layout. The early warning probability can be set reasonably on the basis of the method, and the method is not limited by the method.
It should be understood that, based on the method for predicting open defects of an integrated circuit provided by the present invention, the technical idea of the present invention can also be used for predicting other defects or faults of the integrated circuit, such as bridging defects.
As shown in fig. 4, the present invention can also provide an apparatus for predicting an open defect of an integrated circuit, based on the same inventive concept as the method for predicting an open defect of an integrated circuit according to the present invention.
The defect prediction apparatus in the embodiment of the present invention may include, but is not limited to, a pattern correction module, a first modification module, a second modification module, a pattern segmentation module, and a defect prediction module, which are described in detail below.
The pattern correction module can be used for carrying out optical proximity effect correction on photoetching patterns contained in the integrated circuit design layout so as to obtain and output a first simulation pattern.
The first correction module can be used for correcting the first simulation graph based on the process of etching the first simulation graph to obtain a second simulation graph.
Optionally, the first correction module may be configured to form an etching deviation matrix group based on a simulation process of etching the first simulation pattern, and to correct the first simulation pattern by the etching deviation matrix group; wherein the etching deviation matrix group is used for representing the profile change of the first simulation graph generated by etching.
The second correction module can be used for correcting the second simulation graph based on the process of processing the second simulation graph by chemical mechanical planarization so as to obtain a third simulation graph.
The graph segmentation module can be used for determining a plurality of graph segments by segmenting and dividing the target line graph contained in the third simulation graph. Specifically, the graph segmenting module is configured to traverse all the target line graphs included in the third simulation graph, remove the tail ends of the target line graphs respectively, and segment and divide the target line graph with the tail end removed to obtain a plurality of graph segments. The target line pattern in one or more embodiments of the present invention is a metal line pattern.
The defect prediction module is used for predicting whether the target line graph has open circuit defects according to the morphological characteristics of all the graph segments.
Alternatively, topographical features in the present invention include, but are not limited to, minimum widths. The defect prediction module in this embodiment may be configured to determine that the target line pattern has an open defect according to whether the minimum width of any pattern segment is smaller than an open defect threshold; or the defect prediction module is used for determining that the target line graph has no open defects according to the condition that the minimum widths of all the graph segments are greater than or equal to the open defect threshold. Preferably, the defect prediction module can be configured to determine an open probability of the pattern segment according to the minimum width of the pattern segment being less than the open defect threshold, and determine an open probability of the target line pattern according to the open probability of the pattern segment.
Optionally, the topographical features of the present invention include, but are not limited to, edge roughness. The defect prediction module in this embodiment may be configured to predict whether an open defect exists in the target line pattern according to the edge roughness of the two sides of all the pattern segments.
As shown in fig. 5, one or more embodiments of the invention can provide a computer device including a memory and a processor, the memory having stored therein computer readable instructions which, when executed by the processor, cause the processor to perform the steps of the method for integrated circuit open defect prediction in any of the embodiments of the invention. The method for predicting the open circuit defect of the integrated circuit in the invention comprises but is not limited to the following steps: step 100, performing optical proximity correction on the lithography pattern included in the integrated circuit design layout to obtain a first simulation pattern. Step 200, correcting the first simulation graph based on the process of etching the first simulation graph to obtain a second simulation graph. Optionally, the modifying the first simulation pattern based on the process of etching the first simulation pattern in the embodiment of the present invention includes: forming an etching deviation matrix group based on a simulation process of etching the first simulation graph, wherein the etching deviation matrix group is used for expressing the profile change of the first simulation graph generated by etching; the first simulation pattern is corrected by etching the bias matrix set. And 300, correcting the second simulation graph based on the process of chemically mechanical planarization processing the second simulation graph to obtain a third simulation graph. Step 400, determining a plurality of graphic segments by segmenting the target line graphic contained in the third simulation graphic. The target line pattern in the embodiment of the invention is a metal line pattern. Optionally, determining the plurality of graphic segments by segmenting and dividing the target line graphic included in the third simulation graphic includes: traversing all target line graphs contained in the third simulation graph, and respectively removing the tail ends of all the target line graphs; and segmenting and dividing the target line graph with the tail end removed to obtain a plurality of graph segments. And 500, predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments. Optionally, the topographical feature in embodiments of the present invention comprises a minimum width. Predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments comprises the following steps: determining that the target line pattern has an open defect according to the fact that the minimum width of any pattern segment is smaller than an open defect threshold; or determining that the target line pattern has no open defects according to the condition that the minimum widths of all the pattern segments are greater than or equal to the open defect threshold. Optionally, determining that the target line pattern has the open defect according to that the minimum width of any pattern segment is smaller than the open defect threshold includes: and determining the open-circuit probability of the graph fragment according to the fact that the minimum width of the graph fragment is smaller than the open-circuit defect threshold value, and determining the open-circuit probability of the target line graph according to the open-circuit probability of the graph fragment. Optionally, the topographical features in embodiments of the present invention comprise edge roughness. Predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments comprises the following steps: and predicting whether the target line graph has open circuit defects according to the edge roughness of the two sides of all the graph segments.
As shown in fig. 5, a storage medium having stored thereon computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the method for integrated circuit open defect prediction in any of the embodiments of the present invention. The method for predicting the open circuit defect of the integrated circuit in the invention comprises but is not limited to the following steps: step 100, performing optical proximity correction on the lithography pattern included in the integrated circuit design layout to obtain a first simulation pattern. Step 200, correcting the first simulation graph based on the process of etching the first simulation graph to obtain a second simulation graph. Optionally, the modifying the first simulation pattern based on the process of etching the first simulation pattern in the embodiment of the present invention includes: forming an etching deviation matrix group based on a simulation process of etching the first simulation graph, wherein the etching deviation matrix group is used for expressing the profile change of the first simulation graph generated by etching; the first simulation pattern is corrected by etching the bias matrix set. And 300, correcting the second simulation graph based on the process of chemically mechanical planarization processing the second simulation graph to obtain a third simulation graph. Step 400, determining a plurality of graphic segments by segmenting the target line graphic contained in the third simulation graphic. The target line pattern in the embodiment of the invention is a metal line pattern. Optionally, determining the plurality of graphic segments by segmenting and dividing the target line graphic included in the third simulation graphic includes: traversing all target line graphs contained in the third simulation graph, and respectively removing the tail ends of all the target line graphs; and segmenting and dividing the target line graph with the tail end removed to obtain a plurality of graph segments. And 500, predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments. Optionally, the topographical feature in embodiments of the present invention comprises a minimum width. Predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments comprises the following steps: determining that the target line pattern has an open defect according to the fact that the minimum width of any pattern segment is smaller than an open defect threshold; or determining that the target line pattern has no open defects according to the condition that the minimum widths of all the pattern segments are greater than or equal to the open defect threshold. Optionally, determining that the target line pattern has the open defect according to that the minimum width of any pattern segment is smaller than the open defect threshold includes: and determining the open-circuit probability of the graph fragment according to the fact that the minimum width of the graph fragment is smaller than the open-circuit defect threshold value, and determining the open-circuit probability of the target line graph according to the open-circuit probability of the graph fragment. Optionally, the topographical features in embodiments of the present invention comprise edge roughness. Predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all the graph segments comprises the following steps: and predicting whether the target line graph has open circuit defects according to the edge roughness of the two sides of all the graph segments.
Obviously, compared with a complex open circuit probability calculation scheme (based on the Monte Carlo principle, for example), the method has the outstanding advantages of higher operation speed, higher calculation efficiency, suitability for large-scale or ultra-large-scale integrated circuit design and the like. Therefore, the invention can meet the requirement of mass production and has wide application range.
The logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable storage medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer cartridge (magnetic device), a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM-Only Memory, or flash Memory), an optical fiber device, and a portable Compact Disc Read-Only Memory (CDROM). Additionally, the computer-readable storage medium may even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic Gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic Gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "the present embodiment," "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and simplifications made in the spirit of the present invention are intended to be included in the scope of the present invention.
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