CN113582130B

CN113582130B - Method for preparing MEMS device based on wafer

Info

Publication number: CN113582130B
Application number: CN202110851379.7A
Authority: CN
Inventors: 林欣蓉; 徐泽洋; 刘双娟
Original assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Current assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Priority date: 2021-07-27
Filing date: 2021-07-27
Publication date: 2024-01-05
Anticipated expiration: 2041-07-27
Also published as: CN113582130A

Abstract

The invention provides a method for preparing an MEMS device based on a wafer. By further arranging the protective layer between the mask layer and the second surface of the wafer, the protective layer can be used for protecting the wafer from being attacked by xenon fluoride after the mask layer is consumed, so that the edge of the wafer is prevented from being exposed prematurely and being corroded by the xenon fluoride, the integrity of MEMS devices positioned at the edge of the wafer is effectively ensured, and the yield of MEMS devices on the wafer is improved.

Description

Method for preparing MEMS device based on wafer

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for preparing an MEMS device based on a wafer.

Background

Wafer-based device processing is a common process in the semiconductor arts, such as performing MEMS device processing on a wafer basis. In the wafer processing process for the MEMS device, multiple etching processes are often required to be performed to form the cavity and the back cavity of the MEMS device, however, in each etching process, a larger etching attack is also particularly easy to be caused on the edge of the wafer, so that the edge of the wafer is easily damaged, and at the moment, the MEMS device at the edge of the wafer is correspondingly influenced, so that the yield of the MEMS device in the wafer is greatly influenced.

Disclosure of Invention

The invention aims to provide a method for preparing an MEMS device based on a wafer, which aims to solve the problem that the edge of the wafer is easily damaged in the existing preparation process.

In order to solve the technical problems, the invention provides a method for preparing an MEMS device based on a wafer, which comprises the following steps: providing a wafer, defining a plurality of device areas on the wafer, sequentially forming a first sacrificial layer, a vibrating membrane, a second sacrificial layer and a back electrode plate on the first surface of the wafer of at least part of the device areas, and further arranging a polycrystalline silicon blocking layer between the first sacrificial layer and the vibrating membrane; forming a protective layer and a mask layer on the second surface of the wafer of at least part of the device region, wherein the mask layer covers the protective layer and defines a back cavity region of the MEMS device, and etching the wafer by taking the mask layer as a mask to form a back cavity, and the back cavity exposes the first sacrificial layer; executing a first sacrificial layer release process to remove the exposed first sacrificial layer and further expose the polysilicon barrier layer; etching the polysilicon barrier layer by using etching gas containing xenon fluoride, and completely consuming the mask layer by the etching gas containing xenon fluoride and exposing the protective layer; a second sacrificial layer release process is performed to at least partially remove the second sacrificial layer and also remove the protective layer.

In the method for manufacturing the MEMS device based on the wafer, provided by the invention, a protective layer is arranged between the mask layer and the second surface of the wafer, and the protective layer can be kept after the mask layer is consumed for protecting the wafer from etching attack of xenon fluoride gas. In particular, in the present invention, the protection layer is laid on the mask layer to allow the mask layer to be consumed in a large amount at the wafer edge, so that the problem that the mask layer is consumed in a large amount at the wafer edge due to the poor etching uniformity of the previous etching process (for example, the first sacrificial layer release process) is solved, and the wafer can be prevented from being exposed prematurely and being corroded by xenon fluoride gas. Therefore, the integrity of the MEMS device at the edge of the wafer is guaranteed, and the yield of the MEMS device on the wafer is improved.

Drawings

Fig. 1-4 are schematic structural diagrams of a wafer-based MEMS device fabrication process.

Fig. 5 is a flow chart of a method of fabricating a MEMS device based on a wafer in an embodiment of the invention.

Fig. 6-10 are schematic structural diagrams of a wafer-based MEMS device in accordance with an embodiment of the present invention.

Wherein, the reference numerals are as follows: 10/100-wafer; 20/200-diaphragm; 210-a first insulating layer; 220-a first conductive layer; 230-a second insulating layer; 30/300-back plate; 310-a second conductive layer; 320-a third insulating layer; 400-a protective layer; 51/510-a first sacrificial layer; 52/520-a second sacrificial layer; 60/600-mask layer; 70-a barrier layer; 710—a first barrier layer; 720-a second barrier layer; 730-third barrier layer.

Detailed Description

As described in the background, when MEMS devices are currently fabricated on a wafer, there is often a significant loss on the edge of the wafer, which affects the performance of the MEMS devices at the edge of the wafer. A specific example of the damage to the edge of a wafer during processing is explained below, for example with reference to fig. 1-4.

Referring first to fig. 1, a wafer 10 is provided, and a first sacrificial layer 51, a diaphragm 20, a second sacrificial layer 52, and a back plate 30 are sequentially formed on a first surface of at least a portion of a device region of the wafer 10.

With continued reference to fig. 1, a mask layer 60 is formed on the second surface of the wafer 10, the mask layer 60 defining a back cavity region in the device region. And etching the wafer 10 from the back surface of the wafer 10 by using the mask layer 60 as a mask to form a back cavity, wherein the back cavity exposes the first sacrificial layer 51.

Next, referring to fig. 2, a first sacrificial layer release process is performed to remove the first sacrificial layer 51. As shown in fig. 2, a barrier layer 70 is further provided between the first sacrificial layer 51 and the diaphragm 20 for preventing the diaphragm 20 from being eroded when the first sacrificial layer 51 is etched. Thus, after the first sacrificial layer 51 is removed, the barrier layer 70 is exposed.

It should be noted that, in the first sacrificial layer release process, the etching agent may also attack the mask layer 60 in a small amount, and in the case where the first sacrificial layer release process has poor etching uniformity, uneven consumption of the mask layer 60 may occur. In particular, the edge region of the wafer 10 is typically subjected to a stronger etching attack, which results in greater consumption of the mask layer 60 at the edge region of the wafer.

Referring next to fig. 3, the barrier layer 70 is removed using an etching gas containing xenon fluoride. The etching process superimposes the loss on the mask layer 60, and the edge region of the wafer is exposed to the wafer 10 too early, so that the exposed wafer 10 is largely eroded by the etching gas containing xenon fluoride, and the bottom corner of the wafer edge is missing to form a pit.

Next, referring to fig. 4, a second sacrificial layer release process is performed to remove the second sacrificial layer 52 between the diaphragm 20 and the back plate 30, so that the diaphragm 20 can be released to realize its vibration function.

It should be appreciated that the etchant in the second sacrificial layer release process tends to accumulate in the pits at the bottom corner of the wafer edge, thereby exacerbating the problem of missing bottom corners of the wafer edge, which can correspondingly affect the MEMS device at the edge location.

Therefore, the invention provides an improvement scheme to avoid the edge of the wafer from being corroded to influence the device yield of the edge position. Referring specifically to fig. 5, the method for preparing a MEMS device based on a wafer according to the present invention includes the following steps.

Step S100, a wafer is provided, a first sacrificial layer, a vibrating membrane, a second sacrificial layer and a back electrode plate are sequentially formed on the first surface of the wafer of at least part of the device area, and a polycrystalline silicon blocking layer is further arranged between the first sacrificial layer and the vibrating membrane.

And step 200, forming a protective layer and a mask layer on the second surface of the wafer of at least part of the device region, wherein the mask layer covers the protective layer and defines a back cavity region of the MEMS device, etching the wafer by taking the mask layer as a mask to form a back cavity, and exposing the first sacrificial layer.

Step S300, performing a first sacrificial layer release process to remove the exposed first sacrificial layer and further expose the polysilicon barrier layer.

In step S400, the polysilicon barrier layer is etched by using an etching gas containing xenon fluoride, and the etching gas containing xenon fluoride also completely consumes the mask layer and exposes the protective layer.

Step S500, performing a second sacrificial layer release process to at least partially remove the second sacrificial layer and also remove the protective layer.

The method of fabricating a MEMS device based on a wafer according to the present invention is described in further detail below with reference to fig. 6-10 and the specific examples. 6-10 are schematic structural diagrams of a wafer-based MEMS device in accordance with an embodiment of the present invention, it being understood that the edge portions of the wafer are shown only schematically. It should also be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. And relative terms such as "above," "below," "top," "bottom," "over" and "under" as illustrated in the accompanying drawings may be used to describe various elements' relationship to one another. These relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the figures. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element, for example, will now be below the element.

In step S100, referring specifically to fig. 6, a wafer 100 is provided, and a plurality of device regions are defined on the wafer 100, and at least part of the plurality of device regions are used to form MEMS devices. The wafer 100 is, for example, a silicon wafer. And, the MEMS device may specifically be a MEMS microphone device.

With continued reference to fig. 6, in at least a portion of the device region, a first sacrificial layer 510, a diaphragm 200, a second sacrificial layer 520, and a back plate 300 are sequentially formed on the first surface of the wafer 100. Wherein, the first sacrificial layer 110 and the second sacrificial layer 520 are removed in a subsequent process to release a vibration space of the diaphragm 200. And, the materials of the first sacrificial layer 510 and the second sacrificial layer 520 may each include silicon oxide. Further, the diaphragm 200 may specifically include a first conductive layer 220, and a first insulating layer 210 and a second insulating layer 230 disposed on upper and lower sides of the first conductive layer 220. The material of the first conductive layer 220 may include polysilicon, and the material of the first insulating layer 210 and the second insulating layer 230 may include silicon nitride. And, the back plate 300 includes a second conductive layer 310 and a third insulating layer 320, the third insulating layer 320 being located at a side of the second conductive layer 310 adjacent to the second sacrificial layer 520. The material of the second conductive layer 310 of the back electrode plate 300 may also include polysilicon, and the material of the third insulating layer 320 may include silicon nitride.

With continued reference to fig. 6, the end of the diaphragm 200 is further formed with a support member penetrating the first sacrificial layer 510 to be abutted to the first surface of the wafer 100 for supporting the diaphragm 200 after releasing the first sacrificial layer 510. In this embodiment, the end of the diaphragm 200 is bent toward the wafer 100 to penetrate the first sacrificial layer 510 and abut against the surface of the film layer under the first sacrificial layer 510.

Similar to the diaphragm 200, the end of the back plate 300 is also formed with a support, and the support of the back plate 300 penetrates the second sacrificial layer 520 to abut on the surface of the diaphragm 200 for supporting the back plate 300 after releasing the second sacrificial layer 520. In this embodiment, the end portion of the back plate 300 is bent toward the direction of the diaphragm 200 to penetrate the second sacrificial layer 520 and abut against the surface of the film layer below the second sacrificial layer 520. The back plate 300 is bent to the support of the diaphragm 200, and the third insulating layer 320 of the back plate 300 contacts the second insulating layer 230 of the diaphragm 200, so that the problem of electrical connection between the back plate 300 and the diaphragm 200 can be avoided.

Further, a first barrier layer 710 is further formed between the first surface of the wafer 100 and the first sacrificial layer 510, and the first barrier layer 710 may implement an etching barrier when etching the wafer 100 to form a back cavity. Wherein the material of the first blocking layer 710 may include silicon nitride.

Further, a second barrier layer 720 is further formed between the first sacrificial layer 510 and the diaphragm 200, and the second barrier layer 720 can realize etching barrier during the etching of the first sacrificial layer 510. In this embodiment, the second blocking layer 720 is formed at least in the area of the back cavity. And, the second barrier layer 720 is specifically a polysilicon barrier layer (i.e., the second barrier layer 720 of polysilicon material), so that a larger etching selectivity can be achieved when the first sacrificial layer 510 is etched with a solution containing hydrofluoric acid.

In this embodiment, a third barrier layer 730 (for example, a silicon oxide barrier layer) is further formed between the second barrier layer 720 and the diaphragm 200, and the third barrier layer 730 is used for isolating and protecting the diaphragm 200 when the second barrier layer 720 is removed. As described above, when the second barrier layer 720 is formed using a polysilicon material, although a larger etching selectivity is achieved with the first sacrificial layer 510 of a silicon oxide material, the first insulating layer 210 of a silicon nitride material is generally damaged when the second barrier layer 720 is etched and removed (e.g., when the polysilicon material is etched using xenon fluoride gas, the silicon nitride material is also consumed at the same time), and thus the third barrier layer 730 is provided in this embodiment. The material of the third barrier layer 730 may be the same as that of the second sacrificial layer 520, so that the third barrier layer 730 is removed simultaneously with the removal of the second sacrificial layer 520.

In a specific embodiment, the third barrier layer 730 is also formed at least in the area of the back cavity, and the third barrier layer 730 also covers the sidewall of the second barrier layer 720, so that the sidewall of the second barrier layer 720 is also isolated from the diaphragm 200.

In addition, the thickness of the second barrier layer 720 and the third barrier layer 730 is much smaller than the thickness of the first sacrificial layer 510, so that only a small amount of etching is required to remove the second barrier layer 720 and the third barrier layer 730. For example, the second barrier layer 720 has a thickness of 1000 to 1500 angstroms and the third barrier layer 730 has a thickness of 500 to 1000 angstroms.

In step S200, as shown in fig. 6 and 7, a protection layer 400 and a mask layer 600 are formed on the second surface of the wafer in the at least part of the device region, the mask layer 600 covers the protection layer 400 and defines a back cavity region of the MEMS device, and then the wafer is etched with the mask layer 600 as a mask to form a back cavity, where the back cavity exposes the first sacrificial layer 510. Wherein the material of the mask layer 600 includes silicon nitride.

It should be noted that, the protection layer 400 may be used to stop etching at the protection layer 400 along with consumption of the mask layer 600 when performing the subsequent xenon fluoride etching, so as to avoid the wafer 100 from being exposed in advance and being eroded by the xenon fluoride etchant. Based on this, the material of the protection layer 400 may be selected according to the etching rate of xenon fluoride, and in this embodiment, the material of the mask layer 600 may include silicon nitride, and the material of the protection layer 400 includes silicon oxide.

Specifically, the protective layer 400 is correspondingly provided with an opening area, and the range of the opening area is greater than or equal to the range of the back cavity area. For example, when the opening area of the protection layer 400 is formed by etching under a mask based on the mask layer 600, the range of the opening area of the protection layer 400 corresponds to the range of the back cavity area; alternatively, the opening area of the protection layer 400 is formed prior to the mask layer 600, so that the opening area of the protection layer 400 may be larger than the range of the back cavity area (i.e., the boundary of the opening area of the protection layer 400 is extended by a predetermined distance with respect to the boundary of the back cavity area), and thus, when the patterned mask layer 600 is formed later, the mask layer 600 may further cover the opening sidewall of the protection layer 400. Wherein the boundary of the opening area of the protection layer 400 may be expanded by about 4 μm to 5 μm with respect to the boundary of the back cavity area, on one hand, considering the alignment offset existing in the photolithography process, and on the other hand, ensuring that the mask layer 600 does not cause the defined back cavity area to shrink when covering the opening sidewall of the protection layer 400.

Referring next to fig. 7, a process of etching the wafer 100 using the mask layer 600 as a mask to form a back cavity includes, for example: first, the exposed silicon wafer may be etched using a plasma etching process and the etching is stopped at the first barrier layer 710; the exposed first barrier layer 710 is then etched to further expose the first sacrificial layer 510. Note that the first blocking layer 710 is formed using a silicon nitride material, and thus the mask layer 600 of the silicon nitride material is also consumed in a small amount when the first blocking layer 710 is etched.

Since the first barrier layer 710 of silicon nitride material and the first sacrificial layer 510 of silicon oxide material have a large etching selectivity when etching the first barrier layer 710, the exposed first sacrificial layer 510 can be prevented from being consumed in a large amount, and the problem that the etching amount is difficult to control when removing the first sacrificial layer 510 later can be prevented.

In step S300, referring specifically to fig. 8, a first sacrificial layer release process is performed to remove the exposed first sacrificial layer 510 and further expose the second barrier layer 720 (i.e., the polysilicon barrier layer). In this embodiment, at least the first sacrificial layer corresponding to the back cavity region is removed.

Specifically, the material of the first sacrificial layer 510 includes silicon oxide, and the first sacrificial layer release process may be a wet etching process (e.g., buffer oxide etching solution BOE) using a solution containing hydrofluoric acid, that is, the first sacrificial layer 510 is wet etched using an etching solution containing hydrofluoric acid. However, the etching solution containing hydrofluoric acid may generally consume the mask layer 600 (e.g., may attack the mask layer of the silicon nitride material) while etching the first sacrificial layer 510, and particularly, the edge position of the wafer 100 may be more easily attacked by the etching solution, so that the mask layer 600 at the edge position of the wafer may be consumed more. That is, the mask layer 600 consumes more power in the edge region of the wafer than in the middle region of the wafer.

In step S400, referring specifically to fig. 9, the second barrier layer 720 (i.e., the polysilicon barrier layer) is etched using an etching gas containing xenon fluoride (XeF), and the etching gas containing xenon fluoride also completely consumes the mask layer 600 and exposes the protective layer 400.

In this embodiment, the polysilicon barrier layer is etched and the etching is stopped at the third barrier layer 730. And, the etching gas containing xenon may also consume the remaining mask layer 600 (e.g., the mask layer of silicon nitride material) at the same time, so that the protection layer 400 is exposed, at this time, since the etching selectivity of the etching gas containing xenon to the mask layer 600 (e.g., the silicon nitride material) and the protection layer 400 (e.g., the silicon oxide material) is greater than or equal to 200:1, the protection layer 400 can still be retained on the second surface of the wafer 100. Of course, the etching gas containing xenon fluoride also has a larger etching selectivity to silicon oxide material and silicon material, so that the protective layer 400 of silicon oxide material can better isolate and protect the silicon wafer.

That is, although the mask layer 600 is consumed (particularly, the mask layer 600 at the edge of the wafer is consumed earlier) by the first sacrificial layer release process and the etching gas containing xenon fluoride, the silicon wafer is not exposed after the complete consumption, and the problem that the etching gas containing xenon fluoride further erodes the silicon wafer is avoided.

In addition, it should be noted that, in the present embodiment, the mask layer 600 also covers the opening sidewall of the protection layer 400, where the portion of the mask layer 600 covering the opening sidewall generally has the maximum thickness in the thickness direction of the wafer, so that when the second mask layer 600 is removed by the second etching process, the mask material is generally consumed at the position of the opening sidewall. That is, the silicon wafer exposed from the opening sidewall of the protection layer 400 is generally exposed at or near the etching end point, and thus the exposed silicon wafer is not consumed.

In step S500, referring specifically to fig. 10, a second sacrificial layer release process is performed to at least partially remove the second sacrificial layer 520 between the diaphragm 200 and the back plate 300, and also remove the protective layer 400.

Specifically, a plurality of openings are formed in the back plate 300, and the openings are exposed to the second sacrificial layer 520, so that an etchant can etch the second sacrificial layer 520 through the openings in the second sacrificial layer release process. The openings in the back plate 300 may be prepared before etching the wafer to form the back cavity, and the back plate 300 may be covered and protected during the process of etching the wafer 100, the first barrier layer 710, the first sacrificial layer 510, and the second barrier layer 720 in sequence.

The second sacrificial layer release process is specifically a dry etching process (VHF) adopting hydrogen fluoride-containing gas. The dry etching process used in this embodiment is advantageous in overcoming the difficulty in removing the etching residues, compared to removing the second sacrificial layer 520 by using a wet etching process.

Further, the second sacrificial layer 520 may be made of the same material as the protective layer 400, i.e., may include silicon oxide, so that the second sacrificial layer 520 and the protective layer 400 may be removed simultaneously in the second sacrificial layer release process. In addition, the material of the third barrier layer 730 may also include silicon oxide, so the third barrier layer 730 may also be removed simultaneously in the second sacrificial layer release process to release the diaphragm 200.

With continued reference to fig. 10, for the device region for forming the MEMS device, portions of the first sacrificial layer 510 and the second sacrificial layer 520 corresponding to the back cavity region are removed, and portions of the first sacrificial layer 510 and the second sacrificial layer 520 located at the outer periphery of the back cavity may be reserved for auxiliary support of the diaphragm 200 and the back plate 300.

In summary, in the method for manufacturing the MEMS device based on the wafer as described above, even if the previous etching process (for example, the first sacrificial layer release process) before performing the xenon fluoride etching may wear the mask layer on the second surface of the wafer, especially, uneven wear may occur on the mask layer 600, so that the mask layer 600 may be consumed prematurely at the edge of the wafer, and at this time, the wafer may not be exposed prematurely due to the protection layer, so that a large amount of consumption of the xenon fluoride etching gas for the wafer is realized. In addition, the protection layer can be removed simultaneously in the second sacrificial layer release process, and the process is simple.

It should be noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.

It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method of fabricating a MEMS device based on a wafer, comprising:

providing a wafer, defining a plurality of device areas on the wafer, sequentially forming a first sacrificial layer, a vibrating membrane, a second sacrificial layer and a back electrode plate on the first surface of the wafer of at least part of the device areas, and further arranging a polycrystalline silicon blocking layer between the first sacrificial layer and the vibrating membrane;

forming a protective layer and a mask layer on the second surface of the wafer of at least part of the device region, wherein the mask layer covers the protective layer and defines a back cavity region of the MEMS device, the protective layer is formed before the mask layer, so that the mask layer also covers the side wall of the protective layer, which is close to the back cavity region, and etching the wafer by taking the mask layer as a mask to form a back cavity, and the back cavity exposes the first sacrificial layer;

executing a first sacrificial layer release process to remove the exposed first sacrificial layer and further expose the polysilicon barrier layer;

etching the polysilicon barrier layer by using etching gas containing xenon fluoride, and completely consuming the mask layer by the etching gas containing xenon fluoride and exposing the protective layer;

a second sacrificial layer release process is performed to at least partially remove the second sacrificial layer and also remove the protective layer.

2. The method of fabricating a MEMS device on a wafer of claim 1, wherein the first sacrificial layer release process is a wet etching process using a solution containing hydrofluoric acid.

3. The method of fabricating a MEMS device on a wafer of claim 2, wherein the material of the mask layer comprises silicon nitride, and the mask layer is also partially consumed during the first sacrificial layer release process, and the mask layer is consumed more at the edge region of the wafer than at the middle region of the wafer.

4. The method of claim 1, wherein the etching selectivity of the xenon fluoride-containing etching gas to the mask layer and the protective layer is greater than or equal to 200:1.

5. The method of fabricating a MEMS device on a wafer of claim 4, wherein the material of the mask layer comprises silicon nitride and the material of the protective layer comprises silicon oxide.

6. The method of fabricating a MEMS device on a wafer of claim 1, wherein the second sacrificial layer release process is a dry etching process using a hydrogen fluoride containing gas.

7. The method of fabricating a MEMS device on a wafer of claim 1, wherein the material of the second sacrificial layer comprises silicon oxide, and a silicon oxide barrier layer is further formed between the polysilicon barrier layer and the diaphragm;

and removing the silicon oxide barrier layer in the second sacrificial layer release process at the same time.

8. The method of fabricating a MEMS device based on a wafer of claim 7, wherein the polysilicon barrier layer is formed within the back cavity region, the silicon oxide barrier layer covering the polysilicon barrier layer proximate a top surface of the diaphragm and also covering sidewalls of the polysilicon barrier layer.

9. The method of fabricating a MEMS device on a wafer of claim 1, wherein the polysilicon barrier layer has a thickness of 1000 angstroms to 1500 angstroms.

10. The method of preparing a MEMS device based on a wafer of claim 1, wherein the MEMS device comprises a MEMS microphone.