CN113571570B - Display panel and display device - Google Patents
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- CN113571570B CN113571570B CN202110863579.4A CN202110863579A CN113571570B CN 113571570 B CN113571570 B CN 113571570B CN 202110863579 A CN202110863579 A CN 202110863579A CN 113571570 B CN113571570 B CN 113571570B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
- H10K59/65—OLEDs integrated with inorganic image sensors
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- Inorganic Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The application discloses a display panel and a display device. The display panel has a display area and a functional area adjacent to each other, and the display panel includes: a substrate; the driving device layer comprises a semiconductor layer, a gate insulating layer and a gate metal layer which are arranged in a stacked manner, wherein the semiconductor layer is positioned on one side of the substrate, the gate insulating layer is positioned on one side of the semiconductor layer, which is back to the substrate, and the gate metal layer is positioned on one side of the gate insulating layer, which is back to the substrate; and the connecting wires are used for connecting the two signal wires which are separated by the functional area and transmit the same signal, or the connecting wires are used for connecting the pixel circuits arranged in the display area and the light-emitting elements arranged in the functional area, and at least part of the connecting wires are positioned on one side of the grid metal layer facing the substrate. According to the embodiment of the application, the display effect can be improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
With the rapid development of electronic devices, users have increasingly higher requirements on screen occupation ratios, and technologies such as under-screen cameras, perforated screens and the like have been developed. For technologies such as under-screen cameras and perforated screens, signal wires around a camera area or an open area need to be connected in a one-to-one correspondence manner by using wires, or light-emitting elements in the camera area need to be connected with pixel circuits outside the camera area by using wires, so that the wiring density of a display area provided with wires is different from that of other display areas, and the display effect is affected.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which can improve the display effect.
In a first aspect, an embodiment of the present application provides a display panel having a display area and a functional area that are adjacent, the display panel including: a substrate; the driving device layer comprises a semiconductor layer, a gate insulating layer and a gate metal layer which are arranged in a stacked manner, wherein the semiconductor layer is positioned on one side of the substrate, the gate insulating layer is positioned on one side of the semiconductor layer, which is back to the substrate, and the gate metal layer is positioned on one side of the gate insulating layer, which is back to the substrate; and the connecting wires are used for connecting the two signal wires which are separated by the functional area and transmit the same signal, or the connecting wires are used for connecting the pixel circuits arranged in the display area and the light-emitting elements arranged in the functional area, and at least part of the connecting wires are positioned on one side of the grid metal layer facing the substrate.
In a possible implementation manner of the first aspect, at least part of the plurality of connection lines is located between the semiconductor layer and the gate metal layer;
Preferably, the connection line is used to connect the pixel circuit disposed in the display region and the light emitting element disposed in the functional region, and the connection line is directly connected in contact with the source region or the drain region of the active layer of at least one transistor of the pixel circuit.
In a possible implementation manner of the first aspect, at least part of the plurality of connection lines is located between the semiconductor layer and the substrate;
preferably, in the case where the connection line connects the pixel circuit provided in the display region and the light emitting element provided in the functional region, the connection line is directly in contact with and connected to a source region or a drain region of an active layer of at least one transistor of the pixel circuit;
or a buffer layer is arranged between the connecting line and the semiconductor layer, and the connecting line is connected with the source region or the drain region of the active layer of at least one transistor of the pixel circuit through a via hole under the condition that the connecting line is used for connecting the pixel circuit arranged in the display region and the light-emitting element arranged in the functional region.
In a possible implementation manner of the first aspect, a buffer layer is disposed between the connection line and the semiconductor layer, and an orthographic projection of the connection line on the substrate at least partially overlaps with an orthographic projection of a channel region of an active layer of at least one transistor of the pixel circuit on the substrate.
In a possible implementation manner of the first aspect, the display area includes a main display area and a transitional display area, the transitional display area surrounds at least part of the functional area, the functional area is a light-transmitting display area, the functional area includes a first light-emitting element, the transitional display area includes a first pixel circuit, and the connection line is used for connecting the first light-emitting element and the first pixel circuit;
The transitional display area further comprises a second light-emitting element and a second pixel circuit for driving the second light-emitting element, the main display area further comprises a third light-emitting element and a third pixel circuit for driving the third light-emitting element, the orthographic projection area of the first pixel circuit on the substrate is smaller than the orthographic projection area of the third pixel circuit on the substrate, and/or the orthographic projection area of the second pixel circuit on the substrate is smaller than the orthographic projection area of the third pixel circuit on the substrate, or the orthographic projection areas of the first pixel circuit, the second pixel circuit and the third pixel circuit on the substrate are the same.
In a possible implementation manner of the first aspect, the display area includes a main display area and a winding display area that are adjacent to each other, and the winding display area surrounds at least a part of the functional area, and the display panel further includes:
a plurality of signal lines, each signal line being electrically connected to a pixel circuit provided in the display region and extending in a first direction, the plurality of signal lines including a plurality of first-type signal lines and a plurality of second-type signal lines, each second-type signal line including a first section and a second section separated by the functional region;
the connecting wire is used for connecting the first section and the second section, and at least part of the connecting wire is positioned in the winding display area.
In a possible implementation manner of the first aspect, the first direction is a column direction, and the signal line is a data signal line;
Or the first direction is a row direction, and the signal line is a scanning signal line or a light-emitting control signal line or a reference voltage signal line.
In a possible implementation manner of the first aspect, the display area includes a main display area and a secondary display area that are adjacent, and the functional area is adjacent to the secondary display area;
The functional area comprises a grid driving circuit and a fourth light-emitting element, the auxiliary display area comprises a fourth pixel circuit, and a connecting wire is used for connecting the fourth light-emitting element and the fourth pixel circuit;
Preferably, the auxiliary display area further includes a fifth light emitting element and a fifth pixel circuit for driving the fifth light emitting element, the main display area further includes a third light emitting element and a third pixel circuit for driving the third light emitting element, a forward projection area of the fourth pixel circuit on the substrate is smaller than a forward projection area of the third pixel circuit on the substrate, and/or a forward projection area of the fifth pixel circuit on the substrate is smaller than a forward projection area of the third pixel circuit on the substrate, or a forward projection area of the fourth pixel circuit, the second pixel circuit, and the third pixel circuit on the substrate are the same.
In a possible implementation manner of the first aspect, the longer the length of the connecting line, the larger the line width of the connecting line, and the shorter the length of the connecting line, the smaller the line width of the connecting line.
In a second aspect, an embodiment of the present application provides a display device including the display panel according to the first aspect.
According to the display panel and the display device provided by the embodiments of the application, since at least part of the connecting lines are positioned on the side of the gate metal layer facing the substrate, the difference of the wiring densities of other metal film layers arranged on the gate metal layer and the side of the gate metal layer facing away from the substrate in the display area can be reduced, and it can be understood that the wiring densities of other metal film layers arranged on the gate metal layer and the side of the gate metal layer facing away from the substrate in the display area can be regarded as equal under the condition that all the connecting lines are positioned on the side of the gate metal layer facing the substrate, and therefore, the difference of reflection of light caused by the wiring densities in different areas of the display area can be improved or eliminated by arranging at least part of the connecting lines on the side of the gate metal layer facing the substrate, thereby reducing the display difference of the whole display area and improving the display effect.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar features, and in which the figures are not to scale.
Fig. 1 is a schematic top view of a display panel according to an embodiment of the present application;
fig. 2 is another schematic top view of a display panel according to an embodiment of the present application;
FIG. 3 is a schematic top view of a display panel according to an embodiment of the present application;
FIG. 4 shows an enlarged schematic view of the region Q1 of FIG. 1;
FIG. 5 shows another enlarged schematic view of the region Q2 of FIG. 2;
FIG. 6 shows an enlarged schematic view of the region Q3 of FIG. 3;
FIG. 7 shows a schematic cross-sectional view in the direction A-A of FIG. 4;
FIG. 8 shows a schematic cross-sectional view in the direction B-B in FIG. 5;
FIG. 9 shows another cross-sectional view in the direction B-B in FIG. 5;
FIG. 10 shows a schematic cross-sectional view in the direction C-C in FIG. 6;
Fig. 11 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application;
Fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to illustrate the application and are not configured to limit the application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.
For technologies such as under-screen cameras and perforated screens, signal lines around a camera area or an open area need to be connected in a one-to-one correspondence manner by using wires, or light emitting elements in the camera area need to be connected with pixel circuits outside the camera area correspondingly by using wires. Because the display area provided with the winding is additionally provided with the winding, the difference exists between the wiring density of the display area provided with the winding and the wiring density of other display areas, and the reflection degree of the wiring density is different to ambient light or other light, so that the display effect of the display area provided with the winding is different from that of the other display areas, and the overall display effect of the display panel is affected.
In view of the foregoing technical problems, embodiments of the present application provide a display panel and a display device, and the display panel and the display device provided by the embodiments of the present application will be described with reference to the accompanying drawings.
As shown in fig. 1 to 10, an embodiment of the present application provides a display panel 100 having a display area AA and a functional area UA adjacent to each other. The display panel 100 may be an Organic LIGHT EMITTING Diode (OLED) display panel.
It is understood that the display area AA may be displayed, and a light emitting element is disposed in the display area AA, and a pixel circuit for driving the light emitting element to emit light may be disposed in the display area AA. For example, the functional area UA may be a non-display area of the display panel, or the functional area UA may be a display area of the display panel. It will be appreciated that in the case where the functional area UA is a display area, a light emitting element may be disposed in the functional area UA, and in the case where the functional area UA is a non-display area, a light emitting element may not be disposed in the functional area UA.
The functional area UA may be a rectangular area, a circular area, an elliptical area, a square area, or the like, and the shape of the functional area UA may be set according to actual requirements, which is not limited in the present application.
The functional area UA may be used for placing the photosensitive element or a gate drive circuit may be provided in the functional area UA. The photosensitive assembly may be an image capturing device for capturing external image information. For example, the photosensitive component is a camera or the like. The photosensitive component may not be limited to an image capture device, for example, in some embodiments, the photosensitive component may also be an infrared sensor, a proximity sensor, an infrared lens, a floodlight sensing element, an ambient light sensor, a dot matrix projector, or the like. The grid driving circuit is used for generating a scanning signal and/or a light-emitting control signal.
The display panel 100 may include a substrate 10, a driving device layer 20, and a plurality of connection lines 30.
The substrate 10 may be a glass substrate or a flexible substrate, for example. For example, as shown in any one of fig. 7 to 10, the substrate 10 may include a Glass base Glass, a first flexible layer PI1, a first barrier layer BL1, a second flexible layer PI2, and a second barrier layer BL2, which are stacked. The materials of the first and second flexible layers PI1 and PI2 may include Polyimide (PI). The material of the first and second barrier layers BL1 and BL2 may include silicon oxide (SiOx).
The driving device layer 20 may also be referred to as an array layer, and driving circuits of the display panel and at least part of signal lines (e.g., pixel circuits, gate driving circuits, scan signal lines, data signal lines, light emission control signal lines, reference voltage signal lines, etc.) may be disposed at the driving device layer 20.
The driving device layer 20 includes a semiconductor layer B, a gate insulating layer GI, and a gate metal layer M1, which are stacked, the semiconductor layer B is located on a side of the substrate 10, the gate insulating layer GI is located on a side of the semiconductor layer B facing away from the substrate 10, and the gate metal layer M1 is located on a side of the gate insulating layer GI facing away from the substrate 10.
The driving device layer 20 may further include a capacitive metal layer M2, a source drain metal layer M3, an auxiliary metal layer M4, a capacitive insulating layer CI, an interlayer insulating layer ILD, a first planarization layer PLN1, and a second planarization layer PLN2. The display panel may further include a light emitting layer 40. The light emitting layer 40 may include a pixel defining layer PDL and a light emitting element, which may include a first electrode RE, an organic light emitting layer OM, and a second electrode SE, which are stacked. The first electrode RE may be an anode, and the second electrode SE may be a cathode, for example. The cathode of the display panel 100 may be a face electrode.
The capacitance insulation layer CI is located between the gate metal layer M1 and the capacitance metal layer M2, the interlayer insulation layer ILD is located between the capacitance metal layer M2 and the source/drain metal layer M3, and the first planarization layer PLN1 is located between the source/drain metal layer M3 and the auxiliary metal layer M4. The second planarization layer PLN2 is located between the auxiliary metal layer M4 and the light emitting layer.
For example, a pixel circuit (not shown) of the display panel 100 may include transistors and capacitors, and an active layer of each transistor may be disposed at the semiconductor layer B. One plate of the capacitor may be disposed on the gate metal layer M1, and the other plate may be disposed on the capacitor metal layer M2.
For example, the display panel 100 may include a Scan signal line (Scan), a Data signal line (Data), a light emission control signal line (Emit), a reference voltage signal line (Vref), a power signal line (PVDD), etc., which are not shown in the above signal line diagrams, the Scan signal line and the light emission control signal line may be disposed on the gate metal layer M1, the reference voltage signal line may be disposed on the capacitor metal layer M2, and the Data signal line and the power signal line may be disposed on the source drain metal layer M3. For example, in order to reduce the voltage drop of the power signal line, the power signal line may have a mesh structure, a portion of the power signal line may be disposed on the source/drain metal layer M3, and another portion of the power signal line may be disposed on the auxiliary metal layer M4. It is understood that the extending direction of the power signal line provided to the source/drain metal layer M3 may be the same as the extending direction of the data signal line, and the extending direction of the power signal line provided to the auxiliary metal layer M4 may intersect with the extending direction of the data signal line.
In this case, the functional area UA shown in fig. 4 may be referred to as a hole area, an opening area, a slot area, a blind hole area, a via area, or the like, which is not limited in the present application. The functional area UA divides the partial signal line 50 into two signal lines, which may be a data signal line, a scan signal line, a light emission control signal line, a reference voltage signal line, and the like. To ensure proper transmission of signals, two signal lines separated by a functional area UA need to be connected. For example, the connection line 30 may be used to connect two signal lines that are separated by the functional area UA and transmit the same signal. For example, a portion of the data signal lines are separated into two data signal traces by the functional area UA, and the connection line 30 may connect the separated two data signal traces.
Taking the functional area UA shown in fig. 5 as an example of a display area, the functional area UA may also be referred to as a light-transmitting display area, an under-screen camera area, or the like. Alternatively, the functional area UA shown in fig. 6 is taken as an example of a display area, and in this case, the functional area UA may be also referred to as a frame display area, a gate driving circuit area, or the like. Since the functional area UA is a display area, it is understood that a light emitting element is disposed in the functional area UA, and the light emitting element disposed in the functional area UA may be referred to as a first light emitting element PX1. In order to increase the light transmittance of the functional area UA, or because the space of the functional area UA is limited, a pixel circuit driving the first light emitting element PX1 may be disposed in the display area AA, and the pixel circuit driving the first light emitting element PX1 may be referred to as a first pixel circuit PU1. In order to ensure that the first light emitting element PX1 emits light, the first light emitting element PX1 and the first pixel circuit PU1 need to be connected. Illustratively, the connection line 30 may be used to connect a pixel circuit (e.g., the first pixel circuit PU 1) disposed within the display area AA and a light emitting element (e.g., the first light emitting element PX 1) disposed within the functional area UA.
It will be appreciated that for the entire display area AA, the connection lines 30 are provided in a partial area, and the connection lines 30 are not provided in a partial area. That is, the area of the display area AA where the connection lines 30 are disposed has a larger number of traces than the area where the connection lines 30 are not disposed, resulting in a difference in the trace density between the area of the display area AA where the connection lines 30 are disposed and the area where the connection lines 30 are not disposed, and the difference in the trace density is different in the reflection degree of the ambient light or other light.
The applicant has found that the effect of light reflection on the display effect is mainly reflected in the gate metal layer M1 and other metal film layers (e.g., the capacitor metal layer M2, the source/drain metal layer M3 and the auxiliary metal layer M4) on the side of the gate metal layer M1 facing away from the substrate 10, so that the display difference degree of the whole display area AA can be reduced by reducing the difference of the routing densities of the other metal film layers disposed on the side of the gate metal layer M1 and the gate metal layer M1 facing away from the substrate 10 in the display area AA.
Based on the above findings, in the display panel 100 provided in the embodiment of the application, at least part of the plurality of wires 30 is located at the side of the gate metal layer M1 facing the substrate 10. It is understood that at least a portion of the connection line 30 is located under the gate metal layer M1. For example, the total number of the wires 30 is 1000, and at least 50% of 1000 wires may be located on the side of the gate metal layer M1 facing the substrate 10, the other wires 30 may be located on the side of the gate metal layer M1 or the gate metal layer M1 facing away from the substrate 10, or all the wires 30 may be located on the side of the gate metal layer M1 facing the substrate 10. The above values are only examples and are not intended to limit the present application.
Since at least part of the connection lines 30 are located on the side of the gate metal layer M1 facing the substrate 10, the difference in the routing densities of the other metal film layers disposed on the side of the gate metal layer M1 and the gate metal layer M1 facing away from the substrate 10 in the display area AA can be reduced, and it is understood that in the case that all of the connection lines 30 are located on the side of the gate metal layer M1 facing the substrate 10, the routing densities of the other metal film layers disposed on the side of the gate metal layer M1 and the gate metal layer M1 facing away from the substrate 10 in the display area AA can be regarded as equal, and thus, by disposing at least part of the connection lines 30 on the side of the gate metal layer M1 facing the substrate 10, the difference in light reflection caused by the routing densities in different regions of the display area AA can be improved or eliminated, thereby reducing the display difference in the whole display area AA.
For example, at least part of the plurality of connection lines 30 may be located on a side of the gate metal layer M1 facing the substrate 10, for example, at least part of the plurality of connection lines 30 may be located between the semiconductor layer B and the gate metal layer M1, for example, at least part of the plurality of connection lines 30 may be located between the semiconductor layer B and the substrate 10, for example, part of the plurality of connection lines 30 may be located between the semiconductor layer B and the gate metal layer M1, another part of the plurality of connection lines may be located between the semiconductor layer B and the substrate 10, and the specific location of the connection lines may be set according to specific needs.
In some alternative embodiments, in the case that the connection line 30 is located between the semiconductor layer B and the gate metal layer M1, and the connection line 30 is used to connect the pixel circuit disposed within the display area AA and the light emitting element disposed within the functional area UA, the connection line 30 is directly in contact with and connected to the source or drain region of the active layer of at least one transistor of the pixel circuit.
For example, as shown in fig. 8, the connection line 30 is used to connect the first pixel circuit PU1 disposed in the display area AA and the first light emitting element PX1 disposed in the functional area UA, and the first pixel circuit PU1 may include a plurality of transistors. As shown in fig. 8, an active layer of the transistor T may be disposed on the semiconductor layer B, the active layer may include a source region S, a drain region D, and a channel region P, a gate electrode G of the transistor T1 in the first pixel circuit PU1 may be disposed on the gate metal layer M1, and an orthographic projection of the channel region P of the active layer on the substrate 10 overlaps with an orthographic projection of the gate electrode G on the substrate 10, and an orthographic projection of the source region S and the drain region D on the substrate 10 does not overlap with an orthographic projection of the gate electrode G on the substrate 10. The source region S and the drain region D may be understood as heavily doped regions of the active layer, and the channel region P may be understood as lightly doped regions of the active layer. The source region S and the drain region D may be a source and a drain of the transistor T1, respectively. The connection line 30 may be directly connected to the drain region D of the transistor T1 of the first pixel circuit PU1, that is, the connection line 30 may be directly overlapped on the drain region D of the transistor T1 of the first pixel circuit PU1, without a via hole therebetween, so that the process complexity may be reduced.
For example, in the process of manufacturing the display panel, the active layer of each transistor of the first pixel circuit PU1 may be formed first, then the connection line 30 is formed, the formed connection line 30 is directly overlapped with the drain region D of the active layer of at least one transistor, and then the gate insulating layer GI covering the active layer and the connection line 30 is formed.
It can be understood that, in the case that the connection line 30 is located between the semiconductor layer B and the gate metal layer M1, and the connection line 30 is used for connecting two signal lines separated by the functional area UA and transmitting the same signal, insulation is required between the connection line 30 and the semiconductor layer B and between the connection line 30 and the gate metal layer M1, and the connection line 30 cannot form the gate of the transistor in the pixel circuit, so as to avoid signal crosstalk.
In some alternative embodiments, in the case where the connection line 30 is located between the semiconductor layer B and the substrate 10, and the connection line 30 is used to connect the pixel circuit disposed within the display area AA and the light emitting element disposed within the functional area UA, the connection line is directly contact-connected with the source or drain region of the active layer of at least one transistor of the pixel circuit.
For example, as shown in fig. 9, the connection line 30 is used to connect the first pixel circuit PU1 disposed in the display area AA and the first light emitting element PX1 disposed in the functional area UA, and the first pixel circuit PU1 may include a plurality of transistors. As shown in fig. 9, the active layer of the transistor T1 in the first pixel circuit PU1 may also be disposed on the semiconductor layer B, the active layer of the transistor T1 may also include a source region S, a drain region D, and a channel region P, and the gate electrode G of the transistor T1 may be disposed on the gate metal layer M1. The source region S and the drain region D of the active layer of the transistor T1 may be a source and a drain of the transistor T1, respectively. The connection line 30 may be directly connected to the drain region D of the transistor T1 of the first pixel circuit PU1, that is, the drain region D of the transistor T1 of the first pixel circuit PU1 may be directly overlapped on the connection line 30, and no via hole is required between the two, so that the process complexity may be reduced.
For example, in the process of manufacturing the display panel, the connection line 30 may be formed first, the active layer of each transistor of the first pixel circuit PU1 is formed, the drain region D of the active layer of at least one transistor of the first pixel circuit PU1 is formed to directly overlap with the connection line 30, and then the gate insulating layer GI covering the active layer and the connection line 30 is formed.
It can be understood that, in the case that the connection line 30 is located between the semiconductor layer B and the substrate 10, and the connection line 30 is used for connecting two signal lines separated by the functional area UA and transmitting the same signal, the connection line 30 needs to be disposed in an insulating manner between the semiconductor layer B and the gate metal layer M1, and the connection line 30 cannot form the gate of the transistor in the pixel circuit, so as to avoid signal crosstalk.
In some alternative embodiments, as shown in fig. 10, a buffer layer B2 is provided between the connection line 30 and the semiconductor layer B. The buffer layer B2 between the connection line 30 and the semiconductor layer B is referred to herein as a second buffer layer. Illustratively, the display panel 100 further includes a first buffer layer B1. The first buffer layer B1 is located at a side of the substrate 10, the second buffer layer B2 is located at a side of the first buffer layer B1 facing away from the substrate 10, and the semiconductor layer B is located at a side of the second buffer layer B2 facing away from the substrate 10. The first buffer layer B1 and the second buffer layer B2 are both insulating layers. For example, the material of the first buffer layer B1 may include silicon nitride (SiNx), and the material of the second buffer layer B2 may include silicon oxide (SiOx).
The connection line 30 may be disposed between the first buffer layer B1 and the second buffer layer B2, and in the case where the connection line 30 is used to connect a pixel circuit disposed within the display area AA and a light emitting element disposed within the functional area UA, the connection line 30 is connected to a source or drain region of an active layer of at least one transistor of the pixel circuit through a via hole.
For example, as shown in fig. 10, the connection line 30 is used to connect the fourth pixel circuit PU4 disposed in the display area AA and the fourth light emitting element PX4 disposed in the functional area UA, and the fourth pixel circuit PU4 may include a plurality of transistors. The difference between fig. 10 and fig. 8 or fig. 9 is that the connection line 30 is connected to the drain region D of the transistor T4 of the fourth pixel circuit PU4 through the via hole h1, so that the short circuit between the connection line 30 and the active layers of other transistors in the fourth pixel circuit PU4 can be avoided.
In some alternative embodiments, please continue to refer to fig. 10, the connection line 30 is disposed between the first buffer layer B1 and the second buffer layer B2, and the orthographic projection of the connection line 30 on the substrate 10 at least partially overlaps with the orthographic projection of the channel region of the active layer of the at least one transistor of the pixel circuit on the substrate 10. Fig. 10 shows that the orthographic projection of the connection line 30 on the substrate 10 at least partially overlaps with the orthographic projection of the channel region P of the active layer of the transistor T4 of the fourth pixel circuit PU4 on the substrate 10. The light can have an irreversible effect on the characteristics of the transistor, and by making the connecting line 30 block the channel region of the active layer of the transistor, light can be prevented from entering the channel region, thereby preventing the light from affecting the characteristics of the transistor.
In some alternative embodiments, the material of the connection line 30 may include molybdenum (Mo), indium Tin Oxide (ITO), or the connection line 30 may be a titanium/aluminum/titanium (Ti/Al/Ti) metal laminate structure, which is not limited in the present application.
For example, in the case where the connection line 30 is used to connect a light emitting element and a pixel circuit, as shown in any one of fig. 8 to 10, the connection line 30 may be connected to the first electrode RE of the light emitting element through a via hole. In order to reduce the difficulty in preparing the connection via between the connection line 30 and the light emitting element, the via between the connection line 30 and the light emitting element may include at least two vias, thereby reducing the depth of a single via and reducing the difficulty in preparing the via.
In some alternative embodiments, the lengths of the plurality of connection lines 30 are different, and the longer the length of the connection line 30, the larger the line width of the connection line 30 may be, and the shorter the length of the connection line 30, the smaller the line width of the connection line 30 may be. Thus, the resistances of the different connection lines 30 are made to be uniform, and display differences due to the different resistances of the connection lines 30 are improved.
In some alternative embodiments, referring to fig. 2, 5 and 8 in combination, the display area AA includes a main display area A1 and a transitional display area A3 adjacent to each other, the transitional display area A3 surrounds at least a portion of the functional area UA, the functional area UA is a light-transmitting display area, the functional area UA includes a first light emitting element PX1, the transitional display area A3 includes a first pixel circuit PU1, and the connection line 30 connects the first light emitting element PX1 and the first pixel circuit PU1. In fig. 5, the pixel circuits of the respective regions are shown hidden for clarity.
The transition display area A3 further includes a second light emitting element PX2 and a second pixel circuit PU2 for driving the second light emitting element PX2, and the main display area A1 further includes a third light emitting element PX3 and a third pixel circuit PU3 for driving the third light emitting element PX 3. Optionally, the orthographic projection area of the first pixel circuit PU1 on the substrate 10 is smaller than the orthographic projection area of the third pixel circuit PU3 on the substrate 10, and/or the orthographic projection area of the second pixel circuit PU2 on the substrate 10 is smaller than the orthographic projection area of the third pixel circuit PU3 on the substrate 10. That is, the size of the first pixel circuit PU1 and/or the second pixel circuit PU2 may be compressed. For example, alternatively, the orthographic projection area of the first pixel circuit PU1 on the substrate 10 may be equal to the orthographic projection area of the second pixel circuit PU2 on the substrate 10.
In the case of a higher pixel density of the display panel, the pixel circuit density of the display panel 100 is also higher, and in general, each pixel circuit of the entire display panel is disposed in close proximity, that is, if the original second pixel circuit PU2 or the first pixel circuit PU1 driving the first light emitting element PX1 in the transitional display area A3 is not compressed, no additional space is provided in the transitional display area A3 for placing the first pixel circuit PU1, but in the embodiment of the present application, by compressing the size of the first pixel circuit PU1 and/or the second pixel circuit PU2, enough space is provided in the transitional display area A3 for placing the first pixel circuit PU1.
Alternatively, the front projection area of the first pixel circuit PU1 on the substrate 10, the front projection area of the second pixel circuit PU2 on the substrate 10, and the front projection area of the third pixel circuit PU3 on the substrate 10 may be equal. That is, in the case where the pixel density of the display panel is high, the sizes of the first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 can be compressed, so that not only can there be enough space in the transition display area A3 to place the first pixel circuit PU1, but also driving capability differences caused by different sizes of the pixel circuits can be avoided, thereby avoiding uneven display.
Alternatively, the pixel density of the transition display area A3 and the functional area UA may be reduced, and the sizes of the first pixel circuit PU1 and the second pixel circuit PU2 may not be compressed, so that the forward projection area of the first pixel circuit PU1 on the substrate 10, the forward projection area of the second pixel circuit PU2 on the substrate 10, and the forward projection area of the third pixel circuit PU3 on the substrate 10 are also equal.
In some alternative embodiments, the circuit structure of the first pixel circuit PU1, the circuit structure of the second pixel circuit PU2, and the circuit structure of the third pixel circuit PU3 may be the same, and the first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 each include a transistor and a capacitor. The compression of the sizes of the first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 can be achieved by compressing the sizes of the transistors in the respective pixel circuits.
By way of example, the orthographic projected area of a pixel circuit on substrate 10 may be understood as the sum of the orthographic projected area of the individual transistors included in the pixel circuit and the capacitance on substrate 10.
For example, the first pixel circuits PU1 and the second pixel circuits PU2 in the transitional display area A3 may be alternately distributed in the first direction X, and all the first pixel circuits PU1 may be distributed near the functional area. The first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 may all be distributed in an array.
The circuit structures of the first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 are each the circuit structure of 7T1C shown in fig. 11, for example. In fig. 11, T11 to T17 denote 7 transistors, cst denotes a storage capacitor, D denotes a light emitting element, scan1 denotes a first scanning signal line, scan2 denotes a second scanning signal line, data denotes a Data signal line, emit denotes a light emission control signal line, vref denotes a reference voltage signal line, PVDD power supply signal line, and PVEE denotes a common voltage terminal.
Of course, the circuit structures of the first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 may be all 2T1C, 4T1C, 6T2C, 7T2C, or the like, which is not limited in the present application. Where "T" denotes a transistor, "C" denotes a capacitance, "7T1C" denotes a transistor having 7 transistors and 1 capacitance, and so on.
In some alternative embodiments, referring to fig. 1 and 4 in combination, the display area AA includes a main display area A1 and a winding display area A2 adjacent to each other, the winding display area A2 surrounding at least a portion of the functional area UA. The functional area UA may be a display area or a non-display area.
The display panel 100 further includes a plurality of signal lines 50, each signal line 50 is electrically connected to a pixel circuit disposed in the display area AA and extends along the first direction X, the plurality of signal lines 50 includes a plurality of first type signal lines 51 and a plurality of second type signal lines 52, each second type signal line 52 includes a first segment 521 and a second segment 522 separated by a functional area UA, it is understood that each first type signal line 51 is a continuous trace, and each first type signal line 51 is not separated by the functional area UA. In order to be able to supply signals to the pixel driving circuits electrically connected to the same second type signal line 52, the first 521 and second 522 segments, which are separated, may be connected by a connection line 30 (the connection line 30 is illustrated in broken lines in the figure).
For example, the connection line 30 may be disposed in the winding display area A2, taking the functional area UA as the non-display area, and since the connection line 30 is disposed in the winding display area A2, the frame area of the functional area UA may be reduced, that is, the area of the non-display area may be reduced, thereby improving the screen ratio of the display panel.
The plurality of signal lines 50 extend along the first direction X and are spaced apart in the second direction Y, and the first direction X intersects the second direction Y, for example, the first direction X and the second direction Y may be perpendicular.
Alternatively, the first direction X may be a column direction, and the signal line 50 may be a Data signal line (Data).
Alternatively, the first direction X may be a row direction, and the signal line 50 may be a Scan signal line (Scan) or a light emission control signal line (Emit) or a reference voltage signal line (Vref).
In some alternative embodiments, referring to fig. 3, 6 and 9 in combination, the display area AA includes a main display area A1 and a sub display area A4 that are adjacent, and the functional area UA is adjacent to the sub display area A4. The functional area UA includes a gate driving circuit VSR and a fourth light emitting element PX4, and the auxiliary display area A4 includes a fourth pixel circuit PU2, and the connection line 30 is used for connecting the fourth light emitting element PX4 and the fourth pixel circuit PU4.
According to the embodiment of the application, the non-display area which is originally provided with the grid driving circuit VSR is also designed as the display area, so that the whole display area of the display panel is increased, and the screen occupation ratio is increased.
The auxiliary display area A4 further includes a fifth light emitting element PX5 and a second pixel circuit PU5 for driving the fifth light emitting element PX5, and the main display area A1 further includes a third light emitting element PX3 and a third pixel circuit PU3 for driving the third light emitting element PX 3. Optionally, the orthographic projection area of the fourth pixel circuit PU4 on the substrate 10 is smaller than the orthographic projection area of the third pixel circuit PU3 on the substrate 10, and/or the orthographic projection area of the fifth pixel circuit PU5 on the substrate 10 is smaller than the orthographic projection area of the third pixel circuit PU3 on the substrate 10. That is, the size of the fourth pixel circuit PU4 and/or the second pixel circuit PU2 may be compressed. Illustratively, optionally, the orthographic projection area of the fourth pixel circuit PU4 on the substrate 10 may be equal to the orthographic projection area of the fifth pixel circuit PU5 on the substrate 10. As described above, in the case where the pixel density of the display panel is high, the pixel density of the pixel circuits on the display panel 100 is also high, and in general, each pixel circuit on the entire display panel is disposed in close proximity, that is, if the original fifth pixel circuit PU5 in the auxiliary display area A4 or the fourth pixel circuit PU4 driving the fourth light emitting element PX4 is not compressed, no additional space is provided in the auxiliary display area A4 to place the fourth pixel circuit PU4, and in the embodiment of the present application, by compressing the size of the fourth pixel circuit PU4 and/or the fifth pixel circuit PU5, there is enough space in the auxiliary display area A4 to place the fourth pixel circuit PU4.
Alternatively, the forward projection area of the fourth pixel circuit PU4 on the substrate 10, the forward projection area of the fifth pixel circuit PU5 on the substrate 10, and the forward projection area of the third pixel circuit PU3 on the substrate 10 may be equal. That is, in the case where the pixel density of the display panel is high, the sizes of the fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 can be all compressed, so that not only can there be enough space in the auxiliary display area A4 to place the fourth pixel circuit PU4, but also driving capability differences caused by different sizes of the pixel circuits can be avoided, thereby avoiding uneven display.
For example, the pixel density of the functional area UA and the auxiliary display area A4 may be reduced, and the sizes of the fourth pixel circuit PU4 and the fifth pixel circuit PU5 may not be compressed any more, and the front projection area of the fourth pixel circuit PU4 on the substrate 10, the front projection area of the fifth pixel circuit PU5 on the substrate 10, and the front projection area of the third pixel circuit PU3 on the substrate 10 may be equal.
In some alternative embodiments, the circuit structure of the fourth pixel circuit PU4, the circuit structure of the fifth pixel circuit PU5, and the circuit structure of the third pixel circuit PU3 may be the same, and the first pixel circuit PU1, the fifth pixel circuit PU5, and the third pixel circuit PU3 each include transistors. The compression of the sizes of the fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 can be achieved by compressing the sizes of the transistors in the respective pixel circuits.
For example, the fourth pixel circuits PU4 and the fifth pixel circuits PU5 in the auxiliary display area A4 may be alternately distributed in the first direction X, and all the fourth pixel circuits PU4 may be distributed near the functional area. The fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 may all be distributed in an array.
The circuit structures of the fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 are each the circuit structure of 7T1C shown in fig. 10, for example. In fig. 10, T11 to T17 denote 7 transistors, cst denotes a storage capacitor, D denotes a light emitting element, scan1 denotes a first scanning signal line, scan2 denotes a second scanning signal line, data denotes a Data signal line, emit denotes a light emission control signal line, vref denotes a reference voltage signal line, PVDD power supply signal line, and PVEE denotes a common voltage terminal.
Of course, the circuit structures of the fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 may be all 2T1C, 4T1C, 6T2C, 7T2C, or the like, which is not limited in the present application. Where "T" denotes a transistor, "C" denotes a capacitance, "7T1C" denotes a transistor having 7 transistors and 1 capacitance, and so on.
It should be noted that the above embodiments may be combined with each other without contradiction.
As shown in fig. 12, an embodiment of the present application further provides a display device 1000 including the display panel 100 described in the above embodiment. Since the display device 1000 includes the display panel 100 according to the above embodiment, the display device 1000 has the advantages of the display panel 100 according to the above embodiment, and will not be described in detail herein.
The display device may be any electronic apparatus having a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
These embodiments are not exhaustive of all details, nor are they intended to limit the application to the precise embodiments disclosed, in accordance with the application. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (13)
1. A display panel having contiguous display and functional regions, the functional regions comprising photosensitive elements or gate drive circuits, the display panel comprising:
A substrate;
The driving device layer comprises a semiconductor layer, a gate insulating layer and a gate metal layer which are stacked, wherein the semiconductor layer is positioned on one side of the substrate, the gate insulating layer is positioned on one side of the semiconductor layer, which is away from the substrate, and the gate metal layer is positioned on one side of the gate insulating layer, which is away from the substrate;
A plurality of connection lines for connecting two signal lines which are separated by the functional region and transmit the same signal, or for connecting a pixel circuit provided within the display region and a light emitting element provided within the functional region, at least part of the plurality of connection lines being located on a side of the gate metal layer toward the substrate, the connection lines being provided in a region of the display region close to the functional region, the connection lines not being provided in a region of the display region away from the functional region;
the data signal line of the display panel is positioned on one side of the grid metal layer, which is away from the substrate.
2. The display panel of claim 1, wherein at least a portion of the plurality of connection lines are located between the semiconductor layer and the gate metal layer.
3. The display panel according to claim 2, wherein the connection line is for connecting a pixel circuit provided within the display region and a light emitting element provided within the functional region, the connection line being in direct contact connection with a source region or a drain region of an active layer of at least one transistor of the pixel circuit.
4. The display panel of claim 1, wherein at least a portion of the plurality of connection lines are located between the semiconductor layer and the substrate.
5. The display panel according to claim 4, wherein in the case where the connection line connects a pixel circuit provided within the display region and a light emitting element provided within the functional region, the connection line is connected in direct contact with a source region or a drain region of an active layer of at least one transistor of the pixel circuit;
Or a buffer layer is arranged between the connecting line and the semiconductor layer, and the connecting line is connected with a source region or a drain region of an active layer of at least one transistor of the pixel circuit through a via hole under the condition that the connecting line is used for connecting the pixel circuit arranged in the display region and the light-emitting element arranged in the functional region.
6. The display panel according to claim 4, wherein a buffer layer is provided between the connection line and the semiconductor layer, and an orthographic projection of the connection line on the substrate at least partially overlaps with an orthographic projection of a channel region of an active layer of at least one transistor of the pixel circuit on the substrate.
7. The display panel according to any one of claims 1 to 6, wherein the display region comprises a main display region and a transitional display region adjoining each other, the transitional display region surrounding at least part of the functional region, the functional region being a light-transmissive display region, the functional region comprising a first light-emitting element, the transitional display region comprising a first pixel circuit, the connection line being for connecting the first light-emitting element and the first pixel circuit;
The transition display area further comprises a second light-emitting element and a second pixel circuit for driving the second light-emitting element, the main display area further comprises a third light-emitting element and a third pixel circuit for driving the third light-emitting element, the orthographic projection area of the first pixel circuit on the substrate is smaller than the orthographic projection area of the third pixel circuit on the substrate, and/or the orthographic projection area of the second pixel circuit on the substrate is smaller than the orthographic projection area of the third pixel circuit on the substrate, or the orthographic projection areas of the first pixel circuit, the second pixel circuit and the third pixel circuit on the substrate are the same.
8. The display panel of any one of claims 1 to 6, wherein the display area comprises a contiguous main display area and a wire wrap display area surrounding at least a portion of the functional area, the display panel further comprising:
A plurality of signal lines, each of which is electrically connected to a pixel circuit provided in the display region and extends in a first direction, the plurality of signal lines including a plurality of first-type signal lines and a plurality of second-type signal lines, each of the second-type signal lines including a first segment and a second segment separated by the functional region;
The connecting wire is used for connecting the first section and the second section, and at least part of the connecting wire is positioned in the winding display area.
9. The display panel according to claim 8, wherein the first direction is a column direction, and the signal line is a data signal line;
Or the first direction is a row direction, and the signal line is a scanning signal line or a light-emitting control signal line or a reference voltage signal line.
10. The display panel according to any one of claims 1 to 6, wherein the display region includes a main display region and a sub display region adjacent to each other, the functional region being adjacent to the sub display region;
the functional area comprises a grid driving circuit and a fourth light-emitting element, the auxiliary display area comprises a fourth pixel circuit, and the connecting wire is used for connecting the fourth light-emitting element and the fourth pixel circuit.
11. The display panel according to claim 10, wherein the auxiliary display region further includes a fifth light emitting element and a fifth pixel circuit for driving the fifth light emitting element, wherein the main display region further includes a third light emitting element and a third pixel circuit for driving the third light emitting element, wherein a forward projection area of the fourth pixel circuit on the substrate is smaller than a forward projection area of the third pixel circuit on the substrate, and/or wherein a forward projection area of the fifth pixel circuit on the substrate is smaller than a forward projection area of the third pixel circuit on the substrate, or wherein a forward projection area of the fourth pixel circuit, the fifth pixel circuit, and the third pixel circuit on the substrate are the same.
12. The display panel according to claim 1, wherein the longer the length of the connection line is, the larger the line width of the connection line is, and the shorter the length of the connection line is, the smaller the line width of the connection line is.
13. A display device comprising the display panel according to any one of claims 1 to 12.
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| CN114284247A (en) * | 2021-12-16 | 2022-04-05 | 昆山工研院新型平板显示技术中心有限公司 | Array substrate, display panel and display device |
| CN114335105A (en) * | 2021-12-28 | 2022-04-12 | 合肥维信诺科技有限公司 | Display panel and display device |
| JP2024546553A (en) * | 2022-01-07 | 2024-12-26 | 京東方科技集團股▲ふん▼有限公司 | Display substrate and display device |
| WO2023142071A1 (en) * | 2022-01-29 | 2023-08-03 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display apparatus |
| CN114566532A (en) * | 2022-02-28 | 2022-05-31 | 昆山国显光电有限公司 | Display panel and display device |
| CN114582265B (en) * | 2022-02-28 | 2023-06-20 | 昆山国显光电有限公司 | Display panel and display device |
| CN114914280B (en) * | 2022-04-25 | 2024-07-12 | 上海天马微电子有限公司 | Display panel and display device |
| US20240389382A1 (en) * | 2022-04-28 | 2024-11-21 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display Substrate and Display Device |
| CN115581104A (en) * | 2022-09-05 | 2023-01-06 | 武汉天马微电子有限公司 | Display panel and display device |
| CN115294878B (en) * | 2022-09-06 | 2024-10-15 | 武汉天马微电子有限公司上海分公司 | Display panel and display device |
| CN115547196A (en) * | 2022-09-27 | 2022-12-30 | 武汉天马微电子有限公司 | Display panel and display device |
| CN116456773A (en) * | 2023-04-28 | 2023-07-18 | 合肥维信诺科技有限公司 | Display panel and display device |
| CN116939074A (en) * | 2023-06-13 | 2023-10-24 | 云谷（固安）科技有限公司 | Display screen and wireless communication device |
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| CN101738813A (en) * | 2008-11-25 | 2010-06-16 | 乐金显示有限公司 | Electrophoretic display device and method for fabricating the same |
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| CN101738813A (en) * | 2008-11-25 | 2010-06-16 | 乐金显示有限公司 | Electrophoretic display device and method for fabricating the same |
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