CN113571510B

CN113571510B - A layout reinforcement method for SET effect

Info

Publication number: CN113571510B
Application number: CN202110774796.6A
Authority: CN
Inventors: 梁斌; 陈建军; 池雅庆; 袁珩洲; 吴振宇; 宋睿强; 刘必慰; 胡春媚
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2021-07-08
Filing date: 2021-07-08
Publication date: 2025-03-11
Anticipated expiration: 2041-07-08
Also published as: CN113571510A

Abstract

The present invention discloses a layout reinforcement method for SET effect, which includes forming a layout structure with SET reinforcement effect by at least one of seamless well/substrate contact and split active area on the basis of the layout design of the standard unit after adding well contact and substrate contact reinforcement, wherein seamless well/substrate contact refers to canceling the shallow trench isolation STI between the well/substrate contact and the active area, and splitting the active area refers to splitting a wider transistor into several narrower transistors. The present invention aims to solve the problem that the SET effect of global signals such as clock tree and reset network will have a serious impact on the whole chip, and reinforce such global signals.

Description

Layout reinforcement method aiming at SET effect

Technical Field

The invention relates to an integrated circuit design technology, in particular to a layout reinforcement method aiming at a SET (single event transient pulse) effect.

Background

During the fabrication of an integrated circuit, space heavy ions, alpha particles, neutrons and the like bombard sensitive nodes of the integrated circuit, which directly or indirectly cause the integrated circuit to generate soft errors. With the continued reduction of processes, the increasing complexity of integrated circuits, the decreasing supply voltage, and the increasing operating frequency, soft errors are increasingly becoming the most important reliability problem in deep submicron processes. Single Event Upset (SEU), single event transient pulse (SET), and multi-bit upset (MBU) become the main sources of soft errors after process scaling to deep submicron phases. As integrated circuit fabrication processes continue to shrink to the nanometer scale, SET becomes more and more severe, and has become the first source of soft errors.

The charged particles bombard the sensitive node of the circuit, which will generate a transient pulse. SEU can occur if a transient pulse occurs at a sensitive node of a circuit such as a memory cell, latch, flip-flop, etc., and sufficient charge is collected, the transient pulse thus evolves into a "persistent" error, and the erroneous data is not likely to recover correctly until the data is overwritten. If a transient pulse occurs at the combinational logic node and sufficient charge is collected, it will propagate down the data path and possibly be latched by the next stage sequential cells, becoming a "persistent" error. Such transient pulses occurring at the combinational logic node are referred to as SET.

The SET must be captured by the next stage timing cell under at least four conditions, (1) particle bombardment must produce a pulse that propagates along the circuit, i.e., the pulse produced has sufficient width and height, (2) there must be a sensitization path from the bombarded node to the next stage timing cell, (3) the SET must have sufficient width and height to propagate to the next stage timing cell to change the state of the timing cell, i.e., meet the setup and hold time requirements of the timing cell, (4) in a synchronous circuit, the SET must arrive at an effective clock edge. When the SET pulse width generated at the bombarded node is small, then the width is continuously reduced in the propagation process until the SET pulse finally disappears. Therefore, how to reduce the SET pulse width and achieve the final effect of layout reinforcement has become a key technical problem to be solved urgently.

Disclosure of Invention

The invention aims to solve the technical problems in the prior art, provides a layout reinforcement method aiming at the SET effect, and aims to solve the problem that the SET effect of global signals such as clock trees, reset networks and the like will have serious influence on a whole chip, and reinforce the global signals.

In order to solve the technical problems, the invention adopts the following technical scheme:

A layout reinforcement method aiming at the SET effect comprises the step of forming a layout structure with the SET reinforcement effect through at least one of a seamless well/substrate contact mode and an active region segmentation mode on the basis of layout design of standard units reinforced by adding well contacts and substrate contacts.

Optionally, the seamless well/substrate contact refers to eliminating shallow trench isolation STI between the well/substrate contact and the active region, so that the well/substrate contact is in close proximity to the active region to increase the ability of the well/substrate contact to control the bulk potential.

Optionally, after removing the shallow trench isolation STI between the well/substrate contact and the active region, the method further includes that the well contact and the substrate contact extend towards the middle of the layout design at the same time, and are respectively and directly connected with the source electrodes of the PMOS transistor and the NMOS transistor of the standard cell.

Optionally, the dividing the active region refers to splitting a wider transistor into a plurality of narrower transistors, and the split transistors are connected in parallel and replace the original wider transistors, so that the functions of the circuit are not affected, and the transistors refer to PMOS transistors or NMOS transistors.

Optionally, when the wider transistor is split into a plurality of narrower transistors, shallow trench isolation STI is used to isolate the split transistors.

Optionally, when splitting the wider transistor into a plurality of narrower transistors, the split transistors are co-gated.

Optionally, when splitting the wider transistor into a plurality of narrower transistors, the split transistors are distributed in an abacus shape with a common gate as a center in the layout.

In addition, the invention also provides an integrated circuit, which comprises a standard unit, wherein the standard unit is obtained by adopting the layout reinforcement method aiming at the SET effect.

Optionally, the standard unit is an inv_8 unit.

Optionally, the inv_8 unit includes a PMOS transistor and an NMOS transistor connected in parallel to each other.

Compared with the prior art, the invention has the advantages that on the basis of the layout design of the standard unit after the reinforcement of the well contact and the substrate contact, the layout structure with the SET reinforcement effect is formed by at least one of the two modes of seamless well/substrate contact and division of the active area, the SET pulse width can be effectively reduced by the means, and the problem that the SET effect of global signals such as a clock tree, a reset network and the like will have serious influence on a whole chip can be solved, and the global signals are reinforced.

Drawings

Fig. 1 is a schematic diagram of NMOS conventional well contact and irradiation resistance (p+ and STI should be in close proximity in the figure).

Fig. 2 is a schematic diagram of NMOS seamless well/substrate contact irradiation resistance in this embodiment.

Fig. 3 is a schematic diagram of an active region of a split MOS transistor in this embodiment.

Fig. 4 is a circuit diagram of the inv_8 unit in the present embodiment.

FIG. 5 is a physical layout of an INV_8 cell with added well contact and substrate contact reinforcement.

Fig. 6 is a physical layout of inv_8 cells with seamless well/substrate contact reinforcement design only.

FIG. 7 is a physical layout of the INV_8 cell for a split active area only reinforcement design.

FIG. 8 is a physical layout of an INV_8 cell after reinforcement in combination with seamless well/substrate contact and split active area.

Fig. 9 is an experimental simulation flow in the present embodiment.

Detailed Description

The embodiment provides a layout reinforcement method aiming at a SET effect, which comprises the step of forming a layout structure with the SET reinforcement effect through at least one of a seamless well/substrate contact mode and an active region segmentation mode on the basis of layout design of standard units reinforced by adding well contacts and substrate contacts.

In this embodiment, the seamless well/substrate contact means that shallow trench isolation STI (Shallow trench isolation) between the well/substrate contact and the active region is eliminated, and the well contact (PMOS device) and the substrate contact (NMOS device) are isolated from the active region in standard cells by using shallow trench isolation STI (Shallow trench isolation), so that the well/substrate contact is adjacent to the active region to increase the control capability of the well/substrate contact on the body (bulk) potential.

In this embodiment, after eliminating the shallow trench isolation STI between the well/substrate contact and the active region, the method further includes that the well contact and the substrate contact extend toward the middle of the layout design at the same time, and are directly connected with the source electrodes of the PMOS transistor and the NMOS transistor of the standard cell, respectively.

Fig. 1 is a cross-sectional view showing a conventional connection manner of NMOS transistors for comparison. Research shows that the charge collection of the sensitive node caused by particle bombardment can cause a single particle effect, and the magnitude of the charge collection quantity can directly influence the pulse width and the peak value of single particle transient. The larger the charge collection amount of the device, the wider the pulse width of the single event transient, the higher the peak value, and the more easily soft errors are caused. Under conventional bulk silicon processes, the device charge collection mechanism includes drift, diffusion, and bipolar amplification effects, which predominate. The use of seamless well/substrate contact in this embodiment reduces bipolar amplification effects, thereby reducing SET pulse width, as shown in fig. 2. The seamless well/substrate contact approach may result in a transistor length that does not use the minimum gate length. At S40LL, the minimum gate length is 40nm, and if the method of this embodiment is used, the transistor length near the seamless must be 60nm or more to pass the Design Rule Check (DRC).

In this embodiment, dividing the active region refers to splitting a wider transistor into a plurality of narrower transistors, and the split transistors are connected in parallel and replace the original wider transistors, so that the functions of the circuit are not affected, and the transistors refer to PMOS transistors or NMOS transistors.

In this embodiment, when splitting a wider transistor into a plurality of narrower transistors, the split transistors are isolated by shallow trench isolation STI.

In this embodiment, when splitting a wider transistor into a plurality of narrower transistors, the split transistors are co-gated.

In this embodiment, when splitting a wider transistor into a plurality of narrower transistors, the split transistors are distributed in an abacus shape with a common gate as a center in the layout. On the basis of the layout design of the standard unit reinforced by adding the well contact and the substrate contact, the layout structure with a certain SET reinforcing effect is formed by means of seamless well/substrate contact and division of the active region, and the layout shape of the layout structure is like an abacus.

Many studies have shown that bulk silicon devices have been the most sensitive region of the SET due to the charge collection mechanism of "funneling" and parasitic bipolar amplification effects. The charge collection is greatest when the heavy ions bombard the center of the drain region of the device. And the magnitude of the device charge collection amount is positively correlated with the drain area. Therefore, reducing the area of the drain region of the device can effectively reduce the charge collection amount of the device, thereby inhibiting the width and peak value of the single-event transient pulse. Based on this, the present invention splits the transistor in width. When the width of the MOSFET is large and the sensitive area is overlarge, the wider transistor can be split into a plurality of narrower transistors by dividing the active area. The split transistors are connected in parallel to replace the original wider transistors, so that the functions of the circuit are not affected. And the split transistors are isolated by STI. When heavy ions bombard the sensitive nodes, the transistors are isolated from each other because the drain area of the transistors is reduced. So that only a small portion of the charge deposited by a single particle will be collected by the drain of the transistor. This will reduce charge collection and thus achieve the goal of reducing the SET pulse width. The transistors shown in (1) in fig. 3 and (2) in fig. 3 have the same W and L, and by dividing the active region, the layout shown in (2) in fig. 3 effectively reduces the collection area of charges when bombarded, so as to achieve the purpose of reducing the pulse width when bombarded.

In addition, the embodiment also provides an integrated circuit, which comprises standard units, wherein the standard units are obtained by adopting the layout reinforcement method aiming at the SET effect.

In this embodiment, the standard cell is an inv_8 cell. As shown in fig. 4, the inv_8 unit in this embodiment includes a PMOS transistor and an NMOS transistor connected in parallel with each other.

Table 1 shows the four reinforcement modes used for the comparative units of this example, inv_8_A, inv_8_B, inv_8_C and inv_8_D were bombarded with heavy ions having a bombardment energy of let=37 mev·cm2/mg, respectively, and the simulation conditions are shown in table 2.

Table 1 illustrates reinforcement modes.

Unit cell	Reinforcing mode
		INV_8_A	Unreinforced bombardment
INV_8_B	Only seamless well/substrate contact reinforcement
		INV_8_C	Only active region reinforcement
INV_8_D	Seamless well/substrate contact reinforcement + split active region reinforcement

Table 2 heavy ion bombardment simulation conditions.

Process for producing a solid-state image sensor	SMIC40LL
		Technological angle	TT
Voltage (V)	1.1V
		Temperature (temperature)	25°C

Table 3 shows the pulse widths of 4 units after bombardment with heavy ions. The seamless contact reinforcement design can be obtained by comparing the results of the INV_8_B and the INV_8_A, the pulse width is reduced to a certain extent, compared with the NMOS, the reinforcement effect of the PMOS is more obvious, the abacus reinforcement design can be obtained by comparing the results of the INV_8_C and the INV_8_A, the pulse width is reduced to a certain extent, compared with the PMOS, the reinforcement effect of the NMOS is more obvious, and the combined seamless contact and abacus reinforcement design can be obtained by comparing the results of the INV_8_D and the INV_8_A, so that the pulse width of the PMOS and the NMOS can be reduced to a great extent at the same time, and the good SET reinforcement effect is obtained.

TABLE 3 pulse width (units: ps).

Unit cell	Bombard PMOS	Bombarding NMOS
			INV_8_A	200.5	224.7
INV_8_B	105.7	184.5
			INV_8_C	121.9	68.3
INV_8_D	70.4	61.3

Fig. 5 is a physical layout of inv_8 cells without seamless well/substrate contact reinforcement and split active area reinforcement, with only the addition of well contact and substrate contact reinforcement. As can be seen from the figure, the well contact and the substrate contact are located at the top and bottom of the layout, respectively, and are actively connected to the sources of PMOS and NMOS, respectively, through the metal layer.

Fig. 6 is a physical layout of inv_8 cells with seamless well/substrate contact reinforcement design, and it can be seen from the figure that the well contact and the substrate contact extend toward the middle of the layout at the same time and are directly connected with the source electrodes of PMOS and NMOS, respectively. Such an arrangement allows well/substrate contact to be better controlled for body potential and thus effectively inhibits bipolar amplification effects.

Fig. 7 is a physical layout of the inv_8 unit which is designed by only dividing the active region, and it can be seen from the figure that the active width of a single MOS is smaller, and a plurality of MOS transistors share the same gate. Looking at the whole unit layout, the shape is similar to an abacus. Numerous studies have shown that the area of the drain region is reduced, and that the collected charge, and thus the pulse width, is reduced when bombarded with individual particles.

FIG. 8 is a physical layout of an INV_8 cell after reinforcement in combination with seamless well/substrate contact and split active area. Such a stiffening design fully combines the advantages of seamless contact and abacus-like stiffening.

Fig. 9 is a flow of experimental simulation. A well-known IC design software developer, the Sentaurus TCAD tool published by new cisco technologies, usa, was used to construct the 3D device model and perform single-particle simulation. In order to simulate and analyze the single event effect of an INV_8 unit under a 40nm process, as shown in fig. 4, the experimental simulation has the defects that (1) the patterns of the INV_8_A, the INV_8_B and the INV_8_C units are drawn by using Virtuoso software, (2) the drawn patterns are converted into a three-dimensional TCAD model based on the connection relation given by the patterns and the spacing between the units, (3) the drain centers of a PMOS transistor and an NMOS transistor of a standard unit are bombarded by heavy ions with LET of 37MeV cm ²/mg respectively, and (4) the pulse width change of a node generated by the heavy ion bombardment is observed when the LET is 37MeV cm ²/mg. The results obtained in this example are as follows:

(1) The drain center of the inv_8 cell, which was not reinforced and reinforced with a seamless well/substrate contact, was bombarded with heavy ions of bombardment energy let=37 mev·cm ²/mg, respectively, at a 40nm process. The SET pulse width generated by cells consolidated with seamless well/substrate contact is somewhat reduced compared to unconsolidated cells. Wherein the SET pulse of the PMOS device is reduced by 47.3%, and the SET pulse of the NMOS device is reduced by 17.9%.

(2) The drain centers of the inv_8 cells, which were not reinforced and reinforced with the split active region, were bombarded with heavy ions of bombardment energy let=37 mev·cm ²/mg, respectively, at a 40nm process. The SET pulse width generated by using a segmented active region reinforced cell is reduced compared to an unreinforced cell. Wherein the SET pulse of the PMOS device is reduced by 39.2%, and the SET pulse of the NMOS device is reduced by 69.6%.

(3) The drain centers of inv_8 cells, which were not consolidated and consolidated with a combination of split active region and seamless well/substrate contact, were respectively bombarded with heavy ions of bombardment energy let=37 mev·cm ²/mg at a 40nm process. The SET pulse width produced with the cell combined with the split active region and the seamless well/substrate contact reinforcement is narrower than that of the un-reinforced cell. Wherein the SET pulse of the PMOS device is reduced by 64.9%, and the SET pulse of the NMOS device is reduced by 72.7%.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.

Claims

1. A layout reinforcement method for SET effect, characterized in that it includes: on the basis of the layout design of the standard cell after adding well contact and substrate contact reinforcement, forming a layout structure with SET reinforcement effect by at least one of seamless well/substrate contact and segmented active area;

The seamless well/substrate contact refers to the removal of the shallow trench isolation STI between the well/substrate contact and the active area, so that the well/substrate contact is close to the active area to increase the control capability of the well/substrate contact over the body area potential. After the removal of the shallow trench isolation STI between the well/substrate contact and the active area, the well contact and the substrate contact are extended toward the middle of the layout design at the same time, and are directly connected to the source of the PMOS transistor and the NMOS transistor of the standard cell respectively.

The splitting of the active area refers to splitting a wider transistor into several narrower transistors, and the split transistors are connected in parallel and replace the original wider transistor, so as not to affect the function of the circuit. The transistor refers to a PMOS transistor or an NMOS transistor. When the wider transistor is split into several narrower transistors, the split transistors are isolated by shallow trench isolation STI. When the wider transistor is split into several narrower transistors, the split transistors share a gate. When the wider transistor is split into several narrower transistors, the split transistors are distributed in an abacus shape in the layout with a common gate as the center.

2. An integrated circuit comprising a standard cell, wherein the standard cell is a standard cell reinforced by the layout reinforcement method for SET effect according to claim 1.

3 . The integrated circuit according to claim 2 , wherein the standard cell is an INV_8 cell.

4 . The integrated circuit according to claim 3 , wherein the INV_8 unit comprises a PMOS transistor and an NMOS transistor connected in parallel to each other.