CN113571003A - Display device with recovery mechanism - Google Patents
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- 238000011084 recovery Methods 0.000 title claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims abstract description 84
- 230000002159 abnormal effect Effects 0.000 claims abstract description 37
- 238000001514 detection method Methods 0.000 claims description 37
- 230000009471 action Effects 0.000 claims description 9
- 238000004891 communication Methods 0.000 claims description 8
- 230000005856 abnormality Effects 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims description 2
- 101100508810 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) INP53 gene Proteins 0.000 description 34
- 101100366621 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SRO77 gene Proteins 0.000 description 34
- 101100217143 Schizosaccharomyces pombe (strain 972 / ATCC 24843) arc1 gene Proteins 0.000 description 34
- 101150083500 sop-2 gene Proteins 0.000 description 34
- 238000010586 diagram Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
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Abstract
本申请提供一种具有回复机制的显示装置。所述具有回复机制的显示装置包括电源、超级电容、主控制器、辅助控制器、显示器。所述电源电连接所述超级电容，以用于为所述超级电容充电。所述超级电容分别电连接所述主控制器及显示器，以用于为所述主控制器及所述显示器供电。所述主控制器电连接所述显示器，以对所述显示器的显示内容进行显示控制。所述辅助控制器电连接所述主控制器，以用于检测所述主控制器的运行状态，并在确定所述主控制器处于异常的运行状态时发送设置控制信号以对所述主控制器进行设置，从而使所述主控制器回复到正常的运行状态。本发明可以使得显示器上出现错误的显示内容能够恢复正确。
The present application provides a display device with a recovery mechanism. The display device with a recovery mechanism includes a power supply, a super capacitor, a main controller, an auxiliary controller, and a display. The power supply is electrically connected to the supercapacitor for charging the supercapacitor. The super capacitor is electrically connected to the main controller and the display, respectively, for supplying power to the main controller and the display. The main controller is electrically connected to the display to perform display control on the display content of the display. The auxiliary controller is electrically connected to the main controller for detecting the operating state of the main controller, and when it is determined that the main controller is in an abnormal operating state, a setting control signal is sent to control the main controller The controller is set so that the main controller returns to the normal operating state. The present invention can make the display contents appearing wrong on the display recover to be correct.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display device with a reply mechanism.
Background
In recent years, mobile devices (mobile devices) such as tablet computers or smart phones have been developed at a high speed, and innovations in display technologies have been promoted accordingly. In many display technologies, the reading look of an electronic Paper (e-Paper) display is similar to the feeling of reading a printed book and writing a printed book, so that a user feels comfortable when reading. In addition, compared with other display technologies, the electronic paper display has extremely low power consumption and is suitable for long-term use. Therefore, many technical solutions and applications related to electronic paper displays have been proposed in recent years.
Electronic paper displays are currently used in electronic billboards, mobile phone screens, or wearable electronic devices. However, in the event of a failure of the electronic paper display, the electronic paper display may display erroneous information, thereby causing the viewer to receive outdated information, or erroneous information. Therefore, it is necessary to provide an electronic paper display with a recovery mechanism to recover the correct display content when the electronic paper display displays an error message.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a display device with a recovery mechanism to recover correct display contents when the display displays an error message.
The application provides a display device with a recovery mechanism, wherein the display device with the recovery mechanism comprises a power supply, a super capacitor, a main controller, an auxiliary controller and a display;
the power supply is electrically connected with the super capacitor and is used for charging the super capacitor;
the super capacitor is respectively and electrically connected with the main controller and the display and used for supplying power to the main controller and the display;
the main controller is electrically connected with the display to perform display control on the display content of the display;
the auxiliary controller is electrically connected with the main controller and used for detecting the running state of the main controller and sending a setting control signal to set the main controller when the main controller is determined to be in an abnormal running state, so that the main controller returns to a normal running state.
Preferably, the display device with the reply mechanism further includes a constant current output control circuit, the constant current output control circuit includes an LED driver and a comparator, the power supply is electrically connected to the super capacitor through the LED driver, the comparator is electrically connected to the driver and the super capacitor, respectively, the comparator is configured to compare the current voltage of the super capacitor with a default reference voltage, and control the LED driver to enable and start when the voltage of the super capacitor is less than the default reference voltage, so that the power supply charges the super capacitor through the LED driver, and when the power supply charges the super capacitor, the power supply limits the current output to the super capacitor by the power supply through the LED driver.
Preferably, the LED driver includes an input terminal, an output terminal, and an enable terminal, the power supply is electrically connected to the input terminal of the LED driver, the first terminal of the super capacitor is connected to the output terminal of the LED driver, the second terminal of the super capacitor is electrically connected to the ground terminal, the first terminal of the super capacitor is a voltage output terminal of the super capacitor, the comparator includes a positive input terminal, a negative input terminal, and a voltage output terminal, the positive input terminal of the comparator is electrically connected to the voltage output terminal of the super capacitor, the negative input terminal of the comparator is connected to a voltage source having the default reference voltage, and the voltage output terminal of the comparator is connected to the enable terminal of the LED driver.
Preferably, the main controller includes a data output pin, a status detection pin, a power input pin, and a reset pin, the voltage output end of the super capacitor is electrically connected to the power input pin of the main controller for supplying power to the main controller, the data output pin is electrically connected to the display for providing display data to the display for displaying, the auxiliary controller includes a first status detection pin, a second status detection pin, a first control pin, and a second control pin, the status output pin of the main controller is electrically connected to the first status detection pin of the auxiliary controller, the status detection pin of the main controller is electrically connected to the first control pin of the auxiliary controller, the reset pin of the main controller is electrically connected to the second control pin of the auxiliary controller, when the main controller is not awakened, the state output pin of the main controller outputs a low level, and when the main controller is awakened, the state output pin of the main controller outputs a high level.
Preferably, the auxiliary controller counts time when detecting a high level output by a status output pin of the main controller through the first status detection pin; when the timing time that the state output pin of the main controller outputs the high level is detected to exceed first preset time, the auxiliary controller determines that the main controller is in an abnormal operation state and sends a low pulse signal to the state detection pin of the main controller; and when the state detection pin of the main controller receives a low pulse signal sent by the auxiliary controller, the main controller continuously completes the current thread operation or re-executes the current thread operation according to the low pulse signal, so that the main controller returns from the currently stopped thread operation to continuously execute and complete the subsequent thread operation.
Preferably, when the timing time when the state output pin of the main controller outputs the high level exceeds a second preset time, the auxiliary controller determines that the main controller is in an abnormal operation state, and sends a reset signal to the reset pin of the main controller through the second control pin, and the main controller executes a reset operation when receiving the reset signal.
Preferably, when the main controller wakes up, the main controller performs the following thread operations:
reading default online information from the main controller, and controlling communication connection with a server according to the online information;
sending a request signal or a notification signal to the server, and waiting for a return signal of the server;
receiving a return signal sent by the server, wherein the return signal comprises the time when the main controller is awakened next time and display picture information to be updated;
when the returned signal is determined not to include the display picture information to be updated, controlling the main controller to enter an un-awakened state, and waiting for the next awakening according to the time of the next awakened main controller in the returned signal; and
when the returned signal is determined to include the display picture information to be updated, the display picture information to be updated in the returned signal is stored in the main controller, and when the storage is completed, the display is informed to read the stored display picture information to be updated so as to be displayed on the display.
Preferably, the auxiliary controller further includes a second state detection pin, the second state detection pin is electrically connected to a voltage output terminal of the comparator to detect a potential of the voltage output terminal of the comparator, the auxiliary controller determines whether the abnormal operation state occurs in the main controller according to the potential detected by the second state detection pin, and generates a reset signal to a reset pin of the main controller when it is determined that the abnormal operation state occurs in the main controller, and the main controller executes a reset operation when receiving the reset signal.
Preferably, the auxiliary main controller judges whether the charging frequency of the super capacitor to the main controller is greater than one time within a third preset time according to the potential detected by the second state detection pin, and determines that the abnormal operation state occurs in the main controller when the charging frequency of the super capacitor to the main controller is greater than one time within the third preset time, wherein the third preset time is associated with the time for the main controller to complete one wake-up.
A second aspect of the present application provides a display device with a reply mechanism, the display device with the reply mechanism comprising:
a display module;
the main controller, coupled to the display module, switches between an operation mode and a low power operation mode, including:
the first timer is used for awakening the main controller at intervals of first preset time;
a state pin, wherein the state pin is switched from a first logic level to a second logic level when the host controller is switched from the low power operating mode to the operating mode;
receiving a pin position;
the auxiliary controller monitors whether the main controller is in an abnormal operation state or not, and comprises a second timer, when the state pin is switched from the first logic level to the second logic level, the second timer starts to time an enabling time of the main controller, wherein when the enabling time exceeds a first time, the auxiliary controller transmits a first signal to the receiving pin.
Preferably, the main controller further comprises a reset pin, and when the enable time exceeds the first time, the auxiliary controller transmits a reset signal to the main controller to reset the main controller.
Preferably, when the state pin is switched from the first logic level to the second logic level, the main controller performs the following actions:
reading online information stored in the storage device;
establishing network connection between the display device and the server according to the connection information:
and determining whether to update the display picture of the display device according to the data returned by the server.
Preferably, the data includes a wake-up time for the first timer to determine a time to wake up the main controller.
Preferably, the display device with a reply mechanism further comprises:
the constant current output driver is coupled with the power supply input end of the main controller; and
the super capacitor is coupled with the constant current output driver and the power supply input end;
when the status pin is at the first logic level, the auxiliary controller monitors whether the voltage change at the power input end is abnormal, and if the voltage change is abnormal, the auxiliary controller transmits a reset signal to the main controller to reset the main controller.
Preferably, the display device with a reply mechanism further comprises:
a comparator, comprising:
the output end is coupled with the constant current output driver;
a first input terminal coupled to the power input terminal; and
the second input end is coupled with a reference voltage, when the voltage of the power supply input end is lower than the reference voltage, the output end is switched from the first logic level to the second logic level, and the constant current output driver is conducted to charge the super capacitor.
Preferably, if the number of times that the constant current output driver is turned on is greater than a predetermined value within a second predetermined time, the auxiliary controller transmits a reset signal to the main controller to reset the main controller.
The auxiliary controller detects the running state of the main controller and sends a setting control signal to set the main controller when the main controller is determined to be in an abnormal running state, so that the display content with errors on the display can be recovered to be correct.
Drawings
Fig. 1 is a schematic diagram of a display device with a recovery mechanism according to an embodiment of the invention.
Fig. 2 is a circuit diagram of a display device according to an embodiment of the invention.
Fig. 3 is a flowchart illustrating an operation of the display device according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of another embodiment of a display device according to an embodiment of the invention.
Fig. 5 is a schematic diagram of voltage variation of the voltage output terminal of the super capacitor in fig. 2 after the main controller is awakened.
FIG. 6 is a flowchart illustrating operations of an auxiliary controller in a display device according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating another embodiment of a display device according to an embodiment of the present invention.
Description of the main elements
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application.
All other embodiments that can be obtained by a person skilled in the art without inventive step based on the embodiments in this application are within the scope of protection of this application.
Referring to fig. 1, a schematic diagram of a display device 1 with a recovery mechanism according to an embodiment of the invention is shown. The display device 1 includes a power supply 11, a super capacitor 12, a main controller 13, an auxiliary controller 14, a display 15, a constant current output control circuit 16, a memory 17, and a communication unit 18 (refer to fig. 2). In this embodiment, the power supply 11 is electrically connected to the super capacitor 12 for charging the super capacitor 12. The super capacitor 12 is electrically connected to the main controller 13 and the display 15 respectively, so as to supply power to the main controller 13 and the display 15. The main controller 13 is electrically connected to the display 15 to perform display control on the display content of the display 15. The auxiliary controller 14 is electrically connected to the main controller 13, and is configured to detect an operation state of the main controller 13, and send a setting control signal to set the main controller 13 when it is determined that the main controller 13 is in an abnormal operation state, so that the main controller 13 returns to a normal operation state. In this embodiment, the power source 11 is a battery or a solar panel, the super capacitor 12 is a super capacitor, and the display 15 is an electronic paper display.
In the present embodiment, the constant current output control circuit 16 is electrically connected to the power supply 11 and the super capacitor 12, respectively. The constant current output control circuit 16 includes an LED driver 161 and a comparator 162. The power supply 11 is electrically connected to the super capacitor 12 through the LED driver 161. When the power supply 11 charges the super capacitor 12, the LED driver 161 limits the current output from the power supply 11 to the super capacitor 12, so as to protect the power supply 11 and prolong the service life of the power supply 11. In the present embodiment, the comparator 162 is electrically connected to the driver 61 and the super capacitor 12, respectively. The comparator 162 is configured to compare the current voltage of the super capacitor 12 with a default reference voltage, and control the LED driver 161 to enable and start when the voltage of the super capacitor 12 is less than the default reference voltage, so that the power supply 11 charges the super capacitor 12 through the LED driver 161.
Referring to fig. 2, a circuit diagram of the display device 1 according to an embodiment of the invention is shown. The LED driver 161 includes an input terminal 1611, an output terminal 1612, and an enable terminal 1613. The power supply 11 is electrically connected to the input 1611 of the LED driver 161. The first end 121 of the super capacitor 12 is connected to the output end 1612 of the LED driver 161, and the second end 122 of the super capacitor 12 is electrically connected to the ground GND. In this way, the power supply 11 charges the super capacitor 12 through the LED driver 161, and the first end 121 of the super capacitor 12 is a voltage output end of the super capacitor 12VBUS。
In this embodiment, the comparator 162 includes a positive input terminal 1621, a negative input terminal 1622, and a voltage output terminal 1623. The positive input end 1621 of the comparator 162 and the voltage output end V of the super capacitor 12BUSAnd (6) electrically connecting. Specifically, the voltage output end V of the super capacitor 12BUSIs electrically connected to the positive input 1621 of the comparator 162 through an input resistor. The negative input 1622 of the comparator 162 is connected to a voltage source having a default reference voltage. In this embodiment, the default reference voltage is 3.2V. The voltage output terminal 1623 of the comparator 162 is connected to the enable terminal 1613 of the LED driver 161. In this way, the comparator 162 compares the voltage of the positive input terminal 1621 with the voltage of the negative input terminal 1622, and when the voltage of the positive input terminal 1621 is less than the voltage of the negative input terminal 1622, the enable signal converted from low level to high level is output through the enable terminal 1613, and the LED driver 161 is controlled to be enabled and started by the enable signal, so that the power supply 11 charges the super capacitor 12 through the LED driver 161.
In this embodiment, the main controller 13 includes a data output pin Date _ out, a status output pin SOP2, a status detection pin UARTO _ RX, a power input pin Vcc, a Reset pin Reset, and a timer 131. The voltage output end V of the super capacitor 12BUSIs electrically connected to a power input pin Vcc of the main controller 13 for supplying power to the main controller 13. The data output pin Date _ out is electrically connected to the display 15 for providing display data to the display 15 for the display 15 to display. In this embodiment, the voltage output end V of the super capacitor 12BUSIs connected to the display 15 for supplying said display 15 with power.
The auxiliary controller 14 includes a first status detection pin C1, a second status detection pin C2, a first control pin C3 and a second control pin C4. The state output pin SOP2 of the main controller 13 is electrically connected with the first state detection pin C1 of the auxiliary controller 14. The status detection pin UARTO _ RX of the main controller 13 is electrically connected to the first control pin C3 of the auxiliary controller 14. In this embodiment, the state output pin SOP2 outputs a low level when the main controller 13 is not woken up, and the state output pin SOP2 outputs a high level when the main controller 13 is woken up. When the auxiliary controller 14 detects a high level output from the state output pin SOP2 of the main controller 13 through the first state detection pin C1, it counts time through the timer 131, and generates a low pulse signal when the counted time of the state output pin SOP2 outputting the high level exceeds a first preset time, and sends the generated low pulse signal to the state detection pin UARTO _ RX of the main controller 13 through the first control pin C3.
In the present embodiment, when the main controller 13 is woken up, the main controller 13 executes the following thread operation.
1) The main controller 13 reads default connection information from the memory 17 and controls the communication unit 18 to be in communication connection with a server (not shown) according to the connection information. In this embodiment, the communication unit 18 is a WiFi communication module, and the main controller 13 is connected to the server through the WiFi communication module according to the read online information.
2) The master controller 13 sends a request signal or a notification signal to the server and waits for a signal returned by the server.
3) The main controller 13 receives a return signal sent by the server, where the return signal includes a time when the main controller is awakened next time and display screen information to be updated.
4) When it is determined that the return signal does not include the display picture information to be updated, the main controller 13 controls the main controller 13 to enter an un-awakened state (sleep state), and waits for the next awakening according to the time of the next awakening of the main controller in the return signal.
5) When it is determined that the display screen information to be updated is included in the return signal, the main controller 13 stores the display screen information to be updated in the return signal in the memory 17, and when the storage is completed, notifies the display 15 to read the display screen information to be updated in the memory 17 to display on the display 15.
In this embodiment, when the status detection pin UARTO _ RX of the main controller 13 receives the low pulse signal sent by the auxiliary controller 14, the main controller 13 continues to execute the current thread operation or re-executes the current thread operation. In this embodiment, after the main controller 13 is awakened, the main controller 13 usually completes the above-mentioned 1-5 thread operations within a first preset time (i.e. 2 seconds). However, when the main controller 13 has an unexpected event while executing a certain thread operation, for example, when the main controller 13 of the main controller 13 has not received a return signal sent by the server after sending a request signal or a notification signal to the server, the thread operation currently running by the main controller 13 is stopped, the state output pin SOP2 of the main controller 13 always outputs a high level and the main controller 13 is always in a wake-up state, so that the main controller 13 is abnormal in operation and the display 15 cannot update the display content.
In this embodiment, when the auxiliary controller 14 detects that the timing time when the state output pin SOP2 of the main controller 13 outputs the high level exceeds a first preset time, the auxiliary controller 14 determines that the main controller 13 is in the abnormal operation state, and sends a low pulse signal to the main controller 13. When the status detection pin UARTO _ RX of the main controller 13 receives the low pulse signal sent by the auxiliary controller 14, the main controller 13 continues to complete the current thread operation or re-execute the current thread operation according to the low pulse signal, so that the main controller 13 replies from the currently stopped thread operation to continue executing and complete the subsequent thread operation. In this embodiment, the first preset time is 2 seconds.
In this embodiment, when the time for detecting the state output pin SOP2 of the main controller 13 outputting the high level exceeds the first preset time, the auxiliary controller 14 continuously sends the low pulse signal to the main controller 13 through the first control pin C3 until detecting the state output pin SOP2 of the main controller 13 outputting the low level. Specifically, the auxiliary controller 14 sends a low pulse signal to the main controller 13 through the first control pin C3 every 1 second period until detecting that the state output pin SOP2 of the main controller 13 outputs a low level. In the present embodiment, the auxiliary controller 14 is always in an enabled state. In other embodiments, the auxiliary controller 14 is enabled only when it detects that the state output pin SOP2 of the main controller 13 outputs a high level.
In this embodiment, when the timing time when the state output pin SOP2 outputs the high level exceeds a second preset time, the auxiliary controller 14 determines that the main controller 13 is in the abnormal operation state, and sends a Reset signal to the Reset pin Reset of the main controller 13 through the second control pin C4. The main controller 13 performs a reset operation upon receiving the reset signal. In this embodiment, the main controller 30 executing the reset operation means executing the above-mentioned thread operations 1 to 5. In this embodiment, the second preset time is 20 seconds.
In this embodiment, when the state output pin SOP2 on the main controller 13 outputs a low level, the main controller 13 is normally in an un-wake state and is not enabled, but the state output pin SOP2 outputs a low level but the main controller 13 is in an abnormal operation state of waking up due to an unexpected error of the main controller 13. To avoid the above abnormal operation of the main controller 13, the second state detection pin C2 of the auxiliary main controller 40 is electrically connected to the voltage output terminal 1623 of the comparator 60 for detecting the potential of the voltage output terminal 1623 of the comparator 162. The auxiliary controller 14 determines whether the abnormal operation state occurs according to the potential detected by the second state detection pin C2, and generates the Reset signal to the Reset pin Reset of the main controller 13 when determining that the abnormal operation state occurs, so that the main controller 13 executes the above-mentioned thread operations 1-5 upon receiving the Reset signal. In this embodiment, the auxiliary main controller 40 determines whether the number of times of charging the main controller 13 by the super capacitor 12 is greater than one time within a third preset time according to the potential detected by the second state detection pin C2, and determines that the main controller 13 is in an abnormal operation state when the number of times of charging the main controller 13 by the super capacitor 12 is greater than one time within the third preset time. The third preset time is associated with a time when the main control 30 completes one wake-up. In this embodiment, the third preset time is 20 seconds.
Specifically, in this embodiment, when the state output pin SOP2 of the main controller 13 outputs a low level and the main controller 13 is in an un-awakened state, the voltage output terminal V of the super capacitor 12BUSMaintained at 3.2V for a long time. When in the third preset time (i.e. the time when the main controller 30 completes one wake-up), the super capacitor 12 only needs to charge the main controller 13 once.
Referring to fig. 3, a flowchart of a display device according to an embodiment of the invention is shown.
The circuit diagram of the display device 1 of the present application will be described as an example.
Step S401: the main controller 13 controls the display content of the display 15 according to the return signal sent by the server.
Step S402: the auxiliary controller 14 detects the voltage level of the SOP2 of the main controller 13 and determines whether the SOP2 is high. The step S403 is performed when the state output pin SOP2 is low, and the step S405 is performed when the state output pin SOP2 is low.
Step S403: the assist controller 14 determines whether the main controller 13 is in the awake state. In the present embodiment, step S404 is executed when the main controller 13 is in the wake-up state, and step S402 is executed when the main controller 13 is not in the wake-up state.
Step S404: the auxiliary controller 14 sends a Reset signal to a Reset pin Reset of the main controller 13, so that the main controller 13 performs a Reset operation according to the Reset signal.
Step S405: the auxiliary controller 14 determines whether the state of the state output pin SOP2 of the main controller 13 being at the high level exceeds a first preset time. The step S406 is executed when the state of the state output pin SOP2 of the main controller 13 being at the high level exceeds the first preset time, otherwise, the step S405 is continuously executed.
Step S406: the auxiliary controller 14 sends a low pulse signal to the main controller 13, so that the main controller 13 continues to complete the current thread operation or re-execute the current thread operation according to the low pulse signal. Thereby causing the main controller 13 to resume execution and complete subsequent thread operations in return from the currently stopped thread operation.
Step S407: the auxiliary controller 14 determines whether the state of the state output pin SOP2 of the main controller 13 being at the high level exceeds a second preset time. In this embodiment, the step S404 is executed when the state of the state output pin SOP2 of the main controller 13 being at the high level exceeds the second preset time, otherwise, the step S406 is executed.
In this embodiment, when the auxiliary controller 14 determines that the state of the state output pin SOP2 of the main controller 13 being at the high level exceeds the first preset time, it sends a low pulse signal to the main controller 13, so that the main controller 13 continues to complete the current thread operation or re-executes the current thread operation according to the low pulse signal, and thus the main controller 13 returns from the currently stopped thread operation to continue to execute and complete the subsequent thread operation. In addition, the auxiliary controller 14 sends a Reset signal to the Reset pin Reset of the main controller 13 when determining that the state of the state output pin SOP2 of the main controller 13 is at the high level exceeds a second preset time, so that the main controller 13 executes the above-mentioned thread operations 1-5 when receiving the Reset signal. Thus, when an error occurs in the main controller 13, the main controller 13 is controlled by the auxiliary controller 14 to perform a recovery operation, so that correct display contents can be restored when the error information occurs in the display contents on the display 15 due to an abnormality in the main controller 13.
Fig. 4 is a schematic diagram of another embodiment of the display device 1 according to the invention. The display device 1 includes a battery 41, a constant current output circuit 42, a super capacitor 43, a main controller 44, a comparator 45, an auxiliary controller 46, a storage device 47, a wireless module 48, and an electronic paper display 49.
In the present embodiment, the main controller 44, the auxiliary controller 46, the wireless module 48 and the electronic paper display 49 are mainly powered by the super capacitor 43 and the battery. Under normal conditions, the main controller 44 will wake up at intervals, such as 10 minutes, based on the built-in RTC (real time counter). Except during the wake-up period, the main controller 44 is in a sleep or low power mode of operation at all times. However, the auxiliary controller 46 continues to operate and monitors the status of the main controller 44. In this embodiment, the auxiliary controller 46 operates to consume much less power than the main controller 44. In other words, the main controller 44 switches between the operation mode and the sleep/low power operation mode to reduce the power consumption of the display device 1.
Another advantage of using the super capacitor 43 is that it can provide a large current required when the main controller 44 is awakened or the electronic paper display 49 performs a picture update, so that the battery 41 can be prevented from drawing an excessive current instantaneously, thereby reducing the usage time.
When the main controller 44 of the display device 1 is in a sleep mode, the constant current output circuit 42 is turned off, and the components inside the display device 1, such as the capacitor 4, the comparator 45, and the auxiliary controller 46, are powered by the super capacitor 43. After the main controller 44 is awakened, a series of processes are executed, thereby consuming the super capacitor 43, so that the voltage output terminal VBUS is lowered, and when the divided voltage of the voltage output terminal VBUS is lower than the reference voltage, the output signal VmEn of the comparator 45 is changed from the first voltage level to the second voltage level, and the constant current output circuit 42 is enabled, so that the battery 41 charges the super capacitor 43 and provides power to other components. In one embodiment, the constant current output circuit 42 is an LED driver. The constant current output circuit 42 is used for limiting the output current of the battery 41 to be less than or equal to a predetermined current. When the voltage output terminal VBUS is greater than a voltage, the output signal VmEn of the comparator 45 changes from the second voltage level to the first voltage level to turn off the constant current output circuit 42.
To more clearly illustrate the variation of the voltage output terminal VBUS, please refer to fig. 5, in which fig. 5 is a schematic diagram illustrating the variation of the voltage output terminal when the display device 1 according to the present invention operates. In this embodiment, the minimum operating voltage of the main controller 44 is 2.6V. When the voltage of the comparator 45 is lower than 2.8V, the output signal VmEn changes from the first voltage level to the second voltage level, such as from a logic low voltage level to a logic high voltage level.
At time t1, the main controller 44 wakes up and the super capacitor 43 draws more power, so the voltage output terminal VBUS is decreased faster. At time t2, the voltage output terminal VBUS is lower than 2.8V, and the comparator 45 enables the constant current output circuit 42, where the components in the display device 1 are supplied with power from the battery 41 and the super capacitor 43 is charged. At this time, the voltage output terminal VBUS still drops a little and then slowly increases.
At a time point t3, the main controller 44 enters the sleep mode, in which the rising speed of the voltage output terminal VBUS becomes fast. At time t3, the voltage output terminal VBUS is higher than 3.5V, and the comparator 45 turns off the constant current output circuit 42, so that the battery 41 stops charging the super capacitor 43. At this time, the voltage output terminal VBUS still rises for a period of time, and then starts to gradually decrease.
When the main controller 44 wakes up, the following thread (thread) is executed, and after finishing, the sleep mode is entered again.
1. Reads the connection information in the storage device 47, and establishes a network connection (network connection) between the wireless module 48 and the server according to the connection information.
2. Sends a request (request) or an acknowledge (Ack) signal to the server and waits for the server to send back a signal.
3. The server sends back to the main controller 44 a data including the time when the main controller is woken up next time, (e.g. 10 minutes or 20 minutes, for the RTC to count down), and whether the e-paper display needs to update the screen.
The time that the server returns the main controller 44 to be awakened is not the actual time, such as 10 o' clock and 10 minutes, but is a reciprocal time, such as 10 minutes and 20 minutes. In this way, the server can dynamically adjust the time when the display apparatus 1 updates data. In another embodiment, the server may return a time table over a fixed time, recording the time each time the RTC wakes up the master controller 44.
4-1. if the main controller 44 determines that the display device 1 does not need to update the screen, the main controller 44 enters the sleep mode and waits to be woken up by the RTC.
4-2. if the main controller 44 determines that the screen needs to be updated, the main controller 44 receives the update data through the wireless module 48 and directly stores the update data in another storage device. After the storage is completed, the main controller 44 notifies the electronic paper display to read the data in the storage device and update the picture of the electronic paper display 49. When the electronic paper display 49 finishes updating the screen, it notifies the main controller 44, and then the main controller 44 enters the sleep mode to wait for being woken up by the RTC.
Generally, when the main controller 44 wakes up, if the screen is not updated, it will complete all the processes and enter the sleep mode within 2 seconds. If there is an update screen, it will complete all the procedures, typically 10 seconds. Moreover, when the main controller 44 is woken up, the SOP2 on the SOP pin 44 is pulled high from a logic low level to a logic high level, so that the auxiliary controller 46 can know the current state of the main controller 44 by detecting the logic state of the SOP 2.
In this embodiment, the auxiliary controller 46 is continuously on, so the main controller 44 can be monitored by the auxiliary controller 46. In one embodiment, when the SOP2 is pulled from logic low to logic high, a timing function of the auxiliary controller 46 is enabled and starts timing the time that the main controller 44 is enabled. As mentioned above, the main controller normally completes all operations for about 10 seconds, so the auxiliary controller 46 can set a first time and a second time and send different signals to the main controller 44 to ensure the main controller 44 operates normally.
In one embodiment, the first time is 3 seconds and the second time is 12 seconds. When the auxiliary controller 46 detects that the enabled time of the main controller 44 exceeds the first time, the auxiliary controller 46 sends a first signal to the UART0_ RX pin of the main controller 44, and the main controller 44 may have two actions to return the main controller 44 from the possible abnormal state to the normal state.
The first action is as follows: let the current thread proceed
And the second action: resetting the current thread
In one action, the main controller 44 continues to complete the thread when the main controller 44 receives the first signal from the auxiliary controller 46 because the main controller 44 may suspend operation (halt) due to unexpected conditions. However, in action two, the main controller 44 re-executes the thread in execution. Taking the above-mentioned thread as an example, when the auxiliary controller 46 detects that the enabled time of the main controller 44 exceeds the first time and the main controller 44 is running in the thread, the auxiliary controller 46 sends a first signal to the UART0_ RX pin of the main controller 44, and the main controller 44 sends a request (request) or a notification (Ack) signal to the server again and waits for the server to return the signal. If action one is the case, the main controller 44 does not re-execute the thread, but rather continues to wait for a return signal from the server. In one embodiment, the first signal is a pulse signal.
In another embodiment, if the secondary controller 46 finds that the main controller 44 has been operating for more than a second time, the main controller 44 may re-execute the current thread. In one embodiment, the number of times the first signal is received during the operation of each thread is recorded in the main controller 44, and the number is reset to zero and recalculated once the next thread is reached. When the number of times received during the execution of the same thread is greater than a predetermined number of times, main controller 44 re-executes the thread. It is to be noted that the present operation is an operation performed by the main controller 44 itself, and is not instructed by the auxiliary controller 46.
In this embodiment, if the auxiliary controller 46 finds that the working time of the main controller 44 exceeds a third time, such as 20 seconds, and the main controller 44 has not entered the sleep mode, the auxiliary controller 46 will issue a RESET signal to the RESET pin RESET of the main controller 44, and the main controller 44 is RESET, and the above-mentioned thread 1 will start to execute sequentially again.
In the above embodiment, the auxiliary controller 46 is continuously maintained in the operating mode, and the main controller 44 is switched between the operating mode and the sleep mode, because the auxiliary controller 46 consumes less power in the operating mode than the main controller 44, the energy saving purpose can be achieved. In another embodiment, the auxiliary controller 46 can also operate in a sleep mode, and the status output pin SOP2 of the main controller 44 is connected to an enable pin of the auxiliary controller 46, and once the status output pin SOP2 of the main controller 44 is connected, the auxiliary controller 46 is enabled to monitor whether the main controller 44 is operating normally.
In the above embodiments, the abnormal condition of the state output pin SOP2 of the main controller 44 being at the high logic level is described, but an abnormality of the state output pin SOP2 being at the low logic level may also occur when the main controller 44 is operating. Therefore, to avoid such an abnormal condition, the auxiliary controller 46 monitors the voltage output terminal VBUS to determine whether an abnormality occurs. In the embodiment, the auxiliary controller 46 does not directly monitor the voltage output terminal VBUS, but detects the output signal of the comparator 45. In another embodiment, the auxiliary controller 46 may directly monitor the voltage output terminal VBUS.
As previously mentioned, if the main controller 44 is in the sleep mode, the voltage output VBUS may be lowered at a slow rate, but not below the predetermined 2.8V. Therefore, if the auxiliary controller 46 determines that the main controller 44 is in the sleep mode and the voltage output VBUS is lower than the default value, this indicates abnormal power consumption, so the auxiliary controller 46 sends a reset signal to the main controller 44. When the main controller 44 receives the reset signal, it re-initializes and the constant current output driver charges the super capacitor 43 and provides power to the components in the display device 1.
Under normal conditions, the main controller 44 will wake up and connect to the server at intervals, such as 10 minutes, to determine whether the screen needs to be updated. So that only in this case the voltage output terminal VBUS will drop relatively fast. Therefore, if the output signal of the comparator 45 changes abnormally in a short time, it can be determined that there is a possibility that the display device 1 is abnormal at this time. Therefore, in the present embodiment, the auxiliary controller 46 detects the duty cycle of the VmEn signal or whether a predetermined time, such as 1 second to 20 seconds, is asserted when the state output pin SOP2 is at the low logic level. If so, it indicates that the main controller is abnormal, at this time, the auxiliary controller will send a RESET signal to the RESET pin RESET of the main controller, at this time, the main controller is RESET, and the execution will be started again by the previous thread 1.
FIG. 6 is a flowchart illustrating the operation of the auxiliary controller in the display device 1 according to the present invention. The following description will be given with reference to the display device 1 shown in fig. 4.
Step S61: the auxiliary controller 46 detects the logic state of the SOP2 to determine whether the main controller 44 is currently operating. If yes, go to step S62; if not, step S63 is executed.
Step S62: the auxiliary controller 46 starts timing the enable time of the main controller 44 and determines whether the enable time of the main controller 44 is greater than a first time. If yes, go to step S63; if not, step S65 is executed: the supplementary controller 46 keeps timing the enable time of the main controller 44.
Step S63: the auxiliary controller 46 sends a continuous pulse signal to the main controller 44.
Step S64: the auxiliary controller 46 determines whether the main controller 44 is enabled for a time greater than a third time. If yes, go to step S67; if not, step S65 is executed: the supplementary controller 46 keeps timing the enable time of the main controller 44.
Step S66: the auxiliary controller 46 detects the output signal of the comparator 45 to determine whether there is an abnormal charging condition. If yes, go to step S67; if not, step S68 is executed: the auxiliary controller 46 continuously monitors whether there is a change in the output signal of the comparator 45.
Step S67: the auxiliary controller 46 sends a RESET signal to the RESET pin RESET of the main controller 44, and the main controller 44 is RESET, and the above steps are executed again in sequence.
Referring to fig. 7, a schematic diagram of a display device 1 according to another embodiment of the invention is shown. The display device 1 includes a display module 71, a main controller 72, and an auxiliary controller 73. The main controller 72 is coupled to the display module 71 for switching between an operation mode and a low power operation mode. In this embodiment, the main controller 72 includes a first timer 721, a status pin 722, and a receiving pin 723. The first timer 721 is used to wake up the main controller 72 every first predetermined time. When the main controller 72 switches from the low power operation mode to the operation mode, the state pin 722 switches from a first logic level to a second logic level. The auxiliary controller 73 is used for monitoring whether the main controller 72 is in an abnormal operation state. In this embodiment, the auxiliary controller 73 includes a second timer 731. When the status pin 722 switches from the first logic level to the second logic level, the second timer 731 starts to count an enable time of the main controller 72, wherein the auxiliary controller 73 sends a first signal to the receiving pin when the enable time exceeds a first time.
In one embodiment, the main controller 72 further includes a reset pin 724 and a power input 725, and the auxiliary controller 73 sends a reset signal to the main controller 72 to reset the main controller 72 when the enable time exceeds a first time. In this embodiment, when the state pin 722 is switched from the first logic level to the second logic level, the main controller 72 performs the following operations: reading online information stored in a storage device; establishing a network connection between the display device and a server according to the connection information: and the main control determines whether to update the display picture of the display device according to data returned by the server. In this embodiment, the data includes a wake-up time for the first timer 721 to determine the time for waking up the main controller 72.
In one embodiment, the display device 1 further includes a constant current output driver 74 and a super capacitor 75. The constant current output driver 74 is coupled to a power input 725 of the main controller 72. The super capacitor 75 is used to couple the constant current output driver 74 and the power input 725. When the status pin 722 is at the first logic level, the auxiliary controller 73 monitors whether the voltage variation of the power input terminal 725 is abnormal, and if the voltage variation is abnormal, the auxiliary controller 73 transmits a reset signal to the main controller 72 to reset the main controller 72.
In an embodiment, the display device 1 further comprises a comparator 76. The comparator 76 includes an output 761, a first input 762, and a second input 763. The comparator 76 is coupled to the constant current output driver 74. The first input 762 is coupled to the power input 725. The second input 763 is coupled to a reference voltage. When the voltage at the power input 725 of the main controller 72 is lower than the reference voltage, the output 761 is switched from the first logic level to the second logic level, and the constant current output driver 74 is turned on to charge the super capacitor 75. In this embodiment, if the number of times that the constant current output driver 74 is turned on is greater than a predetermined value within a second predetermined time, the auxiliary controller 73 transmits a reset signal to the main controller 72 to reset the main controller 72.
It should be understood by those skilled in the art that the above embodiments are only for illustrating the present application and are not used as limitations of the present application, and that suitable modifications and changes of the above embodiments are within the scope of the claims of the present application as long as they are within the spirit and scope of the present application.
Claims (16)
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| CN202010349764.7A CN113571003A (en) | 2020-04-28 | 2020-04-28 | Display device with recovery mechanism |
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| CN114253381A (en) * | 2021-12-23 | 2022-03-29 | 厦门四信通信科技有限公司 | An electronic device and its abnormal reset circuit |
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Application publication date: 20211029 |